MM74C76NBPLUS [FAIRCHILD]
J-K Flip-Flop, CMOS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16;
| 型号： | MM74C76NBPLUS |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | J-K Flip-Flop, CMOS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16 振荡器 |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1987
Revised January 1999
MM74C73 • MM74C76
Dual J-K Flip-Flops with Clear and Preset
General Description
Features
The MM74C73 and MM74C76 dual J-K flip-flops are mono-
lithic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement transistors.
Each flip-flop has independent J, K, clock and clear inputs
and Q and Q outputs. The MM74C76 flip flops also include
preset inputs and are supplied in 16 pin packages. This
flip-flop is edge sensitive to the clock input and change
state on the negative going transition of the clock pulse.
Clear or preset is independent of the clock and is accom-
plished by a low level on the respective input.
■ Supply voltage range: 3V to 15V
■ Tenth power TTL compatible: Drive 2 LPTTL loads
■ High noise immunity: 0.45 VCC (typ.)
■ Low power: 50 nW (typ.)
■ Medium speed operation: 10 MHz (typ.)
Applications
•
•
•
•
•
•
•
•
Automotive
Data terminals
Instrumentation
Medical electronics
Alarm systems
Industrial electronics
Remote metering
Computers
Ordering Code:
Order Number Package Number
Package Description
MM74C73N
MM74C76M
MM74C76N
N14A
M16A
N16E
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
MM74C73
MM74C76
Note: A logic “0” on clear sets Q to a logic “0”.
Note: A logic “0” on preset sets Q to a logic “1”.
Note: A logic “0” on clear sets Q to logic “0”.
Top View
Top View
© 1999 Fairchild Semiconductor Corporation
DS005884.prf
www.fairchildsemi.com
Truth Tables
tn
tn+1
Preset
Clear
Qn
Qn
J
0
0
1
K
0
1
0
1
Q
Qn
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
Qn
(Note 1)
Qn
(Note 1)
1
Qn
Note 1: No change in output from previous state
t
t
= bit time before clock pulse
n
= bit time after clock pulse
n+1
Logic Diagrams
MM74C73
MM74C76
Transmission Gate
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2
Absolute Maximum Ratings(Note 2)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature
Power Dissipation
Dual-In-Line
−0.3V to VCC + 0.3V
−40°C to +85°C
−65°C to +150°C
700 mW
500 mW
Small Outline
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of Electrical Characteristics provides
conditions for actual device operation.
Lead Temperature
(Soldering, 10 seconds)
Operating VCC Range
VCC (Max)
260°C
+3V to 15V
18V
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
V
V
V
V
V
V
V
= 5V
3.5
8
V
V
IN(1)
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
= 5V
1.5
2
V
IN(0)
= 10V
= 5V
V
4.5
9
V
OUT(1)
OUT(0)
= 10V
= 5V
V
0.5
1
V
= 10V
= 15V
= 15V
= 15V
V
I
I
I
Logical “1” Input Current
Logical “0” Input Current
Supply Current
1
µA
µA
µA
IN(1)
IN(0)
CC
−1
0.050
60
LOW POWER TTL TO CMOS INTERFACE
V
V
V
V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
V
V
V
V
= 4.75V
= 4.75V
V − 1.5
CC
V
V
V
V
IN(1)
CC
CC
CC
CC
0.8
0.4
IN(0)
= 4.75V, I = −360 µA
2.4
OUT(1)
OUT(0)
O
= 4.75V, I = 360 µA
O
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
I
I
I
I
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
V
= 5V, V
IN(0)
= 0V
= 0V
−1.75
−8
mA
mA
mA
mA
SOURCE
SOURCE
SINK
CC
T
= 25°C, V
OUT
A
V
= 10V, V
= 0V
= 0V
CC
IN(0)
OUT
T
= 25°C, V
A
V
= 5V, V
= 5V
1.75
8
CC
IN(1)
T
= 25°C, V
= V
A
OUT CC
V
= 10V, V
= 10V
SINK
CC
IN(1)
OUT
T
= 25°C, V
= V
A
CC
3
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AC Electrical Characteristics (Note 3)
T
A = 25°C, C = 50 pF, unless otherwise noted
L
Symbol
Parameter
Input Capacitance
Conditions
Min
Typ
Max
Units
C
Any Input
5
pF
ns
ns
IN
t
, t
Propagation Delay Time to a
V
= 5V
180
70
300
pd0 pd1
CC
CC
Logical “0” or Logical “1” from
V
= 10V
110
Clock to Q or Q
t
t
t
t
t
t
t
Propagation Delay Time to a
Logical “0” from Preset or Clear
Propagation Delay Time to a
Logical “1” from Preset or Clear
Time Prior to Clock Pulse that
Data must be Present
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 5V
200
80
300
130
300
130
175
70
ns
ns
pd0
pd
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 10V
= 5V
200
80
ns
= 10V
= 5V
ns
110
45
ns
S
= 10V
= 5V
ns
Time after Clock Pulse that J
and K must be Held
−40
−20
120
50
0
ns
H
= 10V
= 5V
0
ns
Minimum Clock Pulse Width
190
80
ns
PW
PW
MAX
t
= t
= 10V
= 5V
ns
WL
WH
Minimum Preset and Clear
Pulse Width
90
130
60
ns
= 10V
= 5V
40
ns
Maximum Toggle Frequency
2.5
7
4
MHz
MHz
µs
= 10V
= 5V
11
t , t
Clock Pulse Rise and Fall Time
15
5
r
f
= 10V
µs
Note 3: AC Parameters are guaranteed by DC correlated testing.
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4
AC Test Circuit
Switching Time Waveforms
CMOS to CMOS
t
= t = 20 ns
f
r
Typical Applications
Ripple Binary Counters
Shift Registers
74C Compatibility
Guaranteed Noise Margin
as a Function of VCC
5
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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