MM74HC04_05 [FAIRCHILD]
Hex Inverter; 六反相器
| 型号： | MM74HC04_05 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Hex Inverter |
| 文件： | 总7页 (文件大小：84K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised January 2005
MM74HC04
Hex Inverter
General Description
Features
The MM74HC04 inverters utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits.
■ Typical propagation delay: 8 ns
■ Fan out of 10 LS-TTL loads
■ Quiescent power consumption: 10 µW maximum at
room temperature
The MM74HC04 is a triple buffered inverter. It has high
noise immunity and the ability to drive 10 LS-TTL loads.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
■ Low input current: 1 µA maximum
Ordering Code:
Package
Order Number
Package Description
Number
MM74HC04M
M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC04M_NL
MM74HC04SJ
MM74HC04MTC
MM74HC04MTC_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
MM74HC04N
N14A
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
MM74HC04N_NL
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Logic Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
1 of 6 Inverters
Top View
© 2005 Fairchild Semiconductor Corporation
DS005069
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
6
V
V
)
VCC
)
)
)
±25 mA
Operating Temperature Range (TA) −40 +85
°C
)
±50 mA
Input Rise or Fall Times
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf)
V
CC = 2.0V
1000
500
ns
ns
ns
V
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
3.15
4.2
VIL
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level
Output Voltage
V
IN = VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN = VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
VOL
Maximum LOW Level
Output Voltage
V
IN = VIH
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
IIN
Maximum Input
Current
VIN = VCC or GND
±1.0
µA
ICC
Maximum Quiescent
Supply Current
V
IN = VCC or GND
6.0V
2.0
20
40
µA
I
OUT = 0 µA
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC=5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current
(IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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2
AC Electrical Characteristics
V
CC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol Parameter
tPHL, tPLH
Guaranteed
Limit
Conditions
Typ
Units
Maximum Propagation
Delay
8
15
ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
tPHL, tPLH
Parameter
Conditions
Units
Typ
55
11
9
Guaranteed Limits
Maximum Propagation
Delay
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
95
120
24
20
95
19
16
145
29
ns
ns
ns
ns
ns
ns
pF
19
16
75
15
13
24
tTLH, tTHL
Maximum Output Rise
and Fall Time
30
8
110
22
7
19
CPD
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
(per gate)
20
CIN
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCC f + ICC
I
.
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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