MM74HC151N [FAIRCHILD]
8-Channel Digital Multiplexer; 8通道数字多路复用器
| 型号： | MM74HC151N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Channel Digital Multiplexer |
| 文件： | 总7页 (文件大小：74K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised February 1999
MM74HC151
8-Channel Digital Multiplexer
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
General Description
The MM74HC151 high speed Digital multiplexer utilizes
advanced silicon-gate CMOS technology. Along with the
high noise immunity and low power dissipation of standard
CMOS integrated circuits, it possesses the ability to drive
10 LS-TTL loads. The MM74HC151 selects one of the 8
data sources, depending on the address presented on the
A, B, and C inputs. It features both true (Y) and comple-
ment (W) outputs. The STROBE input must be at a low
logic level to enable this multiplexer. A high logic level at
the STROBE forces the W output HIGH and the Y output
LOW.
Features
■ Typical propagation delay data select to output Y: 26 ns
■ Wide operating supply voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent supply current: 80 µA maximum (74HC)
■ High output drive current: 4 mA minimum
Ordering Code:
Order Number Package Number
Package Description
MM74HC151M
MM74HC151SJ
MM74HC151MTC
MM74HC151N
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Inputs
Outputs
Select
Strobe
C
X
L
B
X
L
A
X
L
S
H
L
L
L
L
L
L
L
L
Y
W
L
H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
H = HIGH Level, L = LOW Level, X = Don't Care
D0, D1...D7 = the level of the respective D input
Top View
© 1999 Fairchild Semiconductor Corporation
DS005313.prf
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Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max
6
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
V
V
)
VCC
)
)
)
±25 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
V
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
260°C
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
= V or V
IH IL
OH
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OUT
V
= V or V
IH IL
IN
|I
|I
| ≤ 4.0 mA
| ≤ 5.2 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
= V or V
IH IL
OL
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
V
= V or V
IH IL
IN
|I
|I
| ≤ 4.0 mA
| ≤ 5.2 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
OUT
OUT
I
I
Maximum Input
Current
V
= V or GND
±1.0
µA
IN
IN
CC
Maximum Quiescent
Supply Current
V
= V or GND
6.0V
8.0
80
160
µA
CC
IN
CC
I
= 0 µA
OUT
Note 4: For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-
IH
IL
CC
IH
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
3
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AC Electrical Characteristics
V
CC = 5V, TA = 25°C, CL = 15 pF, t = t = 6 ns
r f
Guaranteed
Limit
Symbol
, t
Parameter
Conditions
Typ
Units
t
t
t
t
t
t
Maximum Propagation Delay
A, B or C to Y
26
35
ns
PHL PLH
, t
Maximum Propagation Delay
A, B or C to W
27
22
24
17
16
35
29
32
23
21
ns
ns
ns
ns
ns
PHL PLH
, t
Maximum Propagation Delay
Any D to Y
PHL PLH
, t
Maximum Propagation Delay
any D to W
PHL PLH
, t
Maximum Propagation Delay
Strobe to Y
PHL PLH
, t
Maximum Propagation Delay
Strobe to W
PHL PLH
AC Electrical Characteristics
C
L = 50 pF, t = t = 6 ns (unless otherwise specified)
r f
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
90
31
26
95
32
27
70
27
23
75
29
25
50
21
18
45
20
17
30
8
Guaranteed Limits
t
t
t
t
t
t
t
, t
Maximum Propagation Delay
A, B or C to Y
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
205
256
51
300
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
PHL PLH
41
35
44
51
, t
Maximum Propagation Delay
A, B or C to W
205
41
256
51
300
60
PHL PLH
35
44
51
, t
Maximum Propagation Delay
any D to Y
195
39
244
49
283
57
PHL PLH
33
41
48
, t
Maximum Propagation Delay
any D to W
185
37
231
46
268
54
PHL PLH
32
40
46
, t
Maximum Propagation Delay
Strobe to Y
140
28
175
35
203
41
PHL PLH
24
30
35
, t
Maximum Propagation Delay
Strobe to W
127
25
159
32
185
37
PHL PLH
22
28
32
, t
Maximum Output Rise
and Fall Time
75
95
110
22
TLH THL
15
19
7
13
16
19
C
C
Power Dissipation
Capacitance (Note 5)
Maximum Input
Capacitance
(per package)
110
PD
5
10
10
10
pF
IN
2
Note 5: C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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