MM74HC244 [FAIRCHILD]
Octal 3-STATE Buffer; 八路三态缓冲器
| 型号： | MM74HC244 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal 3-STATE Buffer |
| 文件： | 总8页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised August 2000
MM74HC244
Octal 3-STATE Buffer
General Description
Features
The MM74HC244 is a non-inverting buffer and has two
■ Typical propagation delay: 14 ns
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
■ Low quiescent supply current: 80 µA
■ Output current: 6 mA
active low enables (1G and 2G); each enable indepen-
dently controls
4 buffers. This device does not have
Schmitt trigger inputs.
These 3-STATE buffers utilize advanced silicon-gate
CMOS technology and are general purpose high speed
non-inverting buffers. They possess high drive current out-
puts which enable high speed operation even when driving
large bus capacitances. These circuits achieve speeds
comparable to low power Schottky devices, while retaining
the advantage of CMOS circuitry, i.e., high noise immunity,
and low power consumption. All three devices have a
fanout of 15 LS-TTL equivalent inputs.
All inputs are protected from damage due to static dis-
charge by diodes to VCC and ground.
Ordering Code:
Order Number Package Number
Package Description
MM74HC244WM
MM74HC244SJ
MM74HC244MTC
MM74HC244N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
1G
L
1A
1Y
L
2G
L
2A
L
2Y
L
L
H
L
L
H
Z
L
H
L
H
Z
H
H
H
H
H
Z
H
Z
H = HIGH Level
L = LOW Level
Z = High Impedance
Top View
© 2000 Fairchild Semiconductor Corporation
DS005327
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Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
± 20 mA
Min
Max
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
V
)
± 35 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
)
± 70 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
V
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
3.15
4.2
VIL
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level
Output Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.4
3.84
5.34
3.7
5.2
VOL
Maximum LOW Level
Output Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
± 0.1
0.33
0.33
± 1.0
0.4
0.4
V
V
IIN
Maximum Input
Current
VIN = VCC or GND
±1.0
µA
IOZ
Maximum 3-STATE
Output Leakage
Current
V
IN = VIH, or VIL
6.0V
6.0V
± 0.5
± 5
±10
µA
µA
VOUT = VCC or GND
G = VIH
IN = VCC or GND
OUT = 0 µA
ICC
Maximum Quiescent
Supply Current
V
8.0
80
160
I
Note 4: For a power supply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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AC Electrical Characteristics
V
CC = 5V, TA = 25°C, tr = tf = 6 ns
Guaranteed
Limit
Symbol Parameter
Conditions
Typ
Units
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
Maximum Propagation
Delay
C
L = 45 pF
14
20
ns
Maximum Enable Delay
to Active Output
RL = 1 kΩ
CL = 45 pF
RL = 1 kΩ
CL = 5 pF
17
15
28
25
ns
ns
Maximum Disable Delay
from Active Output
AC Electrical Characteristics
V
CC = 2.0V-6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
T
A = 25°C
T
A = −40 to 85°C
TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
L = 50 pF
Units
Typ
58
83
14
17
10
14
Guaranteed Limits
tPHL, tPLH Maximum Propagation
Delay
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
115
145
208
29
171
246
34
ns
ns
ns
ns
ns
ns
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 1 kΩ
165
23
33
42
49
20
25
29
28
35
42
tPZH, tPZL Maximum Output Enable
Time
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 1 kΩ
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
75
100
15
30
13
17
75
15
13
150
200
30
189
252
38
224
298
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
50
60
26
32
38
34
43
51
t
PHZ, tPLZ Maximum Output Disable
Time
150
30
189
38
224
45
L = 50 pF
26
32
38
tTLH, tTHL Maximum Output
Rise and Fall Time
60
75
90
12
15
18
6.0V
10
13
15
CPD
Power Dissipation
(per buffer)
G = VIH
Capacitance (Note 5)
12
50
5
pF
pF
pF
G = VIL
CIN
Maximum Input
Capacitance
10
20
10
20
10
20
COUT
Maximum Output
Capacitance
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCCf + ICC
I
.
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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