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MM74HC245AMTCX_NL [FAIRCHILD]

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MM74HC245AMTCX_NL
型号： MM74HC245AMTCX_NL
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
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September 1983  
Revised May 2005  
MM74HC245A  
Octal 3-STATE Transceiver  
General Description  
Features  
The MM74HC245A 3-STATE bidirectional buffer utilizes  
advanced silicon-gate CMOS technology, and is intended  
for two-way asynchronous communication between data  
buses. It has high drive current outputs which enable high  
speed operation even when driving large bus capaci-  
tances. This circuit possesses the low power consumption  
and high noise immunity usually associated with CMOS cir-  
cuitry, yet has speeds comparable to low power Schottky  
TTL circuits.  
■ Typical propagation delay: 13 ns  
■ Wide power supply range: 2–6V  
■ Low quiescent current: 80 A maximum (74 HC)  
■ 3-STATE outputs for connection to bus oriented systems  
■ High output drive: 6 mA (minimum)  
■ Same as the 645  
This device has an active LOW enable input G and a direc-  
tion control input, DIR. When DIR is HIGH, data flows from  
the A inputs to the B outputs. When DIR is LOW, data flows  
from the B inputs to the A outputs. The MM74HC245A  
transfers true data from one bus to the other.  
This device can drive up to 15 LS-TTL Loads, and does not  
have Schmitt trigger inputs. All inputs are protected from  
damage due to static discharge by diodes to VCC and  
ground.  
Ordering Code:  
Order Number  
MM74HC245AWM  
MM74HC245ASJ  
MM74HC245AMTC  
MM74HC245AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
M20D  
MTC20  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Truth Table  
Pin Assignments for DIP, SOIC, SOP and TSSOP  
Control  
Inputs  
Operation  
G
L
DIR  
L
H
X
B data to A bus  
A data to B bus  
Isolation  
L
H
H
L
X
HIGH Level  
LOW Level  
Irrelevant  
Top View  
© 2005 Fairchild Semiconductor Corporation  
DS005165  
www.fairchildsemi.com  
Logic Diagram  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 1)  
(Note 2)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
DC Input Voltage DIR and G pins (VIN  
DC Input/Output Voltage (VIN, VOUT  
Clamp Diode Current (ICD  
DC Output Current, per pin (IOUT  
DC VCC or GND Current, per pin (ICC  
)
0.5 to 7.0V  
1.5 to VCC 1.5V  
0.5 to VCC 0.5V  
20 mA  
Min  
Max  
Units  
)
Supply Voltage (VCC  
DC Input or Output Voltage  
(VIN, VOUT  
)
2
6
V
)
)
)
0
VCC  
85  
V
C
)
35 mA  
Operating Temperature Range (TA)  
Input Rise/Fall Times  
(tr, tf) VCC 2.0V  
VCC 4.5V  
40  
)
70 mA  
Storage Temperature Range (TSTG  
Power Dissipation (PD)  
(Note 3)  
)
65 C to 150 C  
1000  
500  
ns  
ns  
ns  
600 mW  
500 mW  
VCC 6.0V  
400  
S.O. Package only  
Note 1: Maximum Ratings are those values beyond which damage to the  
device may occur.  
Lead Temperature (TL)  
(Soldering 10 seconds)  
Note 2: Unless otherwise specified all voltages are referenced to ground.  
260 C  
Note 3: Power Dissipation temperature derating — plastic “N” package:  
12 mW/ C from 65 C to 85 C.  
DC Electrical Characteristics (Note 4)  
T
25 C  
T
40 to 85 C  
T
A
55 to 125 C  
A
A
V
Symbol  
Parameter  
Conditions  
Units  
CC  
Typ  
Guaranteed Limits  
V
Minimum HIGH Level Input  
Voltage  
2.0V  
4.5V  
6.0V  
2.0V  
4.5V  
6.0V  
1.5  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
V
V
V
V
V
V
IH  
3.15  
4.2  
V
V
Maximum LOW Level Input  
Voltage  
0.5  
0.5  
0.5  
IL  
1.35  
1.8  
1.35  
1.8  
1.35  
1.8  
Minimum HIGH Level Output  
Voltage  
V
V
or V  
IL  
OH  
IN  
IH  
IH  
|I  
|
20  
A
2.0V  
4.5V  
6.0V  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
V
V
V
OUT  
V
V
V
or V  
IL  
IN  
|I  
|I  
|
|
6.0 mA  
7.8 mA  
4.5V  
6.0V  
4.2  
5.7  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
V
V
OUT  
OUT  
V
Maximum LOW Level Output  
Voltage  
V
or V  
IL  
OL  
IN  
IH  
|I  
|
20  
A
2.0V  
4.5V  
6.0V  
0
0
0
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
V
V
OUT  
V
V
V
or V  
IL  
IN  
IH  
|I  
|I  
|
|
6.0 mA  
7.8 mA  
4.5V  
6.0V  
6.0V  
0.2  
0.2  
0.26  
0.26  
0.1  
0.33  
0.33  
1.0  
0.4  
0.4  
1.0  
V
V
A
OUT  
OUT  
I
I
I
Input Leakage  
V
to GND  
CC  
IN  
IN  
Current (G and DIR)  
Maximum 3-STATE Output  
Leakage Current  
V
V or GND  
CC  
6.0V  
6.0V  
0.5  
8.0  
5.0  
80  
10  
A
A
OZ  
CC  
OUT  
Enable G  
V
IH  
Maximum Quiescent Supply  
Current  
V
V
or GND  
CC  
160  
IN  
I
0 A  
OUT  
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when  
OH  
OL  
designing with this supply. Worst case V and V occur at V  
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-  
IH  
IH  
IL  
CC  
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.  
IN CC  
OZ  
3
www.fairchildsemi.com  
AC Electrical Characteristics  
V
5V, TA 25 C, tr tf 6ns  
CC  
Symbol  
, t  
Guaranteed  
Parameter  
Conditions  
Typ  
Units  
Limit  
17  
t
t
Maximum Propagation Delay  
Maximum Output Enable  
Time  
C
R
C
R
C
45 pF  
1 k  
12  
24  
ns  
ns  
PHL PLH  
L
L
L
L
L
, t  
35  
PZH PZL  
45 pF  
1 k  
t
, t  
Maximum Output Disable  
Time  
18  
25  
ns  
PHZ PLZ  
5 pF  
AC Electrical Characteristics  
V
2.0V to 6.0V, CL 50 pF, tr tf 6ns (unless otherwise specified)  
CC  
T
25 C  
T
40 to 85 C  
T
A
55 to 125 C  
A
A
V
Symbol  
Parameter  
Conditions  
Units  
CC  
Typ  
31  
41  
13  
17  
11  
Guaranteed Limits  
t
t
,
Maximum Propagation  
Delay  
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
50 pF  
150 pF  
50 pF  
150 pF  
50 pF  
150 pF  
1 k  
2.0V  
2.0V  
4.5V  
4.5V  
6.0V  
6.0V  
90  
113  
116  
23  
135  
128  
27  
ns  
ns  
ns  
ns  
ns  
ns  
PHL  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
96  
18  
22  
15  
19  
PLH  
28  
33  
19  
23  
14  
23  
28  
t
t
,
Maximum Output Enable  
Time  
PZH  
PZL  
50 pF  
150 pF  
50 pF  
150 pF  
50 pF  
150 pF  
1 k  
2.0V  
2.0V  
4.5V  
4.5V  
6.0V  
6.0V  
2.0V  
4.5V  
6.0V  
2.0V  
4.5V  
6.0V  
71  
81  
26  
31  
21  
25  
39  
20  
18  
20  
6
190  
240  
38  
240  
300  
48  
285  
360  
57  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
48  
60  
72  
32  
41  
48  
41  
51  
61  
t
t
,
Maximum Output Disable  
Time  
135  
27  
169  
34  
203  
41  
PHZ  
50 pF  
PLZ  
23  
29  
34  
t
, t  
Output Rise and Fall Time  
C
50 pF  
60  
75  
90  
TLH THL  
L
12  
15  
18  
5
10  
13  
15  
C
Power Dissipation  
G
G
V
V
50  
5
pF  
pF  
pF  
pF  
PD  
IL  
Capacitance (Note 5)  
Maximum Input Capacitance  
Maximum Input/Output  
Capacitance, A or B  
IH  
C
C
5
10  
20  
10  
20  
10  
20  
IN  
15  
IN/OUT  
2
Note 5: C determines the no load dynamic power consumption, P  
C
V
f
I
V
, and the no load dynamic current consumption, I  
C
V
f
I
.
CC  
PD  
D
PD CC  
CC CC  
S
PD CC  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Package Number M20B  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M20D  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC20  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Package Number N20A  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
8

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