MM74HC374MTC [FAIRCHILD]
3-STATE Octal D-Type Flip-Flop; 三态八路D型触发器
| 型号： | MM74HC374MTC |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 3-STATE Octal D-Type Flip-Flop |
| 文件： | 总7页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised February 1999
MM74HC374
3-STATE Octal D-Type Flip-Flop
signals are present at the other inputs and the state of the
storage elements.
General Description
The MM74HC374 high speed Octal D-Type Flip-Flops uti-
lize advanced silicon-gate CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
The 74HC logic family is speed, function, and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
■ Typical propagation delay: 20 ns
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the setup and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
■ Wide operating voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum
■ Compatible with bus-oriented systems
■ Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HC374WM
MM74HC374SJ
MM74HC374MTC
MM74HC374N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Output
Clock
Data
Output
Control
L
L
↑
↑
H
L
H
L
L
L
X
X
X
Q0
Z
H
H = HIGH Level
L = LOW Level
X = Don't Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance State
Q
= The level of the output before steady state input conditions were
0
established
Top View
© 1999 Fairchild Semiconductor Corporation
DS005336.prf
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
V
)
±35 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
)
±70 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
V
CC = 4.5V
CC = 6.0V
600 mW
500 mW
V
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
= V or V
IH IL
OH
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OUT
V
= V or V
IH IL
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
= V or V
IH IL
OL
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
V
= V or V
IH IL
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
OUT
OUT
I
I
Maximum Input
Current
V
= V or GND
±1.0
µA
IN
IN
CC
Maximum 3-STATE
Output Leakage
Current
V
V
= V , OC = V
IH
6.0V
6.0V
±0.5
±5
±10
µA
µA
OZ
CC
IN
IH
= V or GND
OUT
CC
I
Maximum Quiescent
Supply Current
V
= V or GND
8.0
80
160
IN
CC
I
= 0 µA
OUT
Note 4: For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-
IH
IL
CC
IH
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
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2
AC Electrical Characteristics
V
CC = 5V, TA = 25°C, t = t = 6 ns
r f
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
f
t
t
t
Maximum Operating
Frequency
50
35
MHz
MAX
, t
Maximum Propagation
Delay Clock to Q
Maximum Output Enable
Time
C =45 pF
20
32
ns
PHL PLH
L
, t
R = kΩ
L
PZH PZL
C =45 pF
19
17
28
25
ns
ns
L
, t
Maximum Output Disable
Time
R = kΩ
L
PHZ PLZ
C =5 pF
L
t
t
t
Minimum Setup Time
Minimum Hold Time
Minimum Pulse Width
20
5
ns
ns
ns
S
H
W
9
16
3
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AC Electrical Characteristics
V
CC = 2.0−6.0V, C = 50 pF, t = t = 6 ns (unless otherwise specified)
L r f
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
= 50 pF
Units
CC
Typ
Guaranteed Limits
f
t
Maximum Operating
Frequency
C
2.0V
4.5V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
6
5
4
MHz
MHz
MHz
ns
MAX
L
30
35
24
20
28
23
, t
Maximum Propagation
Delay, Clock to Q
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 1 kΩ
68
110
22
180
230
36
225
288
45
270
345
48
PHL PLH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ns
ns
30
46
57
69
ns
20
31
39
46
ns
28
40
50
60
ns
t
, t
Maximum Output
Enable Time
PZH PZL
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 1 kΩ
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
50
80
21
30
19
26
50
21
19
150
200
30
40
26
35
150
30
26
50
9
189
250
37
225
300
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
60
31
39
44
53
t
t
t
t
t
, t
Maximum Output
Disable Time
189
37
225
45
PHZ PLZ
= 50 pF
31
39
Minimum Setup Time
Minimum Hold Time
Minimum Pulse Width
60
75
S
13
15
9
11
13
5
30
5
H
W
5
5
5
5
5
5
30
9
80
16
14
60
12
10
1000
500
400
100
20
120
24
8
18
20
, t
Maximum Output Rise
and Fall Time
C
= 50 pF
25
7
75
90
THL TLH
L
15
18
6
13
15
t , t
Maximum Input Rise and
Fall Time, Clock
1000
500
400
1000
500
400
r
f
PD
IN
C
Power Dissipation
(per flip-flop)
OC = V
Capacitance (Note 5)
30
50
5
pF
pF
pF
CC
OC=GND
C
Maximum Input Capacitance
10
10
10
2
Note 5: C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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