MM74HC4040MX_NL [FAIRCHILD]
Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16;
| 型号： | MM74HC4040MX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Binary Counter, HC/UH Series, Asynchronous, Negative Edge Triggered, 12-Bit, Up Direction, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2007
MM74HC4040
tm
12-Stage Binary Counter
Features
General Description
■ Typical propagation delay: 16ns
The MM74HC4040 is a high speed binary ripple carry
counter. This counter is implemented utilizing advanced
silicon-gate CMOS technology to achieve speed perfor-
mance similar to LS-TTL logic while retaining the low
power and high noise immunity of CMOS.
■ Wide operating voltage range: 2–6V
■ Low input current: 1µA Max.
■ Low quiescent current: 80µA Max. (74HC Series)
■ Output drive capability: 10 LS-TTL loads
The MM74HC4040 is a 12-stage counter. This device is
incremented on the falling edge (negative transition) of
the input clock, and all their outputs are reset to a low
level by applying a logical high on their reset input.
This device is pin equivalent to the CD4040. All inputs
are protected from damage due to static discharge by
protection diodes to V and ground.
CC
Ordering Information
Package
Order Number
Number
Package Description
(1)
MM74HC4040M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
(1)
MM74HC4040SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
(1)
MM74HC4040MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
MM74HC4040N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Note:
1. Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
Connection Diagram
Logic Diagram
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
2
(2)
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
Supply Voltage
–0.5 to +7.0V
–1.5 to V +1.5V
CC
V
DC Input Voltage
IN
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
–0.5 to V +0.5V
OUT
CC
I
20mA
25mA
CD
I
OUT
I
DC V or GND Current, per pin
50mA
CC
CC
T
Storage Temperature Range
Power Dissipation
–65°C to +150°C
STG
P
D
Note 3
600mW
500mW
260°C
S.O. Package only
T
Lead Temperature (Soldering 10 seconds)
L
Note:
2. Unless otherwise specified all voltages are referenced to ground.
3. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
2
Max.
Units
V
Supply Voltage
6
V
V
CC
V , V
DC Input or Output Voltage
Operating Temperature Range
Input Rise and Fall Times
0
V
CC
IN OUT
T
–40
+85
°C
A
t , t
r
f
V
V
V
= 2.0V
= 4.5V
= 6.0V
1000
500
ns
CC
CC
CC
400
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
3
(4)
DC Electrical Characteristics
T = –40 T = –55
A
A
T = 25°C
to 85°C
to 125°C
A
Symbol
Parameter
Conditions
V
Typ.
1.5
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
V
IH
3.15
4.2
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
V
V
IL
1.35
1.8
1.35
1.8
1.35
1.8
V
Minimum HIGH Level
Output Voltage
V
= V or V :
IH IL
OH
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OUT
V
= V or V :
IH IL
IN
|I
|I
| ≤ 4.0mA
| ≤ 5.2mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
= V or V :
V
OL
IN
IH
IL
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OUT
V
= V or V :
IH IL
IN
|I
|I
| ≤ 4.0 mA
| ≤ 5.2 mA
4.5V
6.0V
6.0V
6.0V
0.2
0.2
.26
.26
0.1
8.0
0.33
0.33
1.0
0.4
0.4
1.0
160
OUT
OUT
I
Maximum Input Current
V
= V or GND
µA
µA
IN
IN
CC
I
Maximum Quiescent
Supply Current
V
= V or GND,
80
CC
IN
CC
I
= 0µA
OUT
Note:
4. For a power supply of 5V 10ꢀ the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V
OH
OL
values should be used when designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V
IH
IL
CC
respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and I ) occur for CMOS at
IH
IN CC
OZ
the higher voltage and so the 6.0V values should be used.
AC Electrical Characteristics
V
= 5V, T = 25°C, C = 15pF, t = t = 6ns
A L r f
CC
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ.
50
Units
MHz
ns
f
Maximum Operating Frequency
Maximum Propagation Delay Clock to Q
Maximum Propagation Delay Reset to any Q
Minimum Reset Removal Time
Minimum Pulse Width
30
35
40
20
16
MAX
(5)
t
, t
17
PHL PLH
t
16
ns
PHL
t
10
ns
REM
t
10
ns
W
Note:
5. Typical Propagation delay time to any output can be calculated using: t = 17 + 12(N–1) ns; where N is the number
P
of the output, Q , at V = 5V.
W
CC
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
4
AC Electrical Characteristics
V
= 2.0V to 6.0V, C = 50pF, t = t = 6ns (unless otherwise specified).
L r f
CC
T = –40 T = –55
A
A
T = 25°C
to 85°C to 125°C
A
Symbol
Parameter
Conditions
V
Typ
Guaranteed Limits
Units
CC
f
Maximum Operating
Frequency
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
10
40
50
80
21
18
80
18
15
72
24
20
6
30
5
24
4
20
MHz
MAX
35
28
24
t
, t
Maximum Propagation
210
42
265
53
313
63
ns
ns
ns
ns
ns
ns
ns
PHL PLH
Delay Clock to Q
1
36
45
53
t
t
Maximum Propagation
Delay Between Stages from
Q to Q
125
25
156
31
188
38
PHL, PLH
n
n+1
21
26
31
t
Maximum Propagation
Delay Reset to any Q
(4020 and 4040)
240
48
302
60
358
72
PHL
41
51
61
t
Minimum Reset Removal
Time
100
20
126
25
149
50
REM
16
21
25
t
Minimum Pulse Width
90
100
20
120
24
W
16
14
18
20
t
, t
Maximum Output Rise and
Fall Time
30
10
9
75
95
110
22
TLH THL
15
19
13
16
19
t , t
Maximum Input Rise and
Fall Time
1000
500
400
1000
500
400
1000
500
400
r
f
C
Power Dissipation
Capacitance
(per package)
55
5
pF
pF
PD
(6)
C
Maximum Input Capacitance
10
10
10
IN
Note:
6. C determines the no load dynamic power consumption, P = C
2
V
f + I
V
, and the no load dynamic
PD
D
PD CC
CC CC
current consumption, I = C
V
f + I
.
S
PD CC
CC
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
5
Timing Diagram
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
6
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
7
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 2. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
8
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
5.00 0.10
4.55
5.90
4.45 7.35
0.65
4.4 0.1
1.45
5.00
0.11
12°
MTC16rev4
Figure 3. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
10
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when properly used in accordance with instructions for use
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2.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild semiconductor. The datasheet is printed for
reference information only.
Rev. I28
©1984 Fairchild Semiconductor Corporation
MM74HC4040 Rev. 1.4
www.fairchildsemi.com
11
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