MM74HC4538MX_NL [FAIRCHILD]
Monostable Multivibrator, HC/UH Series, 2-Func, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16;
| 型号： | MM74HC4538MX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Monostable Multivibrator, HC/UH Series, 2-Func, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16 时钟 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1984
Revised August 2000
MM74HC4538
Dual Retriggerable Monostable Multivibrator
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
put pulse equation is simply: PW = 0.7(R)(C) where PW is
in seconds, R is in ohms, and C is in farads. This device is
pin compatible with the CD4528, and the CD4538 one
shots. All inputs are protected from damage due to static
discharge by diodes to VCC and ground.
General Description
The MM74HC4538 high speed monostable multivibrator
(one shots) is implemented in advanced silicon-gate
CMOS technology. They feature speeds comparable to low
power Schottky TTL circuitry while retaining the low power
and high noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a posi-
tive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The MM74HC4538 is
retriggerable. That is, it may be triggered repeatedly while
their outputs are generating a pulse and the pulse will be
extended.
Features
■ Schmitt trigger on A and B inputs
■ Wide power supply range: 2–6V
■ Typical trigger propagation delay: 32 ns
■ Fanout of 10 LS-TTL loads
■ Low input current: 1 µA max
Ordering Code:
Order Number
MM74HC4538M
MM74HC4538SJ
MM74HC4538N
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
M16D
N16E
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Inputs
Outputs
Clear
A
X
H
X
L
B
X
X
L
Q
L
L
L
Q
H
H
H
L
X
X
H
H
↓
↑
H
H = HIGH Level
L = LOW Level
↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW
= One HIGH Level Pulse
= One LOW Level Pulse
X = Irrelevant
© 2000 Fairchild Semiconductor Corporation
DS005217
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Block Diagrams
Note: Pin 1 and Pin 15 must be hard-wired to GND.
Logic Diagram
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2
Timing Diagram
TRIGGER OPERATION
Circuit Operation
The MM74HC4538 is triggered by either a rising-edge sig-
nal at input A (#7) or a falling-edge signal at input B (#8),
with the unused trigger input and the Reset input held at
the voltage levels shown in the Truth Table. Either trigger
signal will cause the output of the trigger-control circuit to
go HIGH (#9).
The MM74HC4538 operates as follows (refer to logic dia-
gram). In the quiescent state, the external timing capacitor,
CX, is charged to VCC. When a trigger occurs, the Q output
goes HIGH and CX discharges quickly to the lower refer-
1
ence voltage (VREF Lower =
/ VCC). CX then charges,
3
through RX, back up to the upper reference voltage (VREF
Upper = 2/3 VCC), at which point the one-shot has timed out
The trigger-control circuit going HIGH simultaneously ini-
tiates three events. First, the output latch goes LOW, thus
taking the Q output of the HC4538 to a HIGH State (#10).
Second, transistor M3 is turned on, which allows the exter-
nal timing capacitor, CX, to rapidly discharge toward
and the Q output goes LOW.
The following, more detailed description of the circuit oper-
ation refers to both the logic diagram and the timing dia-
gram.
ground (#11). (Note that the voltage across CXappears at
the input of the upper reference circuit comparator.) Third,
transistor M4 is turned off and transmission gate T1 is
turned ON, thus allowing the voltage across CX to also
QUIESCENT STATE
In the quiescent state, before an input trigger appears, the
output latch is HIGH and the reset latch is HIGH (#1 in logic
diagram).
appear at the input of the lower reference circuit compara-
tor.
When CX discharges to the reference voltage of the lower
Thus the Q output (pin 6 or 10) of the monostable multivi-
brator is LOW (#2, timing diagram).
reference circuit (#12), the outputs of both reference cir-
cuits will be HIGH (#13). The trigger-control reset circuit
goes HIGH, resetting the trigger-control circuit flip-flop to a
LOW State (#14). This turns transistor M3 OFF again,
allowing CX to begin to charge back up toward VCC, with a
The output of the trigger-control circuit is LOW (#3), and
transistors M1, M2, and M3 are turned off. The external
timing capacitor, CX, is charged to VCC (#4), and the upper
reference circuit has a LOW output (#5). Transistor M4 is
turned ON and transmission gate T1 is turned OFF. Thus
the lower reference circuit has VCC at the noninverting
time constant t = RXCX (#15). In addition, transistor M4 is
turned ON and transmission gate T1 is turned OFF. Thus a
high voltage level is applied to the input of the lower refer-
ence circuit comparator, causing its output to go LOW
(#16). The monostable multivibrator may be retriggered at
any time after the trigger-control circuit goes LOW.
input and a resulting LOW output (#6).
In addition, the output of the trigger-control reset circuit is
LOW.
When CX charges up to the reference voltage of the upper
reference circuit (#17), the output of the upper reference
circuit goes LOW (#18). This causes the output latch to
3
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Circuit Operation (Continued)
toggle, taking the Q output of the HC4538 to a LOW State
(#19), and completing the time-out cycle.
device is powered down, the capacitor may discharge from
VCC through the input protection diodes at pin 2 or pin 14.
Current through the protection diodes must be limited to 30
mA; therefore, the turn-off time of the VCC power supply
RESET OPERATION
A low voltage applied to the Reset pin always forces the Q
output of the HC4538 to a LOW State.
must not be faster than t = VCC•CX/(30 mA). For example, if
VCC = 5V and CX = 15 µF, the VCC supply must turn OFF
The timing diagram illustrates the case in which reset
occurs (#20) while CX is charging up toward the reference
no faster than t = (15V)•(15 µF)/30 mA = 2.5 ms. This is
usually not a problem because power supplies are heavily
filtered and cannot discharge at this rate.
voltage of the upper reference circuit (#21). When a reset
occurs, the output of the reset latch goes LOW (#22), turn-
ing ON transistor M1. Thus CX is allowed to quickly charge
When a more rapid decrease of VCC to zero volts occurs,
the MM74HC4538 may sustain damage. To avoid this pos-
sibility, use an external clamping diode, DX, connected
up to VCC (#23) to await the next trigger signal.
Recovery time is the required delay after reset goes inac-
tive to a new trigger rising edge. On the diagram it is shown
as (#26) to (#27).
from VCC to the CX pin.
SET UP RECOMMENDATIONS
Minimum
Minimum
R
C
X = 1 kΩ
X = 0 pF.
RETRIGGER OPERATION
In the retriggerable mode, the HC4538 may be retriggered
during timing out of the output pulse at any time after the
trigger-control circuit flip-flop has been reset (#24).
Because the trigger-control circuit flip-flop resets shortly
after CX has discharged to the reference voltage of the
lower reference circuit (#25), the minimum retrigger time, trr
is a function of internal propagation delays and the dis-
charge time of CX:
at room temperature
POWER-DOWN CONSIDERATIONS
Large values of CX may cause problems when powering
down the MM74HC4538 because of the amount of energy
stored in the capacitor. When a system containing this
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4
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max
6
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
V
V
)
VCC
)
)
)
±25 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
(Reset only)
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
600 mW
500 mW
V
V
CC = 4.5V
CC = 6.0V
S.O. Package only
400
Lead Temperature (TL)
(Soldering 10 seconds)
Note 1: Maximum Ratings are those values beyond which damage to the
device may occur.
260°C
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation Temperature Derating: Plastic “N” Package: −
12mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
T
A = −40 to 85°C
T
A = −55 to 125°C
VCC
Symbol
VIH
Parameter
Conditions
Units
Typ
Guaranteed Limits
Minimum HIGH Level Input
Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
3.15
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
4.2
0.5
VIL
Maximum LOW Level Input
Voltage
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
VOH
Minimum HIGH Level Output
Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
2.0V
4.5V
6.0V
3.98
5.48
0.1
3.84
5.34
0.1
3.7
5.2
0.1
0.1
0.1
V
V
V
V
V
VOL
Maximum LOW Level Output
Voltage
VIN = VIH or VIL
0
0
0
|IOUT| ≤ 20 µA
0.1
0.1
0.1
0.1
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
6.0V
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
IIN
Maximum Input Current
(Pins 2, 14) (Note 5)
Maximum Input Current
(all other pins)
VIN = VCC or GND
±1.0
µA
IIN
V
IN = VCC or GND
6.0V
6.0V
6.0V
±0.1
150
130
±1.0
250
220
±1.0
400
350
µA
µA
µA
ICC
Maximum Active Supply
Current
Pins 2, 14 = 0.5 VCC
Q1, Q2 = HIGH
Active
V
IN = VCC or GND
Maximum Quiescent Supply Pins 2, 14 = OPEN
Q1, Q2 = LOW
IN = VCC or GND
ICC
Quiescent Current
V
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
5
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DC Electrical Characteristics (Continued)
Note 5: The device must be set up with 3 steps before measuring IIN
:
Clear
A
L
B
H
H
H
1.
2.
3.
H
H
H
H
L
AC Electrical Characteristics
V
CC = 5V, TA = 25° C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
Conditions
Typ
Limit
Units
tPLH
Maximum Propagation Delay A, or B to Q
23
45
ns
tPHL
tPHL
Maximum Propagation Delay A, or B to Q
Maximum Propagation Delay Clear to Q
26
23
50
45
ns
ns
tPLH
tW
Maximum Propagation Delay Clear to Q
Minimum Pulse Width A, B or Clear
26
10
50
16
ns
ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
T
A=25°C
T
A=−40 to 85°C
T
A = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
100
25
Guaranteed Limits
tPLH
tPHL
tPHL
tPLH
tTLH, tTHL
tr, tf
Maximum Propagation
Delay A, or B to Q
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
3.0V
5.0V
3.0V
5.0V
3.0V
5.0V
3.0V
5.0V
250
50
315
63
373
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
21
43
54
63
Maximum Propagation
Delay A, or B to Q
110
28
275
55
347
69
410
82
23
47
59
70
Maximum Propagation
Delay Clear to Q
100
25
250
50
315
63
373
75
21
43
54
63
Maximum Propagation
Delay Clear to Q
110
28
275
55
347
69
410
82
23
47
59
70
Maximum Output
Rise and Fall
Time
30
75
95
110
22
10
15
19
8
13
16
19
Maximum Input
Rise and Fall
Time (Reset only)
Minimum Pulse Width
A, B, Clear
1000
500
400
80
1000
500
400
101
20
1000
500
400
119
24
tW
16
14
17
20
tREC
Minimum Recovery
Time, Clear
−5
0
0
0
0
0
0
Inactive to A or B
Output Pulse Width
0
0
0
tWQ
C
X = 12 pF
X = 1 kΩ
Min
Max
Min
Max
283
147
283
147
1.2
1.0
1.2
190
120
400
185
R
tWQ
Output Pulse Width
C
X = 100 pF
X = 10 kΩ
R
1.0
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6
AC Electrical Characteristics (Continued)
T
A=25°C
T
A=−40 to 85°C
T
A = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
10.5
10.0
10.5
10.0
Guaranteed Limits
tWQ
Output Pulse Width
C
X = 1000 pF
Min
3.0V
5.0V
3.0V
5.0V
5.0V
5.0V
9.4
9.3
µs
µs
µs
µs
ms
ms
pF
R
X = 10 kΩ
Max
11.6
10.7
tWQ
CIN
CIN
Output Pulse Width
C
X = 0.1µF
X = 10k
Min
0.63
0.77
0.602
0.798
0.595
0.805
R
Max
Maximum Input
25
5
Capacitance (Pins 2 & 14)
Maximum Input
10
10
10
pF
pF
Capacitance (other inputs)
Power Dissipation
Capacitance (Note 6)
Pulse Width Match
Between Circuits in
Same Package
CPD
(per one shot)
150
∆tWQ
±1
%
Note 6: CPD determines the no load dynamic consumption, PD = CPD VCC2f+ICC VCC, and the no load dynamic current consumption, IS = VCC f + ICC
.
7
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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