MM74HC541N [FAIRCHILD]
Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer; 反相八路三态缓冲器八路三态缓冲器
| 型号： | MM74HC541N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer |
| 文件： | 总6页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised February 1999
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
General Description
The MM74HC540 and MM74HC541 3-STATE buffers uti-
opposite sides of the package. All inputs are protected from
lize advanced silicon-gate CMOS technology. They pos-
damage due to static discharge by diodes to VCC and
sess high drive current outputs which enable high speed
ground.
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
Features
circuitry, i.e., high noise immunity, and low power consump-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
■ Typical propagation delay: 12 ns
■ 3-STATE outputs for connection to system buses
■ Wide power supply range: 2–6V
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Output current: 6 mA
Ordering Code:
Order Number Package Number
Package Description
MM74HC540WM
MM74HC540SJ
MM74HC540MTC
MM74HC540N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541WM
MM74HC541SJ
MM74HC541MTC
MM74HC541N
M20B
M20D
MTC20
N20A
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
Top View
MM74HC541
© 1999 Fairchild Semiconductor Corporation
DS005341.prf
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (ICD
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
V
DC Output Current, per pin (IOUT
)
±35 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
DC VCC or GND Current,
per pin (ICC
)
±70 mA
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
V
V
CC = 4.5V
CC = 6.0V
400
600 mW
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
S.O. Package only
Note 2: Unless otherwise specified all voltages are referenced to ground.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics (Note 4)
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level
Output Voltage
V
= V or V
IH IL
OH
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OUT
V
= V or V
IH IL
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
V
Maximum LOW Level
Output Voltage
V
= V or V
IH IL
OL
IN
|I
| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
V
= V or V
IH IL
IN
|I
|I
| ≤ 6.0 mA
| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
V
OUT
OUT
I
I
Maximum Input
Current
V
= V or GND
±1.0
µA
IN
IN
CC
Maximum 3-STATE
6.0V
6.0V
±0.5
±5
±10
µA
µA
V
V
= V or V , G = V
IH
OZ
CC
IN
IH
IL
Output Leakage
Current
= V or GND
CC
OUT
I
Maximum Quiescent
Supply Current
V
= V or GND
8.0
80
160
IN
CC
I
= 0 µA
OUT
Note 4: For a power supply of 5V ±10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst case V and V occur at V = 5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage cur-
IH
IL
CC
IH
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
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2
AC Electrical Characteristics
V
CC = 5V, TA = 25°C, t = t = 6 ns
r f
Guaranteed
Limit
Symbol
, t
Parameter
Conditions
Typ
Units
t
t
t
t
Maximum Propagation
Delay (540)
C
C
= 45 pF
= 45 pF
12
18
ns
PHL PLH
L
L
, t
Maximum Propagation
Delay (541)
14
17
15
20
28
25
ns
ns
ns
PHL PLH
, t
Maximum Output Enable
Time
R
C
R
C
= 1 kΩ
= 45 pF
= 1 kΩ
= 5 pF
PZH PZL
L
L
L
L
, t
Maximum Output Disable
Time
PHZ PLZ
AC Electrical Characteristics
V
CC = 2.0V to 6.0V, CL = 50 pF, t = t = 6 ns (unless otherwise specified)
r f
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
V
Symbol
Parameter
Conditions
= 50 pF
Units
CC
Typ
55
83
12
22
11
18
58
83
14
17
11
14
Guaranteed Limits
t
, t
Maximum Propagation
Delay (540)
C
C
C
C
C
C
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
100
126
190
25
149
224
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 1 kΩ
150
20
30
38
45
17
21
25
26
32
38
t
, t
Maximum Propagation
Delay (541)
115
165
23
145
208
29
171
246
34
PHL PLH
33
42
49
20
25
29
28
35
42
t
, t
Maximum Output Enable
Time
PZH PZL
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 50 pF
= 150 pF
= 1 kΩ
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
75
100
15
30
13
17
75
15
13
25
7
150
200
30
189
252
38
224
298
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
40
50
60
26
32
38
34
43
51
t
, t
Maximum Output Disable
Time
150
30
189
38
224
45
PHZ PLZ
= 50 pF
26
32
38
t
, t
Maximum Output Rise
and Fall Time
C
= 50 pF
60
75
90
THL TLH
L
12
15
18
6
10
13
15
C
Power Dissipation
10
G = V
G = V
PD
IH
Capacitance (Note 5)
Maximum Input
Capacitance
50
5
pF
pF
IL
C
10
20
10
20
10
20
IN
C
Maximum Output Capacitance
15
pF
OUT
2
Note 5: C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
CC
S
PD CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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