MM74HC573SJX_NL [FAIRCHILD]
Bus Driver, HC/UH Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20;
| 型号： | MM74HC573SJX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, HC/UH Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20 锁存器 |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised May 2005
MM74HC573
3-STATE Octal D-Type Latch
General Description
Features
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
■ Typical propagation delay: 18 ns
■ Wide operating voltage range: 2 to 6 volts
■ Low input current: 1 A maximum
■ Low quiescent current: 80 A maximum (74HC Series)
■ Compatible with bus-oriented systems
■ Output drive capability: 15 LS-TTL loads
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the out-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Ordering Code:
Order Number Package Number
Package Description
MM74HC573WM
MM74HC573SJ
MM74HC573MTC
MM74HC573N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Output
Latch
Data
Output
Control
Enable
L
L
H
H
L
H
L
H
L
L
X
X
Q0
Z
H
X
H
L
HIGH Level
LOW Level
Q
Level of output before steady-state input conditions were established.
0
Z
X
High Impedance
Don't Care
Top View
© 2005 Fairchild Semiconductor Corporation
DS005212
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
0.5 to 7.0V
1.5 to VCC 1.5V
0.5 to VCC 0.5V
20 mA
Min Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
0
6
V
V
)
VCC
)
)
)
35 mA
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf) VCC 2.0V
VCC 4.5V
40
85
C
)
70 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
65 C to 150 C
1000
500
ns
ns
ns
600 mW
500 mW
VCC 6.0V
400
S.O. Package only
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 2: Unless otherwise specified all voltages are referenced to ground.
260 C
Note 3: Power Dissipation temperature derating — plastic “N” package:
12 mW/ C from 65 C to 85 C.
DC Electrical Characteristics (Note 4)
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
V
Minimum HIGH Level Input
Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
V
V
IH
3.15
4.2
V
V
Maximum LOW Level Input
Voltage
0.5
0.5
0.5
IL
1.35
1.8
1.35
1.8
1.35
1.8
Minimum HIGH Level Output
Voltage
V
V
or V
IL
OH
IN
IH
|I
|
20
A
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
OUT
V
V
V
or V
IL
IN
IH
|I
|I
|
|
6.0 mA
7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
OUT
OUT
V
Maximum LOW Level Output
Voltage
V
or V
IL
OL
IN
IH
|I
|
20
A
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OUT
V
V
or V
IL
IN
IH
|I
|I
|
|
6.0 mA
7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
0.1
0.33
0.33
1.0
0.4
0.4
1.0
V
V
A
OUT
OUT
I
Maximum Input Current
Maximum 3-STATE Output
Leakage Current
V
V
V
or GND
CC
IN
IN
OUT
I
V
or GND
OZ
CC
OC
V
6.0V
0.5
5.0
10
A
IH
I
Maximum Quiescent Supply
Current
V
V
or GND
CC
IN
CC
I
0
A
6.0V
OE
8.0
1.5
0.8
0.5
80
1.8
1.0
0.6
160
2.0
1.1
0.7
A
mA
mA
mA
OUT
I
Quiescent Supply Current
per Input Pin
V
V
5.5V
2.4V
1.0
0.6
0.4
CC
CC
IN
LE
or 0.4V (Note 4)
DATA
Note 4: For a power supply of 5V 10% the worst-case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when
OH
OL
designing with this supply. Worst-case V and V occur at V
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst-case leakage cur-
IH
IH
IL
CC
rent (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
IN CC
OZ
www.fairchildsemi.com
2
AC Electrical Characteristics
V
5V, TA 25 C, tr tf 6 ns
Symbol Parameter
, t
CC
Guaranteed
Conditions
Typ
Units
Limit
20
t
Maximum Propagation Delay, Data to Q
Maximum Propagation Delay, LE to Q
Maximum Output Enable Time
C
C
R
C
R
C
45 pF
45 pF
1 k
16
14
15
ns
ns
ns
PHL PLH
L
L
L
L
L
L
t
, t
22
PHL PLH
t
, t
27
PZH PZL
45 pF
1 k
t
, t
Maximum Output Disable Time
13
23
ns
PHZ PLZ
5 pF
t
Minimum Set Up Time, Data to LE
Minimum Hold Time, LE to Data
Minimum Pulse Width, LE or Data
10
2
15
5
ns
ns
ns
S
t
H
t
10
16
W
AC Electrical Characteristics
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Symbol
, t
Parameter
Conditions
Units
CC
Typ
45
58
17
21
15
19
46
60
14
21
12
19
Guaranteed Limits
t
Maximum Propagation
Delay Data to Q
C
C
C
C
C
C
C
C
C
C
C
C
R
C
C
C
C
C
C
R
C
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
110
138
188
28
165
225
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
150
22
30
38
40
19
24
29
26
33
39
t
, t
Maximum Propagation
Delay, LE to Q
115
155
23
138
194
29
165
233
35
PHL PLH
31
47
47
20
25
30
27
34
41
t
, t
Maximum Output Enable
Time
PZH PZL
50 pF
150 pF
50 pF
150 pF
50 pF
150 pF
1 k
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
55
67
15
24
14
22
40
13
12
30
10
9
140
180
28
36
24
31
125
25
21
75
15
13
25
5
175
225
35
45
30
39
156
31
27
95
19
16
31
6
210
270
42
54
36
47
188
38
32
110
22
19
38
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
t
, t
Maximum Output Disable
Time
PHZ PLZ
50 pF
t
Minimum Set Up Time
Data to LE
S
t
Minimum Hold Time
LE to Data
H
4
5
6
t
Minimum Pulse Width LE,
or Data
30
9
80
16
14
60
12
10
100
20
18
75
15
13
120
24
20
90
18
15
W
8
t
, t
Maximum Output Rise
and Fall Time, Clock
C
50 pF
25
7
TLH THL
L
6
C
Power Dissipation Capacitance OC
V
5
PD
CC
(Note 5) (per latch)
Maximum Input
Capacitance
OC GND
52
5
C
10
10
10
IN
3
www.fairchildsemi.com
AC Electrical Characteristics (Continued)
T
25 C
T
40 to 85 C
T
A
55 to 125 C
A
A
V
Symbol
Parameter
Conditions
Units
CC
Typ
Guaranteed Limits
C
Maximum Output
Capacitance
Note 5: C determines the no load dynamic power consumption, P
15
20
20
20
pF
OUT
2
C
V
f
I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
C
V
f
I
.
CC
S
PD CC
www.fairchildsemi.com
4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
www.fairchildsemi.com
8
相关型号：
MM74HC573WM_NL
Bus Driver, HC/UH Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明