MM74HC595_04 [FAIRCHILD]
8-Bit Shift Registers with Output Latches; 8位移位寄存器与输出锁存器
| 型号： | MM74HC595_04 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 8-Bit Shift Registers with Output Latches |
| 文件： | 总10页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1983
Revised July 2004
MM74HC595
8-Bit Shift Registers with Output Latches
General Description
Features
The MM74HC595 high speed shift register utilizes
advanced silicon-gate CMOS technology. This device pos-
sesses the high noise immunity and low power consump-
tion of standard CMOS integrated circuits, as well as the
ability to drive 15 LS-TTL loads.
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ 8-bit serial-in, parallel-out shift register with storage
■ Wide operating voltage range: 2V–6V
■ Cascadable
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has 8 3-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a direct-overriding clear, serial input,
and serial output (standard) pins for cascading. Both the
shift register and storage register use positive-edge trig-
gered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
■ Shift register has direct clear
■ Guaranteed shift frequency: DC to 30 MHz
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Ordering Code:
Order Number Package Number
Package Description
MM74HC595M
MM74HC595SJ
MM74HC595MTC
MM74HC595N
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
RCK SCK SCLR
G
H
L
Function
QA thru QH = 3-STATE
Shift Register cleared
Q’H = 0
X
X
X
X
X
L
X
↑
H
H
L
L
Shift Register clocked
QN = Qn-1, Q0 = SER
↑
X
Contents of Shift
Register transferred
to output latches
Top View
© 2004 Fairchild Semiconductor Corporation
DS005342
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Logic Diagram
(positive logic)
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2
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max
Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
2
6
V
)
)
)
0
VCC
V
DC Output Current, per pin (IOUT
DC VCC or GND Current,
)
±35 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
per pin (ICC
)
±70 mA
(tr, tf) VCC = 2.0V
1000
500
ns
ns
ns
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
V
V
CC = 4.5V
CC = 6.0V
400
600 mW
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
S.O. Package only
Note 2: Unless otherwise specified all voltages are referenced to ground.
Lead Temperature (TL)
(Soldering 10 seconds)
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
260°C
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
3.15
4.2
V
VIL
Maximum LOW Level
Input Voltage
0.5
0.5
0.5
1.35
1.8
1.35
1.8
1.35
1.8
V
V
VOH
Minimum HIGH Level
Output Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
Q’H
VIN = VIH or VIL
|IOUT| ≤ 4.0 mA
|IOUT| ≤ 5.2 mA
4.5V
6.0V
4.2
5.2
3.98
5.48
3.84
5.34
3.7
5.2
V
V
QA thru QH
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
VOL
Maximum LOW Level
Output Voltage
V
IN = VIH or VIL
|IOUT| ≤ 20 µA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
Q’H
VIN = VIH or VIL
|IOUT| ≤ 4 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
|IOUT| ≤ 5.2 mA
QA thru QH
VIN = VIH or VIL
|IOUT| ≤ 6.0 mA
|IOUT| ≤ 7.8 mA
4.5V
6.0V
6.0V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
0.4
0.4
V
IIN
Maximum Input
Current
V
IN = VCC or GND
±1.0
µA
IOZ
Maximum 3-STATE
Output Leakage
Maximum Quiescent
Supply Current
V
OUT = VCC or GND
6.0V
6.0V
±0.5
±5.0
±10
µA
µA
G = VIH
IN = VCC or GND
OUT = 0 µA
ICC
V
8.0
80
160
I
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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AC Electrical Characteristics
V
CC = 5V, TA = 25°C, tr = tf = 6 ns
Guaranteed
Limit
Symbol Parameter
Conditions
Typ
Units
fMAX
Maximum Operating
Frequency of SCK
50
30
MHz
tPHL, tPLH
tPHL, tPLH
tPZH, tPZL
tPHZ, tPLZ
tS
Maximum Propagation
Delay, SCK to Q’H
C
L = 45 pF
L = 45 pF
12
18
20
30
ns
ns
Maximum Propagation
Delay, RCK to QA thru QH
Maximum Output Enable
Time from G to QA thru QH
Maximum Output Disable
Time from G to QA thru QH
Minimum Setup Time
from SER to SCK
C
R
C
R
C
L = 1 kΩ
L = 45 pF
L = kΩ
17
15
28
25
ns
ns
L = 5 pF
20
20
40
ns
ns
ns
tS
Minimum Setup Time
from SCLR to SCK
Minimum Setup Time
from SCK to RCK
tS
(Note 5)
tH
Minimum Hold Time
from SER to SCK
0
ns
ns
tW
Minimum Pulse Width
of SCK or RCK
16
Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the stor-
age register state will be one clock pulse behind the shift register.
AC Electrical Characteristics
V
CC = 2.0−6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
fMAX
Parameter
Conditions
L = 50 pF
Units
Typ
10
45
50
58
83
14
17
10
14
70
105
21
28
18
26
Guaranteed Limits
Maximum Operating
Frequency
C
2.0V
4.5V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
2.0V
4.5V
6.0V
6
4.8
24
4.0
20
30
35
MHz
28
24
tPHL, tPLH Maximum Propagation
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
CL = 50 pF
CL = 150 pF
210
294
42
265
367
53
315
441
63
ns
ns
ns
ns
ns
ns
Delay from SCK to Q’H
58
74
88
36
45
54
50
63
76
tPHL, tPLH Maximum Propagation
Delay from RCK to QA thru QH
175
245
35
220
306
44
265
368
53
49
61
74
30
37
45
42
53
63
tPHL, tPLH Maximum Propagation
175
35
221
44
261
52
Delay from SCLR to Q’H
ns
30
37
44
tPZH, tPZL Maximum Output Enable
from G to QA thru QH
R
C
C
C
C
C
C
L = 1 kΩ
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
L = 50 pF
L = 150 pF
2.0V
2.0V
4.5V
4.5V
6.0V
6.0V
75
100
15
175
245
35
220
306
44
265
368
53
ns
ns
ns
20
49
61
74
13
30
37
45
17
42
53
63
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4
AC Electrical Characteristics (Continued)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VCC
Symbol
Parameter
Conditions
Units
Typ
75
Guaranteed Limits
tPHZ, tPLZ Maximum Output Disable
Time from G to QA thru QH
R
L = 1 kΩ
L = 50 pF
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
175
220
44
37
125
25
21
63
13
11
265
53
C
15
35
30
100
20
17
50
10
9
ns
13
45
tS
Minimum Setup Time
from SER to SCK
150
30
ns
ns
ns
ns
ns
ns
ns
25
tR
Minimum Removal Time
from SCLR to SCK
75
15
13
tS
Minimum Setup Time
from SCK to RCK
100
20
17
5
125
25
21
5
150
30
26
tH
Minimum Hold Time
SER to SCK
5
5
5
5
5
5
5
tW
Minimum Pulse Width
of SCK or SCLR
30
9
80
16
14
1000
500
400
60
12
10
75
15
13
100
20
18
1000
500
400
75
15
13
95
19
16
120
24
8
22
tr, tf
Maximum Input Rise and
Fall Time, Clock
1000
500
400
90
t
THL, tTLH Maximum Output
25
7
Rise and Fall Time
18
QA–QH
6
15
tTHL, tTLH Maximum Output
Rise & Fall Time
Q'H
110
22
ns
19
CPD
Power Dissipation
Capacitance, Outputs
Enabled (Note 6)
Maximum Input
Capacitance
G = VCC
90
pF
G = GND
150
CIN
5
10
20
10
20
10
20
pF
pF
COUT
Maximum Output
Capacitance
15
Note 6: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
S = CPD VCC f + ICC
I
.
5
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Timing Diagram
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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