MM74HCT08MX [FAIRCHILD]
AND Gate, HCT Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14;
| 型号： | MM74HCT08MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | AND Gate, HCT Series, 4-Func, 2-Input, CMOS, PDSO14, 0.150 INCH, MS-012, SOIC-14 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1983
Revised February 1999
MM74HCT08
Quad 2-Input AND Gate
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
General Description
The MM74HCT08 is a logic function fabricated by using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS—low quiescent power and
wide power supply range. This device is input and output
characteristic and pinout compatible with standard 74LS
logic families. All inputs are protected from static discharge
damage by internal diodes to VCC and ground.
Features
■ TTL, LS pin-out and threshold compatible
■ Fast switching: tPLH, tPHL = 12 ns (typ)
■ Low power: 10 µW at DC
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
■ High fan-out, 10 LS-TTL loads
Ordering Code:
Order Number Package Number
Package Description
MM74HCT08M
MM74HCT08SJ
MM74HCT08MTC
MM74HCT08N
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Logic Diagram
© 1999 Fairchild Semiconductor Corporation
DS005754.prf
www.fairchildsemi.com
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.0V
−1.5 to VCC +1.5V
−0.5 to VCC +0.5V
±20 mA
Min
Max Units
)
Supply Voltage (VCC
DC Input or Output Voltage
(VIN, VOUT
)
4.5
5.5
V
)
)
)
0
VCC
V
)
±25 mA
Operating Temperature Range (TA)
Input Rise or Fall Times
(tr, tf)
−40
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
500
ns
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
600 mW
500 mW
Note 2: Unless otherwise specified all voltages are referenced to ground.
S.O. Package only
Note 3: Power Dissipation temperature derating — plastic “N” package −12
mW/°C from 65°C to 85°C.
Lead Temperature (TL)
(Soldering 10 seconds)
260°C
DC Electrical Characteristics
V
= 5V ± 10% (unless otherwise specified)
CC
T
= 25°C
T = −40 to 85°C T = −55 to 125°C
A A
A
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
V
IH
V
V
Maximum LOW Level
Input Voltage
0.8
0.8
V
IL
Minimum HIGH Level
Output Voltage
V
= V or V
IH IL
OH
IN
|I
|I
|I
| = 20 µA
V
V
− 0.1
V
− 0.1
V − 0.1
CC
V
V
V
OUT
OUT
OUT
CC
CC
CC
| = 4.0 mA, V = 4.5V
4.2
5.2
3.98
4.98
3.84
3.7
4.7
CC
| = 4.8 mA, V = 5.5V
4.84
CC
V
Maximum LOW Level
Voltage
V
= V
OL
IN
IH
|I
|I
|I
| = 20 µA
0
0.1
0.1
0.1
0.4
V
V
OUT
OUT
OUT
| = 4.0 mA, V = 4.5V
0.2
0.2
0.26
0.26
±0.1
0.33
0.33
±1.0
CC
| = 4.8 mA, V = 5.5V
0.4
V
CC
I
I
Maximum Input
Current
V
= V or GND, V or V
IL
±1.0
µA
IN
IN
CC
IH
Maximum Quiescent
Supply Current
V
= V or GND
2.0
1.2
20
40
µA
CC
IN
CC
I
= 0 µA
OUT
V
= 2.4V or 0.5V (Note 4)
1.4
1.5
mA
IN
Note 4: This is measured per input with all other inputs held at V or ground.
CC
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2
AC Electrical Characteristics
V
CC = 5.0V, t = t = 6 ns, CL = 15 pF, T = 25°C
r
f
A
Guaranteed
Limit
Symbol
, t
Parameter
Conditions
Typ
Units
t
Maximum Propagation Delay
9
15
ns
PLH PHL
AC Electrical Characteristics
V
CC = 5.0V ± 10%, t = t = 6 ns, C = 50 pF
r f L
T
= 25°C
T
= −40 to 85°C T = −55 to 125°C
A
A
A
Symbol
Parameter
Conditions
Units
Typ
11
7
Guaranteed Limits
t
, t
Maximum Propagation Delay
18
23
19
27
22
ns
ns
PLH PHL
t
, t
Maximum Output Rise & Fall
Time
15
THL TLH
C
Power Dissipation Capaci-
tance
(Note 5)
38
5
pF
pF
PD
IN
C
Input Capacitance
10
10
10
Note 5: C determines the no load dynamic power consumption. P = C
V
2 f + I
V
and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
CC
S
PD CC
3
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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