N302AP [FAIRCHILD]
N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs; N沟道逻辑电平PWM优化UltraFET沟道功率MOSFET
| 型号： | N302AP |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs |
| 文件： | 总10页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2002
ISL9N302AP3
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
• Fast switching
• r
• r
= 0.0019Ω (Typ), V = 10V
GS
DS(ON)
DS(ON)
= 0.0027Ω (Typ), V = 4.5V
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
GS
• Q (Typ) = 110nC, V = 5V
g
GS
• Q (Typ) = 31nC
gd
Applications
• DC/DC converters
• C
(Typ) = 11000pF
ISS
SOURCE
DRAIN
GATE
D
S
G
DRAIN
(FLANGE)
TO-220AB
MOSFET Maximum Ratings T = 25°C unless otherwise noted
A
Symbol
Parameter
Ratings
30
Units
V
V
V
V
Drain to Source Voltage
Gate to Source Voltage
DSS
GS
20
Drain Current
o
75
75
A
A
Continuous (T = 25 C, V = 10V)
C
GS
I
D
o
Continuous (T = 100 C, V = 4.5V)
C
GS
Pulsed
Figure 4
A
Power dissipation
Derate above 25 C
345
2.3
W
W/ C
P
o
o
D
o
T , T
Operating and Storage Temperature
-55 to 175
C
J
STG
Thermal Characteristics
o
o
R
Thermal Resistance Junction to Case TO-220
0.43
62
C/W
C/W
θJC
θJA
R
Thermal Resistance Junction to Ambient TO-220
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
N302AP
ISL9N302AP3
TO-220AB
Tube
N/A
50
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
Electrical Characteristics T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
B
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
= 250µA, V = 0V
30
-
-
-
-
-
-
V
VDSS
D
GS
V
V
V
= 25V
= 0V
1
DS
GS
GS
I
µA
nA
DSS
GSS
o
T
= 150
-
250
100
C
I
=
20V
-
On Characteristics
V
Gate to Source Threshold Voltage
V
= V , I = 250µA
1
-
-
3
V
GS(TH)
GS
DS
D
I
I
= 75A, V = 10V
0.0019 0.0025
0.0027 0.0033
D
D
GS
r
Drain to Source On Resistance
Ω
DS(ON)
= 75A, V = 4.5V
-
GS
Dynamic Characteristics
C
C
C
Input Capacitance
-
-
-
11000
2000
900
200
110
12
-
pF
pF
pF
nC
nC
nC
nC
nC
ISS
V
= 15V, V = 0V,
GS
DS
Output Capacitance
-
-
OSS
RSS
f = 1MHz
Reverse Transfer Capacitance
Total Gate Charge at 10V
Total Gate Charge at 5V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q
Q
Q
Q
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
300
165
18
-
g(TOT)
g(5)
g(TH)
gs
GS
GS
GS
-
-
-
-
V
= 15V
DD
= 75A
I
D
I = 1.0mA
g
25
31
-
gd
Switching Characteristics (V = 4.5V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
29
120
45
34
-
224
ns
ns
ns
ns
ns
ns
ON
-
d(ON)
-
V
V
= 15V, I = 28A
r
DD
GS
D
= 4.5V, R = 1.5Ω
Turn-Off Delay Time
Fall Time
-
-
GS
d(OFF)
f
Turn-Off Time
119
OFF
Switching Characteristics (V = 10V)
GS
t
t
t
t
t
t
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
16
120
70
30
-
204
ns
ns
ns
ns
ns
ns
ON
-
d(ON)
-
V
V
= 15V, I = 28A
r
DD
GS
D
= 10V, R = 1.5Ω
Turn-Off Delay Time
Fall Time
-
-
GS
d(OFF)
f
Turn-Off Time
150
OFF
Unclamped Inductive Switching
t
Avalanche Time
I
= 7.2A, L = 3.0mH
D
480
-
-
µs
AV
Drain-Source Diode Characteristics
I
I
I
I
= 75A
= 40A
-
-
-
-
-
-
-
-
1.25
1.0
42
V
V
SD
SD
SD
SD
V
t
Source to Drain Diode Voltage
SD
Reverse Recovery Time
= 75A, dI /dt = 100A/µs
= 75A, dI /dt = 100A/µs
ns
nC
rr
SD
Q
Reverse Recovered Charge
34
RR
SD
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
Typical Characteristic
1.2
1.0
0.8
0.6
0.4
0.2
0
80
60
40
20
0
V
= 10V
GS
V
= 4.5V
GS
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
C
T , CASE TEMPERATURE ( C)
C
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
1
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R
+ T
J
DM
θJC
θJC C
0.01
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
5000
o
T
= 25 C
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
1000
V
= 10V
= 5V
I = I
25
GS
V
GS
100
50
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
Typical Characteristic (Continued)
150
150
125
100
75
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 3.5V
GS
125
V
= 15V
DD
V
= 3V
GS
100
75
50
25
0
o
V
= 4.5V
T
= 25 C
GS
J
50
o
T
= 25 C
o
C
T
= 175 C
J
V
= 10V
GS
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= -55 C
J
0
0
1.5
2.0
2.5
3.0
3.5
0.5
1.0
1.5
2.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
Figure 5. Transfer Characteristics
Figure 6. Saturation Characteristics
10
1.8
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
1.6
8
6
4
2
0
I
= 75A
D
1.4
1.2
1.0
0.8
0.6
I
= 10A
D
V
= 10V, I = 75A
D
GS
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.4
1.2
V
= V , I = 250µA
DS D
GS
I
= 250µA
D
1.2
1.0
0.8
0.6
0.4
0.2
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
Typical Characteristic (Continued)
20000
10000
10
8
V
= 15V
DD
C
= C + C
GS GD
ISS
C
≅ C + C
DS GD
OSS
6
4
C
= C
GD
RSS
WAVEFORMS IN
DESCENDING ORDER:
2
1000
500
I
I
= 75A
= 28A
D
D
V
= 0V, f = 1MHz
GS
0
0
50
100
150
200
250
0.1
1
10
30
V
, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
DS
g
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
1000
1400
V
= 10V, V = 15V, I = 28A
V
= 4.5V, V = 15V, I = 28A
DD D
GS
DD
D
GS
1200
1000
800
600
400
200
0
800
600
400
200
0
t
t
r
f
t
d(OFF)
t
f
t
d(OFF)
t
r
t
d(ON)
t
d(ON)
10
20
30
40
50
0
0
10
GS
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
Figure 13. Switching Time vs Gate Resistance
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
V
BV
DSS
DS
t
P
V
DS
L
I
AS
V
DD
VARY t TO OBTAIN
P
+
-
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
Test Circuits and Waveforms (Continued)
V
DS
V
Q
DD
g(TOT)
R
L
V
DS
V
= 10V
GS
Q
g(5)
V
GS
+
-
V
V
= 5V
DD
V
GS
GS
V
= 1V
DUT
GS
0
I
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
-
V
GS
V
DD
10%
10%
0
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
Figure 19. Switching Time Test Circuit
Figure 20. Switching Time Waveforms
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
PSPICE Electrical Model
SUBCKT ISL9N302AP3 2 1 3 ;
rev Nov 2001
CA 12 8 9e-9
Cb 15 14 5.5e-9
Cin 6 8 1e-8
LDRAIN
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
DBREAK
Ebreak 11 7 17 18 30.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
+
RSLC2
5
51
ESLC
11
-
+
50
-
17
DBODY
RDRAIN
6
8
EBREAK 18
-
ESG
EVTHRES
+
16
It 8 17 1
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
1
Lgate 1 9 5.618e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
+
6
-
18
22
MMED
9
20
MSTRO
RLGATE
LSOURCE
CIN
SOURCE
3
RLgate 1 9 56.1
RLdrain 2 5 15
RLsource 3 7 19.8
8
7
RSOURCE
RLSOURCE
S1A
12
S2A
RBREAK
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
15
13
8
14
13
17
18
RVTEMP
19
S1B
S2B
13
CB
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4e-4
Rgate 9 20 5.93e-1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
Rsource 8 7 RsourceMOD 1.3e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))}
.MODEL DbodyMOD D (IS=2e-10 N=1.05 RS=1.8e-3 TRS1=9e-4 TRS2=1e-6 + CJO=4.9e-9 M=4.9e-1 TT=1e-13 XTI=0)
.MODEL DbreakMOD D (RS=2.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=3.5e-9 IS=1e-30 N=10 M=4.7e-1)
.MODEL MstroMOD NMOS (VTO=2.1 KP=550 IS=1e-25 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.6 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=5.93e-1)
.MODEL MweakMOD NMOS (VTO=1.22 KP=1e-1 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=5.93 RS=1e-1)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7e-7)
.MODEL RdrainMOD RES (TC1=1.2e-2 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.5e-9 TC2=5e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.9e-3 TC2=-9e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-3.5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-0.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
SABER Electrical Model
REV Nov 2001
template ISL9N302AP3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e-10,nl=1.05,rs=1.8e-3,trs1=9e-4,trs2=1e-6,cjo=4.9e-9,m=4.9e-1,tt=1e-13,xti=0)
dp..model dbreakmod = (rs=2.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=3.5e-9,isl=10e-30,nl=10,m=4.7e-1)
m..model mstrongmod = (type=_n,vto=2.1,kp=550,is=1e-25, tox=1)
m..model mmedmod = (type=_n,vto=1.6,kp=30,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.22,kp=1e-1,is=1e-40, tox=1,rs=1e-1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.5,voff=-1.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-3.5)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.1)
LDRAIN
DPLCAP
DRAIN
2
5
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.1,voff=-0.4)
c.ca n12 n8 = 5e-9
c.cb n15 n14 = 5.5e-9
c.cin n6 n8 = 1e-8
10
RLDRAIN
RSLC1
51
RSLC2
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
ISCL
DBREAK
11
50
-
RDRAIN
6
8
ESG
spe.ebreak n11 n7 n17 n18 = 30.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
DBODY
EVTHRES
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
RGATE
GATE
+
6
-
18
22
EBREAK
+
MMED
1
9
20
MSTRO
17
18
-
RLGATE
LSOURCE
i.it n8 n17 = 1
CIN
SOURCE
3
8
7
l.lgate n1 n9 = 5.618e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
RSOURCE
RLSOURCE
S1A
12
S2A
RBREAK
15
13
8
14
13
17
18
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 15
res.rlsource n3 n7 = 19.8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7e-7
res.rdrain n50 n16 = 4e-4, tc1=1.2e-2,tc2=2.5e-5
res.rgate n9 n20 = 5.93e-1
res.rslc1 n5 n51 = 1e-6, tc1=3.5e-9,tc2=5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.3e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.9e-3,tc2=-9e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
}
©2002 Fairchild Semiconductor Corporation
Rev. B January 2002
SPICE Thermal Model
JUNCTION
th
REV May 2001
TISL9N302AP3
CTHERM1 th 6 4.5e-3
CTHERM2 6 5 2e-2
CTHERM3 5 4 1.5e-2
CTHERM4 4 3 2.5e-2
CTHERM5 3 2 7e-2
CTHERM6 2 tl 2.5e-1
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
RTHERM1 th 6 2e-3
RTHERM2 6 5 8.5e-3
RTHERM3 5 4 6e-2
RTHERM4 4 3 8e-2
RTHERM5 3 2 9e-2
RTHERM6 2 tl 1e-1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
5
SABER Thermal Model
SABER thermal model TISL9N302AP3
template thermal_model th tl
thermal_c th, tl
4
3
2
{
ctherm.ctherm1 th 6 = 4.5e-3
ctherm.ctherm2 6 5 = 2e-2
ctherm.ctherm3 5 4 = 1.5e-2
ctherm.ctherm4 4 3 = 2.5e-2
ctherm.ctherm5 3 2 = 7e-2
ctherm.ctherm6 2 tl = 2.5e-1
rtherm.rtherm1 th 6 =2e-3
rtherm.rtherm2 6 5 = 8.5e-3
rtherm.rtherm3 5 4 = 6e-2
rtherm.rtherm4 4 3 = 8e-2
rtherm.rtherm5 3 2 = 9e-2
rtherm.rtherm6 2 tl = 1e-1
}
tl
CASE
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