NC7SP08FHX [FAIRCHILD]
AND Gate, P Series, 1-Func, 2-Input, CMOS, PDSO6, 1 X 1MM, 0.35 MM PITCH, MO-252, MICROPAK2-6;
| 型号： | NC7SP08FHX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | AND Gate, P Series, 1-Func, 2-Input, CMOS, PDSO6, 1 X 1MM, 0.35 MM PITCH, MO-252, MICROPAK2-6 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2010
NC7SP08 — TinyLogic® ULP Two-Input AND Gate
Features
Description
The NC7SP08 is a single two-input AND gate from
Fairchild’s Ultra Low Power (ULP) series of TinyLogic®.
Ideal for applications where battery life is critical, this
product is designed for ultra low power consumption
within the VCC operating range of 0.9V to 3.6V.
0.9V to 3.6V VCC Supply Operation
3.6V Over-Voltage Tolerant I/Os at VCC from
0.9V to 3.6V
Propagation Delay (tPD):
2.5ns Typical for 3.0V to 3.6V VCC
5.0ns Typical for 2.3V to 2.7V VCC
6.0ns Typical for 1.65V to 1.95V VCC
7.0ns Typical for 1.40V to 1.60V VCC
11.0ns Typical for 1.10V to 1.30V VCC
27.0ns Typical for 0.90V VCC
The internal circuit is composed of a minimum of
inverter stages, including the output buffer, to enable
ultra low static and dynamic power.
The NC7SP08, for lower drive requirements, is uniquely
designed for optimized power and speed and is
fabricated with an advanced CMOS technology to
achieve best-in-class speed of operation, while
maintaining extremely low CMOS power dissipation.
Power-Off High-Impedance Inputs and Outputs
Static Drive (IOH/IOL):
± 2.6mA at 3.00V VCC
± 2.1mA at 2.30V VCC
± 1.5mA at 1.65V VCC
± 1.0mA at 1.40V VCC
± 0.5mA at 1.10V VCC
± 20µA at 0.9V VCC
Quiet Series™ Noise / EMI Reduction Circuitry
Ultra Small MicroPak™ Packages
Ultra Low Dynamic Power
Ordering Information
Part Number
NC7SP08P5X
NC7SP08L6X
NC7SP08FHX
Top Mark
Package
Packing Method
P08
J9
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead MicroPak™, 1.00mm Wide
3000 Units on Tape & Reel
5000 Units on Tape & Reel
J9
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel
Notes:
1. TinyLogic ULP and ULP-A with up to 50% less
power consumption can extend battery life
significantly.
2. Battery Life=(Vbattery x Ibattery x 0.9) / (Pdevice) /
24hrs/day; where, Pdevice=(ICC
CC) + (CPD + CL)
x VCC2 x f.
x
V
3. Assumes ideal 3.6V Lithium Ion battery with
current rating of 900mAH and derated 90% and
device frequency at 10MHz, with CL=15pF load.
Figure 1. Battery Life vs. VCC Supply Voltage
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
Connection Diagrams
IEEE/IEC
&
A
B
Y
Figure 2. Logic Symbol
Pin Configurations
1
5
4
A
VCC
1
2
3
6
5
4
A
B
VCC
NC
Y
2
B
GND
3
GND
Y
Figure 3. SC70 (Top View)
Figure 4. MicroPak™ (Top Through View)
Function Table
Y = AB
Inputs
Output
A
L
B
L
Y
L
L
H
L
L
H
H
L
H
H
L = Low Logic Level
H = High Logic Level
Pin Definitions
Pin # SC70
Pin # MicroPak™
Name
A
Description
1
2
3
4
1
2
3
4
5
6
Input
B
Input
GND
Y
Ground
Output
NC
VCC
No Connect
5
Supply Voltage
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCC
VIN
Supply Voltage
-0.5
-0.5
-0.5
-0.5
4.6
4.6
V
V
DC Input Voltage
HIGH or LOW State(4)
VCC=0V
VCC to +0.5
4.6
V
VOUT
IIK
DC Output Voltage
V
DC Input Diode Current at VIN < 0V
-50
mA
V
OUT < 0V
-50
IOK
DC Output Diode Current
mA
VOUT > VCC
+50
IOH / IOL
DC Output Source/Sink Current
±50
mA
mA
°C
ICC or Ground DC VCC or Ground Current per Supply Pin
±50
TSTG
TJ
Storage Temperature Range
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 Seconds)
SC70-5
-65
+150
+150
+260
150
°C
TL
°C
PD
Power Dissipation at +85°C
MicroPak™-6
130
mW
V
MicroPak2™-6
120
Human Body Model
JEDEC: JESD22-A114
JEDEC: JESD22-C101
4000
2000
ESD
Charged Device Model
Note:
4. The IO maximum rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Supply Voltage
Input Voltage(5)
Conditions
Min.
Max.
Unit
VCC
VIN
0.9
0
3.6
3.6
V
V
HIGH or LOW State
VCC=0V
CC=3.0V to 3.6V
0
VCC
3.6
VOUT
Output Voltage
V
0
V
±2.6
±2.1
±1.5
±1.0
±0.5
20.0
+85
10
VCC=2.3V to 2.7V
VCC=1.65V to 1.95V
VCC=1.40V to 1.60V
VCC=1.10V to 1.30V
VCC=0.9V
mA
IOH / IOL Output Current in IOH / IOL
µA
°C
TA
Free Air Operating Temperature
Minimum Input Edge Rate
-40
VIN=0.8V to 2.0V, VCC=3.0V
SC70-5
ns/V
Δt / ΔV
425
500
560
Thermal Resistance
MicroPak™-6
°C/W
θJA
MicroPak2™-6
Note:
5. Unused inputs must be held HIGH or LOW. They may not float.
© 2001 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7SP08 • Rev. 1.0.4
3
DC Electrical Characteristics
TA=+25°C
TA=-40 to +85°C
Symbol
Parameter
VCC
Conditions
Units
Min.
Max.
Min.
Max.
0.90
0.65 x VCC
0.65 x VCC
0.65 x VCC
0.65 x VCC
1.6
0.65 x VCC
0.65 x VCC
0.65 x VCC
0.65 x VCC
1.6
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0.90
HIGH Level Input
Voltage
VIH
V
2.1
2.1
0.35 x VCC
0.35 x VCC
0.35 x VCC
0.35 x VCC
0.7
0.35 x VCC
0.35 x VCC
0.35 x VCC
0.35 x VCC
0.7
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0.90
LOW Level Input
Voltage
VIL
V
0.9
0.9
V
CC - 0.1
VCC - 0.1
VCC - 0.1
VCC - 0.1
VCC - 0.1
VCC - 0.1
VCC - 0.1
0.70 x VCC
0.99
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0.90
VCC - 0.1
VCC - 0.1
VCC - 0.1
VCC - 0.1
VCC - 0.1
0.75 x VCC
1.07
IOH=-20µA
HIGH Level Output
Voltage
VOH
V
IOH=-0.5mA
IOH=-1mA
IOH=-1.5mA
IOH=-2.1mA
IOH=-2.6mA
1.24
1.22
1.95
1.87
2.61
2.55
0.1
0.1
0.1
0.1
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0.1
0.1
IOL=20µA
0.1
0.1
0.1
0.1
LOW Level Output
Voltage
VOL
0.1
0.1
V
IOL=0.5mA
IOL=1mA
0.30 x VCC
0.31
0.31
0.31
0.31
0.30 x VCC
0.37
0.35
0.33
0.33
IOL=1.5mA
IOL=2.1mA
IOL=2.6mA
Input Leakage
Current
IIN
IOFF
ICC
0.90 to 3.60
0
0 ≤ VIN ≤ 3.6V
±0.1
0.5
±0.5
0.5
µA
µA
µA
Power Off Leakage
Current
0 ≤ (VO, VIN)
≤ 3.6V
Quiescent Supply
Current
0.90 to 3.60
VIN=VCC or GND
0.9
0.9
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
4
AC Electrical Characteristics
TA=+25°C
TA=-40 to +85°C
Symbol
Parameter
VCC
Conditions
Units Figure
Min. Typ. Max. Min.
Max.
0.90
27.0
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0.90
3.5
2.5
2.0
1.5
1.0
11.0 21.8
3.0
2.0
1.5
1.0
1.0
34.3
15.0
12.2
9.9
7.0
6.0
14.8
12.0
9.4
CL=10pF,
RL=1MΩ
5.0
4.0
8.3
9.0
30.0
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0.90
4.0
3.0
2.5
2.0
1.5
11.0 22.8
3.5
2.5
2.0
1.5
1.0
37.3
16.5
13.6
10.8
9.5
8.0
6.0
15.5
12.6
9.9
CL=15pF,
RL=1MΩ
Figure 1,
ns
tPHL, tPLH Propagation Delay
Figure 2
5.0
4.0
8.7
32.0
1.10 ≤ VCC ≤ 1.30
1.40 ≤ VCC ≤ 1.60
1.65 ≤ VCC ≤ 1.95
2.30 ≤ VCC ≤ 2.70
3.00 ≤ VCC ≤ 3.60
0
5.0
4.0
3.0
2.0
1.5
13.0 25.9
4.0
3.5
2.0
1.5
1.0
46.3
18.2
15.9
12.8
10.7
9.0
7.0
6.0
5.0
2
17.8
14.4
11.3
9.2
CL=30pF,
RL=1MΩ
CIN
Input Capacitance
pF
pF
Power Dissipation
Capacitance
VIN=0V or VCC
f=10MHz
,
CPD
0.90 to 3.60
6
Figure 5. AC Test Circuit
Figure 6. AC Waveforms
Symbol
VCC
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC / 2
1.8V ± 0.15V
VCC / 2
1.5V ± 0.1V
1.2V ± 0.1V
VCC / 2
0.9V
Vmi
VCC / 2
VCC / 2
VCC / 2
VCC / 2
Vmo
1.5V
VCC / 2
VCC / 2
VCC / 2
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
5
Physical Dimensions
Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
3000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
P5X
Trailer (Hub End)
75 (Typical)
Empty
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
6
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
TOP VIEW
A
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 8. 6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
L6X
Trailer (Hub End)
75 (Typical)
Empty
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
7
Physical Dimensions
0.89
0.35
0.05 C
2X
1.00
B
A
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05 C
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
5X
0.25
0.60
6
5
4
0.10
.05
C B A
0.40
0.30
0.35
(0.08)
4X
C
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 9. 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
FHX
Trailer (Hub End)
75 (Typical)
Empty
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
8
© 2001 Fairchild Semiconductor Corporation
NC7SP08 • Rev. 1.0.4
www.fairchildsemi.com
9
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