NC7SV17P5X_10_技术文档

December 2010

NC7SV17

TinyLogic^®ULP-A Single Buffer with Schmitt Trigger Input

Features

Description

The NC7SV17 is a single buffer with Schmitt trigger

input from Fairchild's Ultra-Low Power (ULP-A) Series

of TinyLogic^®. ULP-A is ideal for applications that

require extreme high speed, high drive, and low power.

This product is designed for a wide low-voltage

operating range (0.9V to 3.6V V_CC) and applications that

require more drive and speed than the TinyLogic^®ULP

series, but still offer best-in-class, low-power operation.

0.9V to 3.6V V_CCSupply Operation

3.6V Over-Voltage Tolerant I/Os at VCC from

0.9V to 3.6V

Extremely High Speed tPD

- 1.5ns: Typical for 2.7V to 3.6V V_CC

- 1.8ns: Typical for 2.3V to 2.7V V_CC

- 2.0ns: Typical for 1.65V to 1.95V V_CC

- 3.2ns: Typical for 1.4V to 1.6V V_CC

- 5.9ns: Typical for 1.1V to 1.3V V_CC

- 12.0ns: Typical for 0.9V V_CC

The NC7SV17 is uniquely designed for optimized power

and speed and is fabricated with an advanced CMOS

technology to achieve high-speed operation while

maintaining low CMOS power dissipation.

Power-Off High-Impedance Inputs and Outputs

High Static Drive (I_OH/I_OL

- ±24mA at 3.00V V_CC

- ±18mA at 2.30V V_CC

- ±6mA at 1.65V V_CC

- ±4mA at 1.4V V_CC

- ±2mA at 1.1V V_CC

- ±0.1mA at 0.9V V_CC

)

Uses Proprietary Quiet Series™ Noise/EMI

Reduction Circuitry

Ultra-Small MicroPak™ Packages

Ultra-Low Dynamic Power

Ordering Information

Part Number

Top Mark

Package

Packing Method

3000 Units on

Tape & Reel

NC7SV17P5X

V17

G5

5-Lead SC70, EIAJ SC-88a, 1.25mm Wide

5000 Units on

Tape & Reel

NC7SV17L6X

NC7SV17FHX

6-Lead MicroPak™, 1.00mm Wide

5000 Units on

Tape & Reel

G5

6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

TinyLogic® is a registered trademark of Fairchild Semiconductor Corporation.

MicroPak™ and Quiet Series™ are trademarks of Fairchild Semiconductor Corporation.

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

Battery Life

700

600

500

400

300

200

100

0

ULP (SP)

Battery Life

(Days)

ULP-A (SV)

UHS (SZ)

0.9 1.2 1.5 1.8

2.5 3.3 5.0

V_CCSupply Voltage

Figure 1. Battery Life vs. V_CCSupply Voltage

Notes:

1. TinyLogic^®ULP and ULP-A with up to 50% less power consumption can extend battery life significantly.

Battery Life = (V_battery•I_battery•.9)/(P_device)/24hrs/day

where, P_device= (I_CC• V_CC) + (C_PD+ C_L) • V_CC2• f.

2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at

10MHz, with C_L=15pF load.

Connection Diagram

IEEE/IEC

Y

A

1

Figure 2. Logic Symbol

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

2

Pin Configurations

1

5

4

NC

V_CC

1

2

3

6

5

4

NC

A

V_CC

NC

Y

2

A

GND

3

GND

Y

Figure 3. SC70 (Top View)

Figure 4. MicroPak™ (Top Through View)

Pin Definitions

Pin # SC70

Pin # MicroPak

Name

NC

A

Description

No Connect

1

2

3

4

5

1

2

3

4

6

5

Input

GND

Y

Ground

Output

V_CC

NC

Supply Voltage

No Connect

Function Table

Inputs

Output

A

L

Y

L

H

H=HIGH Logic Level

L=LOW Logic Level

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

3

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

Min.

-0.5

Max.

4.6

Unit

V

Supply Voltage

V_IN

DC Input Voltage

4.6

V

HIGH or LOW State⁽³⁾

V_CC+ 0.5

4.6

V_OUT

I_IK

DC Output Voltage

V

V_CC=0V

DC Input Diode Current

DC Output Diode Current

DC Output Source/Sink Current

V_IN< 0V

-50

mA

V_OUT< 0V

V_OUT> V_CC

-50

I_OK

+50

I_{OH/ OL}

I

±50

mA

°C

I_CCor I_GND

DC V_CCor Ground Current per Supply Pin

Storage Temperature Range

±50

T_STG

T_J

-65

+150

+260

150

Junction Temperature Under Bias

Junction Lead Temperature, Soldering 10 Seconds

SC70-5

°C

T_L

°C

P_D

Power Dissipation at +85°C

MicroPak™-6

MicroPak2™-6

130

mW

V

120

Human Body Model, JEDEC:JESD22-A114

Charge Device Model, JEDEC:JESD22-C101

4000

2000

ESD

Note:

3. IO absolute maximum rating must be observed.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_CC

Parameter

Supply Voltage

Conditions

Min.

0.9

0

Max.

3.6

V_CC

±24

±18

±6

Unit

V

V_IN

Input Voltage

V

V_CC=0V

HIGH or LOW State

_CC=3.0V to 3.6V

0

V_OUT

Output Voltage

V

0

V

V_CC=2.3V to 3.6V

V_CC=1.65V to 1.95V

V_CC=1.4V to 1.6V

V_CC=1.1V to 1.3V

V_CC=0.9V

I_OH/I_OL

Output Current in I_OH/I_OL

mA

±4

±2

±0.1

T_A

Operating Temperature, Free Air

Minimum Input Edge Rate

-40

+85

°C

V_IN=0.8V to 2.0, V_CC=3.0V

SC70-5

10

ns/V

Δt/ΔV

425

500

560

Thermal Resistance

MicroPak™-6

°C/W

θ_JA

MicroPak2™-6

Note:

4. Unused inputs must be held HIGH or LOW. They may not float.

www.fairchildsemi.com

NC7SV17 • Rev. 1.0.6

4

DC Electrical Characteristics

T_A=25°C

T_A=-40 to 85°C

Symbol Parameter

V_CC

Conditions

Units

Min.

Max.

Min.

Max.

0.90

1.10

0.30

0.40

0.50

0.70

1.00

1.50

0.10

0.15

0.20

0.25

0.40

0.60

0.07

0.08

0.09

0.15

0.25

0.60

V_CC-0.1

0.70

1.00

1.40

1.50

1.80

2.20

0.60

0.70

0.80

0.90

1.15

1.50

0.50

0.60

0.80

1.00

1.10

1.20

0.30

0.40

0.70

1.00

1.40

1.50

1.80

2.20

0.60

0.70

0.80

0.90

1.15

1.50

0.50

0.60

0.80

1.00

1.10

1.20

Positive

1.40

0.50

V_P

V_N

V_H

Threshold

Voltage

V

1.65

0.70

2.30

1.00

2.70

1.50

0.90

0.10

1.10

0.15

Negative

Threshold

Voltage

1.40

0.20

V

1.65

0.25

2.30

0.40

2.70

0.60

0.90

0.07

1.10

0.08

1.40

0.09

Hysteresis

Voltage

V

1.65

0.15

2.30

0.25

2.70

0.60

0.90

V_CC-0.1

V_CC-0.2

.75 x V_CC

1.25

V

_CC-0.1

_CC-0.2

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70≤ V_CC≤ 3.60

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

I_OH=-100µA

I

_OH=-2mA

_OH=-4mA

_OH=-6mA

.75 x V_CC

1.25

2.0

HIGH Level

Output Voltage

V_OH

V

2.0

I

_OH=-12mA

_OH=-18mA

_OH=-24mA

1.8

2.2

1.7

2.4

2.2

Continued on following page…

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

5

DC Electrical Characteristics (Continued)

T_A=25°C

T_A=-40 to 85°C

Symbol

Parameter

V_CC

Conditions

Units

Min.

Max.

0.10

0.20

Min.

Max.

0.10

0.90

0.10

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

2.30≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

0.20

I

_OL=100µA

0.20

I

_OL=2mA

_OL=4mA

_OL=6mA

0.25 x V_CC

0.30

0.25 x V_CC

0.30

LOW Level

Output Voltage

V_OL

V

0.40

I_OL=12mA

0.40

0.60

I

_OL=18mA

_OL=24mA

0.40

0.55

Input Leakage

Current

I_IN

0.90 to 3.60

±0.1

±0.5

0.5

µA

0 ≤ V_IN≤ 3.60

Power Off

Leakage

Current

I_OFF

0

0.5

0.9

0 ≤ (V_IN,v_O) ≤ 3.60

V_IN=V_CC, or GND

0.9

Quiescent

Supply Current

I_CC

0.90 to 3.60

µA

±0.9

V_CC≤ V_IN≤ 3.6V

AC Electrical Characteristics

T_A=25°C

T_A=-40 to 85°C

Symbol Parameter

V_CC

Conditions

Units Figure

Min. Typ. Max. Min.

Max.

C_L=15pF,

R_L=1MΩ

0.90

12

2.0

1.0

0.8

0.7

5.9

3.2

2.0

1.8

1.5

10.0

6.1

5.2

3.7

3.3

1.0

0.9

0.7

0.6

0.5

14.9

7.0

6.2

4.4

3.8

1.10 ≤ V_CC≤ 1.30

1.40 ≤ V_CC≤ 1.60

1.65 ≤ V_CC≤ 1.95

2.30 ≤ V_CC≤ 2.70

2.70 ≤ V_CC≤ 3.60

C_L=15pF,

R_L=2kΩ

Propagation

t_PHL, t_PLH

Figure 5

ns

Delay

Figure 6

C_L=30pF,

R_L=500Ω

Input

C_IN

0

2

pF

Capacitance

Power

V_IN=0V or V_CC

f=10MHz

,

C_PD

Dissipation

0.90 to 3.60

10

Capacitance

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

6

AC Loadings and Waveforms

V_CC

TEST

SIGNAL

DUT

C_LpF

R_L

Figure 5. AC Test Circuit

Figure 6. AC Waveforms

V_CC

2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.1V

Symbol

3.3V ± 0.3V

1.5V

1.2V ± 0.1V

V_CC/2

0.9V

V_CC/2

V_mi

V_CC/2

V_mo

1.5V

V_CC/2

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

7

Physical Dimensions

Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

3000

Cavity Status Cover Type Status

Empty

Filled

Sealed

P5X

Trailer (Hub End)

75 (Typical)

Empty

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

8

Physical Dimensions

2X

0.05 C

1.45

B

(1)

2X

0.05 C

(0.49)

5X

(0.254)

1.00

(0.75)

(0.52)

1X

TOP VIEW

A

PIN 1 IDENTIFIER

5

0.55MAX

(0.30)

6X

PIN 1

0.05 C

0.05

0.00

RECOMMENED

LAND PATTERN

0.05 C

C

0.45

0.35

0.10

6X

0.00

0.25

6X

0.15

1.0

DETAIL A

0.10

C B A

0.40

0.30

0.05

C

0.35

0.25

5X

0.40

0.30

DETAIL A

PIN 1 TERMINAL

0.075 X 45

CHAMFER

0.5

BOTTOM VIEW

(0.05)

6X

(0.13)

4X

Notes:

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

2. DIMENSIONS ARE IN MILLIMETERS

3. DRAWING CONFORMS TO ASME Y14.5M-1994

4. FILENAME AND REVISION: MAC06AREV4

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY

OTHER LINE IN THE MARK CODE LAYOUT.

Figure 8. 6-Lead, MicroPak™, 1.0mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

L6X

Trailer (Hub End)

75 (Typical)

Empty

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

9

Physical Dimensions

0.89

0.35

0.05 C

2X

1.00

B

A

5X 0.40

1X 0.45

PIN 1

0.66

MIN 250uM

1.00

6X 0.19

0.05 C

TOP VIEW

RECOMMENDED LAND PATTERN

FOR SPACE CONSTRAINED PCB

2X

0.90

0.35

0.05 C

0.55MAX

C

5X 0.52

SIDE VIEW

0.73

0.57

1X

(0.08) 4X

0.09

0.19

6X

DETAIL A

1

2

3

0.20 6X

ALTERNATIVE LAND PATTERN

FOR UNIVERSAL APPLICATION

(0.05) 6X

0.35

5X

0.25

0.60

6

5

4

0.10

.05 C

C B A

0.40

0.30

0.35

(0.08)

4X

BOTTOM VIEW

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

B. DIMENSIONS ARE IN MILLIMETERS.

0.075X45°

CHAMFER

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

DESIGN.

DETAIL A

PIN 1 LEAD SCALE: 2X

E. DRAWING FILENAME AND REVISION: MGF06AREV3

Figure 9. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

FHX

Trailer (Hub End)

75 (Typical)

Empty

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

10

NC7SV17 • Rev. 1.0.6

www.fairchildsemi.com

11


型号：	NC7SV17P5X_10
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	TinyLogicÂ® ULP-A Single Buffer with Schmitt Trigger Input
文件：	总11页 (文件大小：553K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NC7SV17P5X_10 [FAIRCHILD]

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