NC7SZ08L6X_09_技术文档

September 2009

NC7SZ08

TinyLogic^®UHS Two-Input AND Gate

Features

Description

The NC7SZ08 is a single two-input AND gate from

Fairchild’s Ultra-High Speed (UHS) series of

TinyLogic^®. The device is fabricated with advanced

CMOS technology to achieve ultra-high speed with high

output drive while maintaining low static power

dissipation over a broad V_CCoperating range. The

devise is specified to operate over the 1.65V to 5.5V

V_CCoperating range. The inputs and output are high

impedance when V_CCis 0V. Inputs tolerate voltages up

to 6V, independent of V_CCoperating voltage.

Ultra-High Speed: t_PD2.7ns (Typical) into 50pF at

5V V_CC

High Output Drive: ±24mA at 3V V_CC

Broad V_CCOperating Range: 1.65V to 5.5V

Matches Performance of LCX Operated at 3.3V V_CC

Power Down High Impedance Inputs/Outputs

Over-Voltage Tolerance inputs facilitate 5V to 3V

Translation

Proprietary Noise/EMI Reduction Circuitry

Ultra-Small MicroPak™ Packages

Space-Saving SOT23 and SC70 Packages

Ordering Information

Packing

Part Number Top Mark

Package

Method

Eco Status

RoHS

3000 Units on

5-Lead SOT23, JEDEC MO-178 1.6mm

Tape & Reel

NC7SZ08M5X

NC7SZ08P5X

NC7SZ08L6X

NC7SZ08FHX

7Z08

Z08

GG

3000 Units on

5-Lead SC70, EIAJ SC-88a, 1.25mm Wide

Tape & Reel

RoHS

5000 Units on

6-Lead MicroPak™, 1.00mm Wide

Tape & Reel

RoHS

5000 Units on

6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch

Tape & Reel

GG

Green

For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

Connection Diagrams

IEEE/IEC

Figure 1. Logic Symbol

Pin Configurations

Figure 2. SC70 and SOT23 (Top View)

Figure 3. MicroPak (Top Through View)

Pin Definitions

Pin # SC70 / SOT23

Pin # MicroPak

Name

A

Description

1

2

3

4

5

1

2

3

4

6

5

Input

B

GND

Y

Ground

Output

V_CC

NC

Supply Voltage

No Connect

Function Table

Y=AB

Inputs

Output

A

L

B

L

Y

L

H

L

H

L

H

H = HIGH Logic Level

L = LOW Logic Level

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

2

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol

V_CC

Parameter

Min.

-0.5

Max.

6.0

Unit

V

Supply Voltage

V_IN

DC Input Voltage

DC Output Voltage

6.0

V

V_OUT

6.0

V

V_IN< -0.5V

_IN> 6.0V

V_OUT< -0.5V

_OUT> 6V, V_CC=GND

-50

I_IK

DC Input Diode Current

DC Output Diode Current

mA

V

+20

-50

I_OK

V

+20

±50

+150

+260

200

150

130

120

4000

2000

I_OUT

I_CCor I_GND

T_STG

DC Output Current

mA

°C

DC V_CCor Ground Current

Storage Temperature Range

Junction Temperature Under Bias

-65

T_J

°C

T_L

Junction Lead Temperature (Soldering, 10 Seconds)

SOT-23

°C

SC70-5

Power Dissipation at +85°C

MicroPak-6

P_D

mW

V

MicroPak2-6

Human Body Model, JESD22-A114

ESD

Charged Device Model, JESD22-C101

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

Parameter

Supply Voltage Operating

Supply Voltage Data Retention

Input Voltage

Conditions

Min.

1.65

1.50

0

Max.

5.50

5.5

Unit

V_CC

V

V_IN

V_OUT

T_A

V

Output Voltage

0

V_CC

+85

20

Operating Temperature

-40

0

°C

V_CCat 1.8V, 2.5V ± 0.2V

V_CCat 3.3V ± 0.3V

V_CCat 5.0V ± 0.5V

SOT-23

t_r, t_f

Input Rise and Fall Times

Thermal Resistance

ns/V

0

10

0

5

300

425

500

560

SC70-5

°C/W

θ_JA

MicroPak-6

MicroPak2-6

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

www.fairchildsemi.com

NC7SZ08 • Rev. 1.0.3

3

DC Electrical Characteristics

T_A=25°C

Typ. Max.

T_A=-40 to +85°C

Symbol

Parameter

V_CC

Conditions

Units

Min.

Max.

1.65 to 1.95

2.30 to 5.50

1.65 to 1.95

2.30 to 5.50

1.65

0.75V_CC

0.70V_CC

0.75V_CC

0.70V_CC

HIGH Level Input

Voltage

V_IH

V_IL

V

0.25V_CC

0.30V_CC

0.25V_CC

0.30V_CC

LOW Level Input

Voltage

1.55

1.70

2.20

2.90

4.40

1.29

1.90

2.50

2.40

3.90

1.65

1.80

2.30

3.00

4.50

1.52

2.15

2.80

2.68

4.20

0.00

0.80

0.10

0.15

0.22

1.55

1.70

2.20

2.90

4.40

1.29

1.90

2.40

2.30

3.80

1.80

V_IN=V_IH, I_OH=-100µA

2.30

3.00

V

4.50

HIGH Level

Output Voltage

V_OH

1.65

I_OH=-4mA

I_OH=-8mA

I_OH=-16mA

I_OH=-24mA

2.30

3.00

4.50

I_OH=-32mA

1.65

0.10

0.24

0.30

0.40

0.55

0.10

0.24

0.30

0.40

0.55

1.80

V_IN=V_IL, I_OL=100µA

2.30

3.00

V

4.50

LOW Level

Output Voltage

V_OL

1.65

I_OL=4mA

I_OL=8mA

I_OL=16mA

I_OL=24mA

I_OL=32mA

2.30

3.00

4.50

Input Leakage

Current

I_IN

I_OFF

I_CC

0 to 5.5

0

V_IN=5.5V, GND

±1

1

±10

10

µA

Power Off

Leakage Current

V_INor V_OUT=5.5V

Quiescent Supply

Current

1.65 to 5.50 V_IN=5.5V, GND

2

20

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

4

AC Electrical Characteristics

T_A=25°C

Typ. Max.

T_A=-40 to +85°C

Symbol

Parameter

V_CC

Conditions

Units Figure

Min.

2.0

0.8

0.5

1.5

0.8

Min.

2.0

0.8

0.5

1.5

0.8

Max.

12.7

10.5

7.5

6.3

5.2

3.4

2.6

2.2

3.3

2.7

4

12.0

10.0

7.0

1.65

1.80

C_L=15pF,

R_L=1MΩ

2.50 ± 0.20

3.30 ± 0.30

5.00 ± 0.50

3.30 ± 0.30

5.00 ± 0.50

0.00

Figure 4

ns

5.0

t_PLH, t_PHLPropagation Delay

4.7

Figure 5

4.4

4.1

5.5

5.2

C_L=50pF,

R_L=500Ω

4.5

4.8

C_IN

Input Capacitance

pF

20

3.30

Power Dissipation

Capacitance⁽²⁾

C_PD

pF

Figure 6

25

5.00

Note:

2.

C_PDis defined as the value of the internal equivalent capacitance which is derived from dynamic operating

current consumption (I_CCD) at no output lading and operating at 50% duty cycle. C_PDis related to I_CCDdynamic

operating current by the expression: I_CCD=(C_PD)(V_CC)(f_IN)+(I_CCstatic).

Notes:

3. C_Lincludes load and stray capacitance.

4. Input PRR=1.0MHz; t_W500ns.

Figure 4. AC Test Circuit

Figure 5. AC Waveforms

Note:

5. Input=AC Waveform; t_r=t_f=1.8ns; PRR=10MHz; Duty Cycle=50%.

Figure 6. I_CCDTest Circuit

www.fairchildsemi.com

NC7SZ08 • Rev. 1.0.3

5

Physical Dimensions

SYMM

C

L

3.00

2.80

0.95

A

5

4

B

3.00

2.60

1.70

1.50

2.60

1

2

3

(0.30)

1.00

0.50

0.30

0.95

0.20

C

A B

1.90

0.70

TOP VIEW

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.30

0.90

1.45 MAX

C

0.15

0.05

0.22

0.08

0.10 C

NOTES: UNLESS OTHEWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MO-178, ISSUE B, VARIATION AA,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

GAGE PLANE

0.25

C) MA05Brev5

8°

0°

0.55

0.35

SEATING PLANE

0.60 REF

Figure 7. 5-Lead SOT23, JEDEC MO-178 1.6mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/SOT23-5L_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

3000

Cavity Status Cover Type Status

Empty

Filled

Sealed

M5X

Trailer (Hub End)

75 (Typical)

Empty

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

6

Physical Dimensions

Figure 8. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

3000

Cavity Status Cover Type Status

Empty

Filled

Sealed

P5X

Trailer (Hub End)

75 (Typical)

Empty

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

7

Physical Dimensions

2X

0.05 C

1.45

B

(1)

2X

0.05 C

(0.49)

5X

1.00

(0.75)

(0.52)

1X

A

TOP VIEW

0.55MAX

(0.30)

6X

PIN 1

0.05 C

0.05

0.00

RECOMMENED

LAND PATTERN

0.05 C

C

0.45

0.35

0.10

6X

0.00

0.25

6X

0.15

1.0

DETAIL A

0.10

C B A

0.40

0.30

0.05

C

0.35

0.25

5X

0.40

0.30

DETAIL A

PIN 1 TERMINAL

0.075 X 45

CHAMFER

0.5

BOTTOM VIEW

(0.05)

6X

(0.13)

4X

Notes:

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

2. DIMENSIONS ARE IN MILLIMETERS

3. DRAWING CONFORMS TO ASME Y14.5M-1994

MAC06AREVC

Figure 9. 6-Lead, MicroPak™, 1.0mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

L6X

Trailer (Hub End)

75 (Typical)

Empty

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

8

Physical Dimensions

DETAIL A

5X

Figure 10. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specification

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator

Tape Section

Leader (Start End)

Carrier

Cavity Number

125 (Typical)

5000

Cavity Status Cover Type Status

Empty

Filled

Sealed

FHX

Trailer (Hub End)

75 (Typical)

Empty

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

9

NC7SZ08 • Rev. 1.0.3

www.fairchildsemi.com

10


型号：	NC7SZ08L6X_09
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	TinyLogicÂ® UHS Two-Input AND Gate 栅
文件：	总10页 (文件大小：541K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NC7SZ08L6X_09 [FAIRCHILD]

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