NC7WZ14L6XF113 [FAIRCHILD]
Inverter, LVC/LCX/Z Series, 2-Func, 1-Input, CMOS, PDSO6, 1 MM, ROHS COMPLIANT, MO-252UAAD, MICROPAK-6;
| 型号： | NC7WZ14L6XF113 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Inverter, LVC/LCX/Z Series, 2-Func, 1-Input, CMOS, PDSO6, 1 MM, ROHS COMPLIANT, MO-252UAAD, MICROPAK-6 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2011
NC7WZ14
TinyLogic® UHS Dual Inverter with Schmitt Trigger
Inputs
Features
Description
The NC7WZ14 is a dual inverter with Schmitt trigger input
from Fairchild's Ultra-High Speed (UHS) Series of
TinyLogic. The device is fabricated with advanced CMOS
technology to achieve ultra-high speed with high output
drive while maintaining low static power dissipation over a
very broad VCC operating range. The device is specified to
operate over the 1.65V to 5.5V VCC range. The inputs and
outputs are high-impedance when VCC is 0V. Inputs
tolerate voltages up to 7V independent of VCC operating
voltage. Schmitt trigger inputs achieve typically 1V
hysteresis between the positive-and negative-going input
threshold voltage at 5V.
.
Ultra-High Speed: tPD 3.2ns (Typical) into 50pF at
5V VCC
.
.
.
High Output Drive: ±24mA at 3V VCC
Broad VCC Operating Range: 1.65V to 5.5V
Matches Performance of LCX when Operated at
3.3V VCC
.
.
Power Down High Impedance Inputs/Outputs
Over-Voltage Tolerance Inputs Facilitate 5V to 3V
Translation
.
.
.
Proprietary Noise/EMI Reduction Circuitry
Ultra-Small MicroPak™ Packages
Space-Saving SC70 Package
Ordering Information
Operating
Temperature
Top
Mark
Packing
Part Number
Package
Method
3000 Units on
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
Tape & Reel
NC7WZ14P6X
NC7WZ14EP6X
NC7WZ14L6X
NC7WZ14FHX
-40 to +85°C
Z14
Z14
A9
3000 Units on
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
Tape & Reel
-40 to +125°C
-40 to +85°C
-40 to +85°C
5000 Units on
6-Lead MicroPak™, 1.00mm Wide
Tape & Reel
5000 Units on
6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch
Tape & Reel
A9
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
Connection Diagrams
IEEC/IEC
Figure 1. Logic Symbol
Pin Configurations
A
Y
1
1
2
3
6
5
4
1
GND
V
CC
A
2
Y
2
Figure 2. SC70 (Top View)
Figure 3. MicroPak (Top Through View)
AAA
Pi n On e
Notes:
1. AAA represents Product Code Top Mark (see ordering code).
2. Orientation of Top Mark determines Pin One location. Read the top product code mark left to right.
Pin One is the lower left pin.
Figure 4. SC70 Pin 1 Orientation
Pin Definitions
Pin # SC70
Pin # MicroPak
Name
A1
Description
1
2
3
4
5
6
1
2
3
4
5
6
Input
GND
A2
Ground
Input
Y2
Output
VCC
Y1
Supply Voltage
Output
Function Table
Y= /A
Inputs
Output
A
L
Y
H
L
H
H = HIGH Logic Level
L = LOW Logic Level
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
-0.5
-0.5
-0.5
Max.
7.0
Unit
V
Supply Voltage
VIN
DC Input Voltage
7.0
V
VOUT
IIK
DC Output Voltage
7.0
V
DC Input Diode Current
DC Output Diode Current
DC Output Current
VIN < -0.5V
VOUT < -0.5V
-50
mA
mA
mA
mA
°C
°C
°C
IOK
-50
IOUT
±100
±50
ICC or IGND
TSTG
TJ
DC VCC or Ground Current
Storage Temperature Range
Junction Temperature Under Bias
-65
+150
+150
+260
170
TL
Junction Lead Temperature (Soldering, 10 Seconds)
TA=85°C
TA=125°C
SC70-6
104
PD
Power Dissipation
mW
V
MicroPak-6
130
MicroPak2-6
120
Human Body Model, JEDEC:JESD22-A114
Charge Device Model, JEDEC:JESD22-C101
4000
2000
ESD
Recommended Operating Conditions(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Supply Voltage Operating
Supply Voltage Data Retention
Input Voltage
Conditions
Min.
1.65
1.5
0
Max.
5.50
5.5
Unit
VCC
V
VIN
5.5
V
V
VOUT
Output Voltage
0
VCC
+125
+85
+85
390
500
560
SC70-6
-40
-40
-40
TA
Operating Temperature
Thermal Resistance
MicroPak-6
MicroPak2-6
SC70-6
°C
MicroPak-6
MicroPak2-6
°C/W
JA
Note:
3. Unused inputs must be held HIGH or LOW. They may not float.
© 1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ14 • Rev. 1.0.7
3
DC Electrical Characteristics
TA=-40 to
+85°C
TA=-40 to
+125°C
TA=+25°C
Symbol
Parameter
VCC (V)
Conditions
Units
Min. Typ. Max. Min. Max.
Min.
Max.
1.65
1.80
2.30
3.00
4.50
5.50
1.65
1.80
2.30
3.00
4.50
5.50
1.65
1.80
2.30
3.00
4.50
5.50
1.65
1.80
2.30
3.00
4.50
1.65
2.30
3.00
3.00
4.50
1.65
1.80
2.30
3.00
4.50
1.65
2.30
3.00
3.00
4.50
0.60
0.70
1.00
1.30
1.90
2.20
1.40
1.50
1.80
2.20
3.10
3.60
0.60
0.70
1.00
1.30
1.90
2.20
0.20
0.25
0.40
0.60
1.00
1.20
0.10
0.15
0.25
0.40
0.60
0.70
1.55
1.70
2.20
2.90
4.40
1.29
1.90
2.40
2.30
3.80
1.40
1.50
1.80
2.20
3.10
3.60
0.80
0.90
1.15
1.50
2.00
2.30
0.90
1.00
1.10
1.20
1.50
1.70
0.60
0.70
1.00
1.30
2.00
2.30
0.30
0.35
0.50
0.70
1.10
1.40
0.10
0.15
0.25
0.40
0.60
0.70
1.55
1.70
2.20
2.90
4.40
1.26
1.80
2.30
2.20
3.70
1.40
1.50
1.80
2.20
3.20
3.70
0.90
1.00
1.20
1.60
2.20
2.50
0.90
1.00
1.10
1.20
1.50
1.70
Positive Threshold
Voltage
VP
V
0.20 0.50 0.80
0.25 0.56 0.90
0.40 0.75 1.15
0.60 0.98 1.50
1.00 1.42 2.00
1.20 1.68 2.30
0.10 0.48 0.90
0.15 0.51 1.00
0.25 0.62 1.10
0.40 0.76 1.20
0.60 1.01 1.50
0.70 1.20 1.70
1.55 1.65
Negative Threshold
Voltage
VN
V
VH
Hysteresis Voltage
V
1.70 1.80
VIN=VIL,
IOH=-100µA
2.20 2.30
2.90 3.00
4.40 4.50
HIGH Level Output
Voltage
VOH
V
IOH=-4mA
IOH=-8mA
IOH=-16mA
IOH=-24mA
IOH=-32mA
1.29 1.52
1.90 2.14
2.40 2.75
2.30 2.62
3.80 4.13
0.00 0.10
0.10
0.10
0.10
0.10
0.10
0.24
0.30
0.40
0.55
0.55
0.10
0.10
0.10
0.10
0.10
0.26
0.32
0.43
0.60
0.60
0.00 0.10
VIN=VIH,
IOL=100µA
0.00 0.10
0.00 0.10
0.00 0.10
LOW Level Output
Voltage
VOL
V
IOL=4mA
0.08 0.24
0.10 0.30
IOL=8mA
IOL=16mA
IOL=24mA
IOL=32mA
0.16 0.40
0.24 0.55
0.25 0.55
Input Leakage
Current
IIN
IOFF
ICC
0 to 5.5
0
VIN=5.5V, GND
±0.1
1
±1.0
10
±2.0
20
µA
µA
µA
Power Off Leakage
Current
VIN or
VOUT=5.5V
Quiescent Supply
Current
1.65 to
5.50
VIN=5.5V, GND
1.0
10
20
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
4
AC Electrical Characteristics
TA=-40 to TA=-40 to
+85°C +125°C
TA=+25°C
Symbol
Parameter
VCC (V)
Conditions
Units Figure
Min. Typ. Max. Min. Max. Min. Max.
1.65
1.80
2.5 7.6
2.5 6.3
1.8 4.3
1.5 3.3
1.0 2.7
1.8 4.0
1.2 3.2
2.5
13.1
10.9
7.4
2.5
2.5
1.8
1.5
1.0
1.8
1.2
14.5
12.0
8.1
2.5
2.5
1.8
1.5
1.0
1.8
1.2
14.7
12.3
8.4
CL=15pF,
RL=1M
Figure 5
Figure 6
ns
2.50 ± 0.20
3.30 ± 0.30
5.00 ± 0.50
3.30 ± 0.30
5.00 ± 0.50
0.00
tPLH, tPHL Propagation Delay
5.0
5.5
5.8
4.1
4.5
4.8
6.0
6.6
6.9
CL=50pF,
RL=500
Figure 5
Figure 6
4.9
5.4
5.7
CIN
Input Capacitance
pF
3.30
11.0
Power Dissipation
Capacitance(4)
CPD
pF
Figure 7
5.00
12.5
Note:
4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating
current consumption (ICCD) at no output loading and operating at 50% duty cycle. CPD is related to ICCD dynamic
operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).
Note:
5. CL includes load and stray capacitance;
Input PRR=1.0MHz; tW=500ns
Figure 5. AC Test Circuit
Figure 6. AC Waveforms
Note:
6. Input=AC Waveform; tr=tf=1.8ns; PRR=variable; Duty Cycle =50%.
Figure 7. ICCD Test Circuit
© 1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7WZ14 • Rev. 1.0.7
5
Physical Dimensions
SYMM
C
L
±0.20
2.00
A
0.65
0.50 MIN
6
4
B
PIN ONE
±0.10
1.25
1.90
1
3
0.30
0.15
(0.25)
0.40 MIN
0.10
A B
1.30
0.65
1.30
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.00
0.80
1.10
0.80
0.10 C
0.10
0.00
C
2.10±0.30
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
GAGE
PLANE
A) THIS PACKAGE CONFORMS TO EIAJ
SC-88, 1996.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH.
(R0.10)
0.25
0.10
D) DRAWING FILENAME: MKT-MAA06AREV6
0.20
30°
0°
0.46
0.26
DETAIL A
SCALE: 60X
Figure 8. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
3000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
P6X
Trailer (Hub End)
75 (Typical)
Empty
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
6
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
TOP VIEW
A
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 9. 6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
L6X
Trailer (Hub End)
75 (Typical)
Empty
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
7
Physical Dimensions
0.89
0.35
0.05 C
2X
B
1.00
A
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05 C
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
0.25
5X
0.60
6
5
4
0.10
.05 C
C B A
0.40
0.30
0.35
(0.08)
4X
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 10. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
FHX
Trailer (Hub End)
75 (Typical)
Empty
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
8
© 1999 Fairchild Semiconductor Corporation
NC7WZ14 • Rev. 1.0.7
www.fairchildsemi.com
9
相关型号：
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NC7WZ16FHX
Buffer, LVC/LCX/Z Series, 2-Func, 1-Input, CMOS, PDSO6, 1 X 1MM, 0.35 MM PITCH, GREEN, MO-252, MICROPAK2-6
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