NC7WZ240 [FAIRCHILD]
TinyLogic. UHS Dual Inverting Buffer with 3-STATE Outputs; TinyLogic 。 UHS双反相缓冲器，具有3态输出
| 型号： | NC7WZ240 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TinyLogic. UHS Dual Inverting Buffer with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2001
Revised January 2005
NC7WZ240
TinyLogic UHS Dual Inverting Buffer
with 3-STATE Outputs
General Description
Features
■ Space saving US8 surface mount package
The NC7WZ240 is a Dual Inverting Buffer with indepen-
dent active LOW enables for the 3-STATE outputs. The
Ultra High Speed device is fabricated with advanced
CMOS technology to achieve superior switching perfor-
mance with high output drive while maintaining low static
power dissipation over a broad VCC operating range. The
■ MicroPak Pb-Free leadless package
■ Ultra High Speed; tPD 2.3 ns typ into 50 pF at 5V VCC
■ High Output Drive; ±24 mA at 3V VCC
■ Broad VCC Operating Range: 1.65V to 5.5V
device is specified to operate over the 1.65V to 5.5V VCC
■ Matches the performance of LCX when operated at
3.3V VCC
operating range. The inputs and outputs are high imped-
ance when VCC is 0V. Inputs tolerate voltages up to 5.5V
■ Power down high impedance inputs/outputs
independent of VCC operating range. Outputs tolerate volt-
ages above VCC when in the 3-STATE condition.
■ Overvoltage tolerant inputs facilitate 5V to 3V translation
■ Outputs are overvoltage tolerant in 3-STATE mode
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Product
Order
Package Code
Number Top Mark
Package Description
Supplied As
Number
NC7WZ240K8X MAB08A
NC7WZ240L8X MAC08A
WZ40
U7
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide 3k Units on Tape and Reel
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
5k Units on Tape and Reel
Pb-Free package per JEDEC J-STD-020B.
TinyLogic is a registered trademark of Fairchild Semiconductor Corporation.
MicroPak is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500398
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
IEEE/IEC
Pin Assignments for US8
Pin Descriptions
Pin Names
Description
OEn
An
Enable Inputs for 3-STATE Outputs
Inputs
(Top View)
Yn
3-STATE Outputs
Pin One Orientation Diagram
Function Table
Inputs
OE
Output
Yn
An
L
L
L
H
L
H
L
H
Z
H
H
Z
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
H = HIGH Logic Level
L = LOW Logic Level
Z = 3-STATE
Pad Assignment for MicroPak
(Top Through View)
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 3)
−0.5V to +7.0V
Supply Voltage (VCC
DC Input Voltage (VIN) (Note 2)
DC Output Voltage (VOUT
)
−0.5V to +7.0V Supply Voltage Operating (VCC
−0.5V to +7.0V Supply Voltage Data Retention (VCC
Input Voltage (VIN
)
1.65V to 5.5V
1.5V to 5.5V
0V to 5.5V
)
)
DC Input Diode Current (IIK
)
)
@VIN < 0V
−50 mA Output Voltage (VOUT
)
DC Output Diode Current (IOK
)
Active State
0V to VCC
0V to 5.5V
@VOUT < 0V
−50 mA
3-STATE
DC Output Source/Sink Current (IOUT
DC VCC/Ground Current (ICC/IGND
Storage Temperature Range (TSTG
)
± 50 mA Operating Temperature (TA)
± 100 mA Input Rise and Fall Time (tr, tf)
−40°C to +85°C
)
)
−65°C to +150°C
+150°C
V
CC @ 1.8V, 0.15V, 2.5V ± 0.2V
VCC @ 3.3V ± 0.3V
CC @ 5.0V ± 0.5V
Thermal Resistance (θJA
0 ns/V to 20 ns/V
0 ns/V to 10 ns/V
0 ns/V to 5 ns/V
250°C/W
Junction Lead Temperature under Bias (TJ)
Junction Lead Temperature (TL)
(Soldering, 10 seconds)
V
+260°C
)
Power Dissipation (PD) @ +85°C
250 mW
Note 1: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 2: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
Min
Typ
Max
Min
Max
VIH
HIGH Level Input Voltage
1.65 to 1.95 0.75 VCC
2.3 to 5.5 0.7 VCC
1.65 to 1.95
0.75 VCC
0.7 VCC
V
V
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.25 VCC
0.3 VCC
0.25 VCC
0.3 VCC
2.3 to 5.5
VOH
1.65
2.3
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
1.65
2.3
1.55
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
V
IN = VIH
I
OH = −100 µA
V
V
V
V
3.0
3.0
or VIL
4.5
4.5
1.65
2.3
1.52
2.15
2.80
2.68
4.20
0.0
I
I
I
I
I
OH = −4 mA
OH = −8 mA
OH = −16 mA
OH = −24 mA
OH = −32 mA
V
IN = VIH
3.0
or VIL
3.0
4.5
VOL
LOW Level Output Voltage
1.65
2.3
0.10
0.10
0.10
0.10
0.24
0.3
0.10
0.10
0.10
0.10
0.24
0.3
0.0
V
IN = VIH
I
OL = 100 µA
3.0
0.0
or VIL
4.5
0.0
1.65
2.3
0.08
0.10
0.15
0.22
0.22
I
I
I
I
I
OL = 4 mA
OL = 8 mA
OL = 16 mA
OL = 24 mA
OL = 32 mA
3.0
0.4
0.4
3.0
0.55
0.55
±0.1
±0.5
0.55
0.55
±1
4.5
IIN
Input Leakage Current
0 to 5.5
1.65 to 5.5
µA
µA
V
V
IN = 5.5V, GND
IN = VIH or VIL
IOZ
3-STATE Output Leakage
±5
0 ≤ VOUT ≤ 5.5V
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
0.0
1
1
10
10
µA
µA
VIN or VOUT = 5.5V
1.65 to 5.5
VIN = 5.5V, GND
3
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Noise Characteristics
VCC
T
A = + 25°C
Max
Symbol
Parameter
Units
Conditions
(V)
5.0
5.0
5.0
5.0
5.0
Typ
VOLP (Note 4) Quiet Output Maximum Dynamic VOL
VOLV (Note 4) Quiet Output Minimum Dynamic VOL
1.0
1.0
4.0
3.5
1.5
V
V
V
V
V
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
V
OHV (Note 4) Quiet Output Minimum Dynamic VOH
VIHD (Note 4) Minimum HIGH Level Dynamic Input Voltage
VILD (Note 4) Maximum LOW Level Dynamic Input Voltage
Note 4: Parameter guaranteed by design.
AC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Figure
Symbol
Parameter
Units
Conditions
(V)
Min
2.0
1.0
0.8
0.5
1.2
0.8
Typ
Max
12.0
7.5
Min
2.0
1.0
0.8
0.5
1.2
0.8
Max
13.0
8.0
Number
tPLH
,
Propagation Delay
An to Yn
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
C
L = 15 pF
D = 1 MΩ
tPHL
R
Figures
1, 3
ns
5.2
5.5
S1= Open
4.5
4.8
tPLH,
tPHL
Propagation Delay
An to Yn
5.7
6.0
C
L = 50 pF
D = 500Ω
Figures
1, 3
5.0
5.3
ns
ns
R
S1= Open
tOSLH
,
Output to Output Skew
(Note 5)
3.3 ± 0.3
5.0 ± 0.5
1.0
0.8
1.0
0.8
C
L = 50 pF
D = 500Ω
Figures
1, 3
tOSHL
R
S1= Open
L = 50 pF
RD, RU = 500 Ω
tPZL
,
Output Enable Time
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.5 ± 0.5
3.0
1.8
1.2
0.8
14.0
8.5
3.0
1.8
1.2
0.8
15.0
9.0
C
tPZH
Figures
1, 3
6.2
6.5
ns S1 = GND for tPZH
S1 = VI for tPZL
5.5
5.8
VI = 2 x VCC
tPLZ
,
Output Disable Time
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
2.5
1.5
0.8
0.3
12.0
8.0
2.5
1.5
0.8
0.3
13.0
8.5
CL = 50 pF
tPHZ
RD, RU = 500 Ω
ns S1 = GND for tPZH
S1 = VI for tPZL
Figures
1, 3
5.7
6.0
4.7
5.0
VI = 2 x VCC
CIN
Input Capacitance
0
2.5
4
pF
COUT
CPD
Output Capacitance
5.0
3.3
5.0
Power Dissipation Capacitance
10
12
pF (Note 6)
Figure 2
Note 5: Parameter guaranteed by design. tOSLH = |tPLHmax − tPLHmin|; tOSHL = |tPHLmax − tPHLmin|.
Note 6: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD dynamic operating current by the expression:
I
CCD = (CPD)(VCC)(fIN) + (ICCstatic).
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4
AC Loading and Waveforms
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tw = 500 ns
FIGURE 1. AC Test Circuit
Input = AC Waveform; tr = tf = 1.8 ns;
PRR = 10 MHz; Duty Cycle = 50%
FIGURE 2. ICCD Test Circuit
FIGURE 3. AC Waveforms
5
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Tape and Reel Specification
Tape Format for US8
Package
Tape
Section
Number
Cavities
125 (typ)
3000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
K8X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
Tape Format for MicroPak
Package
Tape
Section
Number
Cavities
125 (typ)
3000
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Leader (Start End)
Carrier
Sealed
L8X
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
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6
Tape and Reel Specification (Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165 0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(W1 + 2.00/−1.00)
8 mm
(177.8) (1.50) (13.00) (20.20) (55.00) (8.40 + 1.50/−0.00)
(14.40)
7
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Package Number MAC08A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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相关型号：
NC7WZ241K8X_NL
Bus Driver, LVC/LCX/Z Series, 2-Func, 1-Bit, True Output, CMOS, PDSO8, 3.10 MM, MO-187CA, US-8
FAIRCHILD
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