NM25C020LZEMT8 [FAIRCHILD]
EEPROM, 256X8, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8;
| 型号： | NM25C020LZEMT8 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDSO8, PLASTIC, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1997
NM25C020
2048-Bit Serial CMOS EEPROM (Serial Peripheral
™
Interface (SPI ) Synchronous Bus)
General Description
Features
n 2.1 MHz clock rate
n 2048-bits organized as 256 x 8
The NM25C020 is a 2048-bit CMOS EEPROM with a SPI
compatible serial interface. The NM25C020 is designed for
data storage in applications requiring both nonvolatile
memory and in-system data updates. This EEPROM is well
suited for applications using the 68HC11 series of microcon-
trollers that support the SPI interface for high speed commu-
nication with peripheral devices via a serial bus to reduce pin
count. The NM25C020 is implemented in Fairchild Semicon-
ductor’s floating gate CMOS process that provides superior
endurance and data retention.
n Multiple chips on the same 3-wire bus with separate
chip select lines
n Self-timed programming cycle
n Simultaneous programming of 1 to 4 bytes at a time
n Status register can be polled during programming to
monitor READY/BUSY
n Write Protect (WP ) pin and write disable instruction for
both hardware and software write protection
n Block write protect feature to protect against accidental
writes
n Endurance: 106 data changes
n Data retention greater than 40 years
n Packages available: 8-Pin DIP, 8-Pin SO or 8-Pin
TSSOP
The serial data transmission of this device requires four sig-
nal lines to control the device operation: Chip Select (CS ),
Clock (SCK), Serial Data In (SI), and Serial Data Out (SO).
All programming cycles are completely self-timed and do not
require an erase before WRITE.
BLOCK WRITE protection is provided by programming the
STATUS REGISTER with one of four levels of write protec-
tion. Additionally, separate write enable and write disable in-
structions are provided for data protection.
Hardware data protection is provided by the WP pin to pro-
tect against accidental data changes. The HOLD pin allows
the serial communication to be suspended without resetting
the serial sequence.
Block Diagram
DS012400-1
™
SPI is a trademark of Motorola, Inc.
© 1997 Fairchild Semiconductor Corporation
DS012400
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PrintDate=1997/08/04 PrintTime=17:25:43 5250 ds012400 Rev. No. 5 cmserv Proof
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Connection Diagram
Dual-In-Line Package (N)
SO Package (M8) and
TSSOP Package (MT8)
DS012400-2
Top View
See Package Number
N08E (N), M08A (M8) and MTC08 (MT8)
Pin Names
CS
Chip Select Input
Serial Data Output
Write Protect
SO
WP
VSS
SI
Ground
Serial Data Input
Serial Clock Input
Suspends Serial Input
Power Supply
SCK
HOLD
VCC
Ordering Information
Commercial Temperature Range (0˚C to +70˚C)
Order Number
NM25C020N/LN/LZN
NM25C020M8/LM8/LZM8
NM25C020MT8/LMT8/LZMT8
Extended Temperature Range (−40˚C to +85˚C)
Order Number
NM25C020EN/LEN/LZEN
NM25C020EM8/LEM8/LZEM8
NM25C020EMT8/LEMT8/LZEMT8
Automotive Temperature Range (−40˚C to +125˚C)
Order Number
NM25C020VN/LVN/LZVN
NM25C020VM8/LVM8/LZVM8
NM25C020VMT8/LVMT8/LZVMT8
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Standard Voltage 4.5V ≤ VCC
≤
ESD Rating
2000V
5.5V Specifications
Operating Conditions
Absolute Maximum Ratings (Note 1)
Ambient Operating Temperature
NM25C020
0˚C to +70˚C
−40˚C to +85˚C
−40˚C to +125˚C
4.5V–5.5V
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
−65˚C to +150˚C
NM25C020E
NM25C020V
+6.5V to −0.3V
+300˚C
Power Supply (VCC
)
(Soldering, 10 seconds)
DC and AC Electrical Characteristics
Symbol
Parameter
Operating Current
Standby Current
Input Leakage
Part Number
Conditions
Min
Max
Units
mA
µA
µA
µA
V
=
ICC
CS VIL
3
50
1
=
CS VCC
ICCSB
IIL
=
VIN 0 to VCC
−1
−1
=
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
VOUT GND to VCC
+1
*
VIL
−0.3
VCC 0.3
*
VIH
0.7 VCC
VCC + 0.3
0.4
V
=
VOL
VOH
fOP
IOL 1.6 mA
V
=
IOH −0.8 mA
VCC − 0.8
V
NM25C020
2.1
2.0
2.0
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tRI
Input Rise Time
tFI
Input Fall Time
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
Minimum CS High Time
CS Setup Time
NM25C020
NM25C020
NM25C020
NM25C020
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
Data Setup Time
HOLD Setup Time
CS Hold Time
NM25C020
NM25C020
240
100
90
Data Hold Time
HOLD Hold Time
Output Delay
=
NM25C020
NM25C020
NM25C020
NM25C020
CL 200 pF
240
100
240
100
10
tLZ
HOLD Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
=
tDF
CL 200 pF
tHZ
tWP
1–4 Bytes
Capacitance
AC Test Conditions
Output Load
=
=
TA 25˚C, f 1 MHz
=
CL 200 pF
Symbol
COUT
CIN
Test
Type Max
Units
pF
pF
* *
0.1 VCC – 0.9 VCC
Input Pulse Levels
Timing Measurement
Reference Level
Output Capacitance
Input Capacitance
3
2
8
6
*
*
0.3 VCC – 0.7 VCC
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 2: The SCK frequency specification specifies a minimum clock period of 476 ns; therefore, in a SCK clock cycle, t
CLH
+ t
must be ≥476 ns. For example,
CLL
=
=
if t
190 ns, then the minimum t
CLH
286 ns in order to meet the SCK frequency specification.
CLL
Note 3: CS must be brought high for a minimum of 240 ns (t ) between consecutive instruction cycles.
CSH
3
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PrintDate=1997/08/04 PrintTime=17:25:48 5250 ds012400 Rev. No. 5 cmserv Proof
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Low Voltage 2.7V ≤ VCC ≤ 5.5V
ESD Rating
2000V
Specifications
Operating Conditions
Absolute Maximum Ratings (Note 4)
Ambient Operating Temperature
NM25C020L/LZ
0˚C to +70˚C
−40˚C to +85˚C
−40˚C to +125˚C
2.7V–5.5V
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
−65˚C to +150˚C
NM25C020LE/LZE
NM25C020LV/LZV
+6.5V to −0.3V
+300˚C
Power Supply (VCC
)
(Soldering, 10 seconds)
DC and AC Electrical Characteristics
Symbol
ICC
Parameter
Operating Current
Standby Current
Part Number
Conditions
Min
Max
Units
=
CS VIL
3
mA
=
ICCSB
Z
CS VCC
10
1
µA
LZ
=
IIL
Input Leakage
VIN 0 to VCC
−1
+1
+1
µA
µA
V
=
VOUT GND to VCC
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
*
VIL
−0.3
0.3 VCC
*
VIH
VOL
VOH
fOP
tRI
0.7 VCC
VCC + 0.3
0.4
V
=
IOL 0.8 mA
V
=
IOH −0.4 mA
VCC − 0.8
V
1
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Input Rise Time
2.0
2.0
tFI
Input Fall Time
tCLH
tCLL
tCSH
tCSS
tDIS
tHDS
tCSN
tDIN
tHDN
tPD
Clock High Time
Clock Low Time
Minimum CS High Time
CS Setup Time
(Note 5)
(Note 5)
(Note 6)
410
410
500
500
100
240
500
100
240
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
=
CL 200 pF
500
240
500
240
10
tLZ
HOLD Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
=
tDF
CL 200 pF
tHZ
tWP
1–4 Bytes
Capacitance
AC Test Conditions
Output Load
=
=
TA 25˚C, f 1 MHz
=
CL 200 pF
Symbol
COUT
CIN
Test
Type Max
Units
pF
pF
* *
0.1 VCC − 0.9 VCC
Input Pulse Levels
Timing Measurement
Reference Level
Output Capacitance
Input Capacitance
3
2
8
6
*
*
0.3 VCC – 0.7 VCC
Note 4: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 5: The SCK frequency specification specifies a minimum clock period of 476 ns; therefore, in a SCK clock cycle, t
CLH
+ t
must be ≥476 ns. For example,
CLL
=
=
if t
190 ns, then the minimum t
CLH
286 ns in order to meet the SCK frequency specification.
CLL
Note 6: CS must be brought high for a minimum of 240 ns (t
) between consecutive instruction cycles.
CSH
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AC Test Conditions (Continued)
DS012400-3
FIGURE 1. Synchronous Data Timing Diagram
DS012400-4
Note: When connected to the SPI port of a 68HC11 microcontroller, the NM25C020 accepts a clock phase of 0 and a clock parity of 0.
FIGURE 2. SPI Serial Interface
5
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PROTOCOL: When connected to the SPI port of a 68HC11
microcontroller, the NM25C020 accepts a clock phase of 0
and a clock polarity of 0. The SPI protocol for this device de-
fines the byte transmitted on the SI and SO data lines for
proper chip operation. See Figure 3.
Functional Description
MASTER: The device that generates the serial clock is des-
ignated as the master. The NM25C020 can never function as
a master.
SLAVE: The NM25C020 always operates as a slave as the
serial clock pin is always an input.
HOLD: The HOLD pin is used in conjunction with the CS to
select the device. Once the device is selected and a serial
sequence is underway, HOLD may be forced low to suspend
further serial communication with the device without reset-
ting the serial sequences. Note that HOLD must be brought
low while the SCK pin is low. The device must remain se-
lected during this sequence. To resume serial communica-
tion HOLD is brought high while the SCK pin is low. Pins SI,
SCK and SO are at a high impedance state during HOLD .
See Figure 4.
TRANSMITTER/RECEIVER: The NM25C020 has separate
pins for data transmission (SO) and reception (SI).
MSB: The Most Significant Bit is the first bit transmitted and
received.
CHIP SELECT: The chip is selected when pin CS is low.
When the chip is not selected, data will not be accepted from
pin SI, and the output pin SO is in high impedance.
SERIAL OP-CODE: The first byte transmitted after the chip
is selected with CS going low contains the op-code that de-
fines the operation to be performed.
DS012400-5
FIGURE 3. SPI Protocol
DS012400-6
FIGURE 4. HOLD Timing
TABLE 1.
Instruction Instruction
Operation
Name
WREN
Format
00000110
00000100
00000101
00000001
00000011
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
WRDI
RDSR
WRSR
READ
DS012400-7
Read Data from Memory
Array
FIGURE 5. Invalid Op-Code
WRITE
00000010
Write Data to Memory Array
READ SEQUENCE (One or More Bytes): Reading the
memory via the SPI link requires the following sequence.
The CS line is pulled low to select the device. The READ
op-code is transmitted on the SI line followed by the byte ad-
dress (A7–A0) to be read. After this is done, data on the SI
line becomes don’t care. The data (D7–D0) at the address
specified is then shifted out on the SO line. If only one byte
INVALID OP-CODE: After an invalid code is received, no
data is shifted into the NM25C020, and the SO data output
pin remains high impedance until a new CS falling edge
re-initializes the serial communication. See Figure 5.
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=
Status register Bit 0 0 (RDY ) indicates that the device is
Functional Description (Continued)
=
READY; Bit 0
1 indicates that a program cycle is in
=
is to be read, the CS line can be pulled back to the high level.
It is possible to continue the READ sequence as the byte ad-
dress is automatically incremented and data will continue to
be shifted out. When the highest address is reached (FF),
the address counter rolls over to lowest address (000) allow-
ing the entire memory to be read in one continuous READ
cycle. See Figure 6.
progress. Bit 1 0 (WEN) indicates that the device is not
=
WRITE ENABLED. Bit 1
1 indicates that the device is
WRITE ENABLED. Non-volatile status register Bits 2 and 3
(BP0 and BP1) indicate the level of BLOCK WRITE PRO-
TECTION selected. The block write protection levels and
corresponding status register control bits are shown in Table
III. Note that if a RDSR instruction is executed during a pro-
gramming cycle only the RDY bit is valid. All other bits are
1s. See Figure 7.
READ STATUS REGISTER (RDSR): The Read Status Reg-
ister (RDSR) instruction provides access to the status regis-
ter which is used to interrogate the READY/BUSY and
WRITE ENABLE status of the chip. Two nonvolatile status
register bits are used to select one of four levels of BLOCK
WRITE PROTECTION. The status register format is shown
in Table 2.
TABLE 3. Block Write Protection Levels
Status Register Bits
Array
Addresses
Protected
None
Level
BP1
BP0
TABLE 2. Status Register Format
0
1
2
3
0
0
1
1
0
1
0
1
C0–FF
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
80–FF
00–FF
1
1
1
1
BP1 BP0 WEN RDY
DS012400-8
FIGURE 6. Read Sequence
DS012400-9
FIGURE 7. Read Status
WRITE ENABLE (WREN): When VCC is applied to the chip,
it “powers up” in the write disable state. Therefore, all pro-
gramming modes must be preceded by a WRITE ENABLE
(WREN) instruction. Additionally the WP pin must be held
high during a WRITE ENABLE instruction. At the completion
of a WRITE or WRSR cycle the device is automatically re-
turned to the write disable state. Note that a WRITE DIS-
ABLE (WRDI) instruction or forcing the WP pin low will also
return the device to the write disable state. See Figure 8.
DS012400-10
FIGURE 8. Write Enable
WRITE DISABLE (WRDI): To protect against accidental
data disturbance the WRITE DISABLE (WRDI) instruction
disables all programming modes. See Figure 9.
7
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written. Programming will start after the CS pin is forced
back to a high level. Note that the LOW to HIGH transition of
the CS pin must occur during the SCK low time immediately
after clocking in the D0 data bit. See Figure 10.
Functional Description (Continued)
The READY/BUSY status of the device can be determined
by executing a READ STATUS REGISTER (RDSR) instruc-
=
tion. Bit 0
1 indicates that the WRITE cycle is still in
=
progress and Bit 0 0 indicates that the WRITE cycle has
=
ended. During the WRITE programming cycle (Bit 0 1) only
the READ STATUS REGISTER instruction is enabled.
The NM25C020 is capable of a 4 byte PAGE WRITE opera-
tion. After receipt of each byte of data the two low order ad-
dress bits are internally incremented by one. The seven high
order bits of the address will remain constant. If the master
should transmit more than 4 bytes of data, the address
counter will “roll over”, and the previously loaded data will be
reloaded.
DS012400-11
FIGURE 9. Write Disable
WRITE SEQUENCE: To program the device the WRITE
PROTECT (WP ) pin must be held high and two separate in-
structions must be executed. The chip must first be write en-
abled via the WRITE ENABLE instruction and then a WRITE
instruction must be executed. Moreover, the address of the
memory location(s) to be programmed must be outside the
protected address field selected by the Block Write Protec-
tion Level. See Table 3.
At the completion of a WRITE cycle the device is automati-
cally returned to the write disable state.
If the WP pin is forced low or the device is not WRITE en-
abled, the device will ignore the WRITE instruction and re-
turn to the standby state when CS is forced high. A new CS
falling edge is required to re-initialize the serial communica-
tion. See Figure 11.
A WRITE command requires the following sequence. The
CS line is pulled low to select the device, then the WRITE
op-code is transmitted on the SI line followed by the byte ad-
dress (A7–A0) and the corresponding data (D7–D0) to be
DS012400-12
FIGURE 10. Write Sequence
DS012400-13
FIGURE 11. Start Write Condition
WRITE STATUS REGISTER (WRSR): The WRITE STATUS
REGISTER (WRSR) instruction is used to program the
non-volatile status register Bits 2 and 3 (BP0 and BP1). The
WRITE PROTECT (WP ) pin must be held high and two
separate instructions must be executed. The chip must first
be write enabled via the WRITE ENABLE instruction and
then a WRSR instruction must be executed.
Note that the first four bits are don’t care bits followed by BP1
and BP0 then two additional dont’care bits. Programming will
start after the CS pin is forced back to a high level. As in the
WRITE instruction the LOW to HIGH transition of the CS pin
must occur during the SCK low time immediately after clock-
ing the last don’t care bit. See Figure 13.
The READY/BUSY status of the device can be determined
by executing a READ STATUS REGISTER (RDSR) instruc-
The WRSR command requires the following sequence. The
CS line is pulled low to select the device and then the WRSR
op-code is transmitted on the SI line followed by the data to
be programmed. See Figure 12.
=
tion. Bit 0
1 indicates that the WRSR cycle is still in
=
progress and Bit 0 0 indicates that the WRSR cycle has
ended.
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Functional Description (Continued)
At the completion of a WRSR cycle the device is automati-
cally returned to the write disable state.
DS012400-14
FIGURE 12. Write Status Register
DS012400-15
FIGURE 13. Start WRSR Condition
Book
Extract
End
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Physical Dimensions inches (millimeters) unless otherwise noted
Molded Small Outline Package (M8)
Package Number M08A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Package Number N08E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Fairchild
Corporation
Fairchild
Europe
Fairchild
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
Americas
Customer Response Center
Tel: 1-888-522-5372
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 8 141-35-0
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
English Tel: +44 (0) 1 793-85-68-56
Italy
Tel: +39 (0) 2 57 5631
Tel: +852 2737-7200
Fax: +852 2314-0061
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
12
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