NM93CS66LZVN [FAIRCHILD]
EEPROM, 256X16, Serial, CMOS, PDIP8, PLASTIC, DIP-8;
| 型号： | NM93CS66LZVN |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | EEPROM, 256X16, Serial, CMOS, PDIP8, PLASTIC, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1997
NM93CS06LZ/CS46LZ/CS56LZ/CS66LZ
256-/1024-/2048-/4096-Bit Serial EEPROM with Extended
™
Voltage (2.7V to 5.5V) and Data Protect (MICROWIRE
Bus Interface)
and 5 which operate on the Protect Register. The memory in-
structions are READ, WRITE, WRITE ALL, WRITE EN-
ABLE, and WRITE DISABLE. The Protect register instruc-
tions are PRREAD, PRWRITE, PRCLEAR, PRDISABLE and
PRENABLE.
General Description
The NM93CS06LZ/CS46LZ/CS56LZ/CS66LZ devices are
256/1024/2048/4096 bits, respectively, of non-volatile elec-
trically erasable memory divided into 16/64/128/256 x 16-bit
registers (addresses). The NM93CSxxLZ Family functions in
an extended voltage operating range and is fabricated using
Fairchild Semiconductor’s floating gate CMOS technology
for high reliability, high endurance and low power consump-
tion. N registers (N≤16, N≤64, N≤128, N≤256) can be pro-
tected against data modification by programming the Protect
Register with the address of the first register to be protected
against data modification. (All registers greater than, or
equal to, the selected address are then protected from fur-
ther change.) Additionally, this address can be “locked” into
the device, making all future attempts to change data impos-
sible.
Features
n 2.7V to 5.5V operation in all modes
n Less than 1.0 µA standby current
n Sequential register read
n Write protection in a user-defined section of memory
n Typical active current of 200 µA
n Direct write: no erase before program
n Reliable CMOS floating gate technology
n MICROWIRE compatible serial I/O
n Self-timed programming cycle
These devices are available in both SO and TSSOP pack-
ages for small space considerations.
n Device status indication during programming mode
n 40 years data retention
n Endurance: 106 changes
The serial interface that control these EEPROMs is MI-
CROWIRE compatible, providing simple interfacing to stan-
dard microcontrollers and microprocessors. There are a total
of 10 instructions, 5 which operate on the EEPROM memory
n Packages available: 8-pin SO, 8-pin DIP, 8-Pin TSSOP
Block Diagram
DS011807-1
© 1997 Fairchild Semiconductor Corporation
DS011807
www.fairchildsemi.com
1
PrintDate=1997/08/29 PrintTime=12:23:19 10402 ds011807 Rev. No. 5 cmserv Proof
1
Connection Diagrams
Pin Names
CS
SK
DI
Chip Select
Dual-In-Line Package
8–Pin SO Package (M8) and
8–Pin TSSOP Package (MT8)
Serial Data Clock
Serial Data Input
Serial Data Output
DO
GND Ground
PE
PRE
VCC
Program Enable
Protect Register Enable
Power Supply
DS011807-2
Top View
Package Number N08E (N)
Package Number M08A (M8)
Package Number MTC08 (MT8)
Ordering Information
Commercial Temp. Range (0˚C to +70˚C)
Order Number
NM93CS06LZN/NM93CS46LZN/NM93CS56LZN/NM93CS66LZN
NM93CS06LZM8/NM93CS46LZM8/NM93CS56LZM8/NM93CS66LZM8
NM93CS46LZMT8/NM93CS56LZMT8/NM93CS66LZMT8
Extended Temp. Range (−40˚C to +85˚C)
Order Number
NM93CS06LZEN/NM93CS46LZEN/NM93CS56LZEN/NM93CS66LZEN
NM93CS06LZEM8/NM93CS46LZEM8/NM93CS56LZEM8/NM93CS66LZEM8
NM93CS46LZEMT8/NM93CS56LZEMT8/NM93CS66LZEMT8
Automotive Temp. Range (−40˚C to +125˚C)
Order Number
NM93CS06LZVN/NM93CS46LZVN/NM93CS56LZVN/NM93CS66LZVN
NM93CS06LZVM8/NM93CS46LZVM8/NM93CS56LZVM8/NM93CS66LZVM8
NM93CS06LZVMT8/NM93CS46LZVMT8/NM93CS56LZVMT8/NM93CS66LZEVT8
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PrintDate=1997/08/29 PrintTime=12:23:21 10402 ds011807 Rev. No. 5 cmserv Proof
2
Absolute Maximum Ratings (Note *NO
Operating Conditions
Ambient Operating Temperature
NM93CSxxLZ
TGT: FNXref NS0157*)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
−65˚C to +150˚C
0˚C to +70˚C
−40˚C to +85˚C
−40˚C to +125˚C
2.7V to 5.5V
VCC + 1V to −0.3V
NM93CSxxLZE
NM93CSxxLZV
Lead Temperature
(Soldering, 10 sec.)
Power Supply (VCC) Range
+300˚C
2000V
ESD rating
<
<
DC and AC Electrical Characteristics: 2.7V VCC 4.5V
Symbol
ICCA
ICCS
IIL
Parameter
Operating Current
Standby Current
Input Leakage
Part Number
Conditions
Min
Max
Units
mA
µA
=
=
CS VIH, SK 250 kHz
1
=
CS 0V
1
=
±
VIN 0V to VCC
200
nA
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
(Note 3)
VIL
−0.1
0.15 VCC
VCC + 1
0.1 VCC
V
V
VIH
0.8 VCC
=
IOL 10 µA
VOL
VOH
fSK
=
IOH −10 µA
0.9 VCC
0
(Note 4)
250
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
µs
µs
µs
tSKH
tSKL
tSKS
tCS
1
SK Low Time
1
SK Setup Time
Minimum CS
0.4
1
(Note 2)
tCSS
tPRES
tPES
tDIS
CS Setup Time
PRE Setup Time
PE Setup Time
DI Setup Time
0.2
0.2
0.2
0.4
70
tDH
DO Hold Time
tCSH
tPEH
tPREH
tDIH
tPD1
tPD0
tSV
CS Hold Time
0
PE Hold Time
0.4
0.4
0.4
PRE Hold Time
DI Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to DO in
2
2
1
=
tDF
CS VIL
0.4
TRI-STATE®
=
tWP
Write Cycle Time
VCC 2.7V
15
15
ms
ms
=
VCC 2.7V
<
<
DC and AC Electrical Characteristics: 4.5V VCC 5.5V
Symbol
ICCA
ICCS
IIL
Parameter
Operating Current
Standby Current
Input Leakage
Part Number
Conditions
Min
Max Units
=
=
CS VIH, SK 1.0 MHz
1
mA
µA
nA
=
CS 0V
1
=
±
VIN 0V to VCC
200
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIL
−0.1
0.8
V
V
V
V
VIH
2
VCC+1
0.4
=
IOL 2.1 mA
VOL1
VOH1
=
IOH −400 µA
2.4
3
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PrintDate=1997/08/29 PrintTime=12:23:24 10402 ds011807 Rev. No. 5 cmserv Proof
3
<
<
5.5V (Continued)
DC and AC Electrical Characteristics: 4.5V VCC
Symbol
VOL2
VOH2
fSK
Parameter
Part Number
Conditions
IOL 10 µA
Min
Max Units
=
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
0.2
V
V
=
IOL −10 µA
VCC − 0.2
(Note 4)
0
1
MHz
ns
tSKH
NM93CS06LZ-NM93CS66LZ
250
300
250
50
NM93CS06LZE/V-NM93CS66LZE/V
tSKL
tSKS
SK Low Time
ns
ns
SK Setup Time
SK Must Be at VIL for
tSKS before CS goes high
(Note 2)
tCS
Minimum CS
250
ns
Low Time
tCSS
tPRES
tDH
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
50
50
70
50
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPES
tDIS
tCSH
tPEH
tPREH
tDIH
250
50
20
tPD1
tPD0
tSV
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to DO in
500
500
500
100
=
tDF
CS VIL
TRI-STATE®
tWP
Write Cycle Time
10
ms
Capacitance
=
=
TA 25˚C f 1 MHz
Symbol
COUT
Test
Max
5
Units
pF
Output Capacitance
Input Capacitance
CIN
5
pF
Note 1: Stress ratings above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and operation
of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Note 2: CS (Chip Select) must be brought low (to V ) for an interval of t in order to reset all internal device registers (device reset) prior to beginning another op-
IL CS
code cycle (this is shown in the opcode diagrams in the following pages).
Note 3: Typical leakage values are in the 20 nA range.
=
Note 4: The shortest allowable SK clock period 1/f (as shown under the f parameter). Maximum SK clock speed (minimum SK period) is determined by the
SK SK
interaction of several AC parameters stated in the datasheet. Within this SK period, both t
and t limits must be observed. Therefore, it is not allowable to set
SKL
SKH
=
1/f
t
+ t
for shorter SK cycle time operation.
SKL (minimum)
SK
SKH (minimum)
AC Test Conditions
VCC Range
VIL/VIH
Input Levels
0.3V/1.8V
VIL/VIH
VOL/VOH
Timing Level
0.8V/1.5V
IOL/IOH
Timing Level
<
±
10 µA
2.7V ≤ VCC 4.5V
1.0V
(Extended Voltage Levels)
4.5V ≤ VCC ≤ 5.5V
(TTL Levels)
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
− 2.1 mA/0.4 mA
=
Output Load: 1 TTL Gate (CL 100 pF)
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PrintDate=1997/08/29 PrintTime=12:23:28 10402 ds011807 Rev. No. 5 cmserv Proof
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Functional Description
The extended voltage EEPROMs of the NM93CSxxLZ Fam-
ily have 10 instructions as described below. Note that MSB
of any instruction is a “1” and is viewed as a start bit in the in-
terface sequence. For the CS06 and CS46 the next 8 bits
carry the op code and the 6-bit address for register selection.
For the CS56 and CS66, the next 10 bits carry the op code
and the 8-bit address for register selection. All Data In sig-
nals are clocked into the device on the low-to-high SK tran-
sition.
Write Disable (WDS):
To protect against accidental data disturb, the WDS instruc-
tion disables all programming modes and should follow all
programming operations. Execution of a READ instruction is
independent of both the WEN and WDS instructions.
Note: For all protect register operations: If the PRE pin is not
held at VIH, all instructions will be applied to the EEPROM ar-
ray, rather than the Protect Register.
Protect Register Read (PRREAD):
Read and Sequential Register Read (READ):
The PRREAD instruction outputs the address stored in the
Protect Register on the DO pin. The PRE pin MUST be held
high while loading the instruction sequence. Following the
PRREAD instruction the 6- or 8-bit address stored in the
memory protect register is transferred to the serial out shift
register. As in the READ mode, a dummy bit (logical 0) pre-
cedes the 6- or 8-bit address string.
The READ instruction outputs serial data on the D0 pin. After
a READ instruction is received, the instruction and address
are decoded, followed by data transfer from the selected
memory register into
a 16-bit serial-out shift register. A
dummy bit (logical 0) precedes the 16-bit data output string.
Output data changes are initiated by a low to high transition
of the SK clock. In the Sequential Read mode of operation,
the memory automatically cycles to the next register after
each 16 data bits are clocked out. The dummy-bit is sup-
pressed in this mode and a continuous string of data is ob-
tained.
Protect Register Enable (PREN):
The PREN instruction is used to enable the PRCLEAR,
PRWRITE, and PRDS modes. Before the PREN mode can
be entered, the part must be in the Write Enable (WEN)
mode. Both the PRE and PE pins MUST be held high while
loading the instruction sequence.
Write Enable (WEN):
When VCC is applied to the part, it “powers up” in the Write
Disable (WDS) state. Therefore, all programming modes
must be preceded by a Write Enable (WEN) instruction.
Once a Write Enable instruction is executed, programming
remains enabled until a Write Disable (WDS) instruction is
executed or VCC is removed from the part.
Note that a PREN instruction must immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
Protect Register Clear (PRCLEAR):
The PRCLEAR instruction clears the address stored in the
Protect Register and therefore enables all registers for the
WRITE and WRALL instruction. The PRE and PE pins must
be held high while loading the instruction sequence; how-
ever, after loading the PRCLEAR instruction, the PRE and
PE pins become “don’t care”. Note that a PREN instruction
must immediately precede a PRCLEAR instruction.
Write (WRITE):
The WRITE instruction is followed by 16 bits of data to be
written into the specified address. After the last bit of data is
allocated to the data-in (DI) pin, CS must be brought low be-
fore the next rising edge of the SK clock. This falling edge of
the CS initiates the self-timed programming cycle. The PE
pin MUST be held high while loading the WRITE instruction;
however, after loading the WRITE instruction, the PE pin be-
comes a “don’t care”. The D0 pin indicates the READY/
BUSY status of the chip if CS is brought high after the tCS in-
Please note that the PRCLEAR instruction and the
PRWRITE instruction will both program the Protect Register
with all 1s. However, the PRCLEAR instruction will allow the
LAST register to be programmed, whereas the PRWRITE in-
=
struction all 1s will PREVENT the last register from being
=
programmed. In addition, the PRCLEAR instruction will allow
terval. D0 logical 0 indicates that programming is still in
=
=
the use of the WRALL command, where the PRWRITE all
progress. D0 logical 1 indicates that the register at the ad-
1s will lock out the Bulk programming opcode.
dress specified in the instruction has been written with the
data pattern specified in the instruction and that the part is
ready for another instruction.
Protect Register Write (PRWRITE):
The PRWRITE instruction is used to write into the Protect
Register the address of the first register to be protected. Af-
ter the PRWRITE instruction is executed, all memory regis-
ters whose addresses are greater than or equal to the ad-
dress specified in the Protect Register are protected from the
WRITE operation. Note that before executing a PRWRITE
instruction, the Protect Register must first be cleared by ex-
ecuting a PRCLEAR operation and the PRE and PE pins
must be held high while loading the instruction; however, af-
ter loading the PRWRITE instruction, the PRE and PE pins
become “don’t care”. Note that a PREN instruction must im-
mediately precede a PRWRITE instruction.
Write All (WRALL):
The WRALL instruction is valid only when the Protect Regis-
ter has been cleared by executing a PRCLEAR instruction.
The WRALL instruction will simultaneously program all regis-
ters with the data pattern specified in the instruction. Like the
WRITE instruction, the PE pin MUST be held high while
loading the WRALL instruction; however, after loading the
WRITE instruction, the PE pin becomes a “don’t care”. As in
the WRITE mode, the DO pin indicates the READY/BUSY
status of the chip if CS is brought high after the tCS interval.
This function is DISABLED if the protect register is in use to
lock out a section memory.
Protect Register Disable (PRDS):
The PRDS instruction is a ONE TIME ONLY instruction
which renders the Protect Register unalterable in the future.
Therefore, the specified registers become PERMANENTLY
protected against data changes. As in the PRWRITE instruc-
5
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PrintDate=1997/08/29 PrintTime=12:23:29 10402 ds011807 Rev. No. 5 cmserv Proof
5
Note that a PREN instruction must immediately precede a
PRDS instruction.
Functional Description (Continued)
tion the PRE and PE pins must be held high while loading
the instruction, and after loading the PRDS instruction the
PRE and PE pins become “don’t care”.
Instruction Set for the NM93CS06LZ and NM93CS46LZ
Instruction SB
Op
Code
10
Address
Data
PRE PE
Comments
READ
WEN
1
1
1
1
1
1
1
A5–A0
11XXXX
A5–A0
0
0
0
0
0
1
1
X
1
1
1
X
X
1
Reads data stored in memory, starting at specified address.
Enable all programming modes.
00
WRITE
WRALL
WDS
01
D15–D0
Writes address if unprotected.
00
01XXXX D15–D0
00XXXX
Writes all registers. Valid only when Protect Register is cleared.
Disables all programming modes.
00
PRREAD
PREN
10
XXXXXX
Reads address stored in Protect Register.
00
11XXXX
Must immediately precede PRCLEAR, PRWRITE, and PRDS
instructions.
PRCLEAR
PRWRITE
1
1
11
01
111111
A5–A0
1
1
1
1
Clears the Protect Register so that no registers are protected
from WRITE.
Programs address into Protect Register. Thereafter, memory
addresses ≥ the address in Protect Register are protected from
WRITE.
PRDS
1
00
000000
1
1
ONE TIME ONLY instruction after which the address in the
Protect Register cannot be altered.
Note: Address bits A5 and A4 become “Don’t Care” for the NM93CS06LZ.
Instruction Set for the NM93CS56LZ and NM93CS66LZ
Instruction SB
Op
Code
10
Address
Data
PRE PE
Comments
READ
WEN
1
1
1
1
1
1
1
A7–A0
11XXXXXX
A7–A0
0
0
0
0
0
1
1
X
1
1
1
X
X
1
Reads data stored in memory, starting at specified address.
Enable all programming modes.
00
WRITE
WRALL
WDS
01
D15–D0
Writes address if unprotected.
00
01XXXXXX D15–D0
00XXXXXX
Writes all registers. Valid only when Protect Register is cleared.
Disables all programming modes.
00
PRREAD
PREN
10
XXXXXXXX
Reads address stored in Protect Register.
00
11XXXXXX
Must immediately precede PRCLEAR, PRWRITE, and PRDS
instructions.
PRCLEAR
PRWRITE
1
1
11
01
11111111
A7–A0
1
1
1
1
Clears the “protect register” so that no registers are protected
from WRITE.
Programs address into Protect Register. Thereafter, memory
addresses ≥ the address in Protect Register are protected from
WRITE.
PRDS
1
00
00000000
1
1
ONE TIME ONLY instruction after which the address in the
Protect Register cannot be altered.
Note: Address bit A7 becomes “Don’t Care” for the NM93CS56LZ.
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PrintDate=1997/08/29 PrintTime=12:23:31 10402 ds011807 Rev. No. 5 cmserv Proof
6
Timing Diagrams
Synchronous Data Timing
DS011807-4
READ:
=
=
X
PRE 0, PE
DS011807-5
†
Sequential read is possible when CS is held high. The device will automatically cycle to the next register and output sequentially.
7
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PrintDate=1997/08/29 PrintTime=12:23:32 10402 ds011807 Rev. No. 5 cmserv Proof
7
Timing Diagrams (Continued)
WEN:
=
=
PRE 0, D0 TRI-STATE
DS011807-6
WDS:
=
=
=
PRE 0, PE X, DO TRI-STATE
DS011807-7
WRITE:
=
PRE
0
DS011807-8
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PrintDate=1997/08/29 PrintTime=12:23:33 10402 ds011807 Rev. No. 5 cmserv Proof
8
Timing Diagrams (Continued)
WRALL:
=
PRE
0
(PROTECT REGISTER MUST BE CLEARED)
DS011807-9
*Don’t care
PRREAD:
=
PE
X
DS011807-10
9
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PrintDate=1997/08/29 PrintTime=12:23:33 10402 ds011807 Rev. No. 5 cmserv Proof
9
Timing Diagrams (Continued)
PREN:
D0 TRI-STATE
=
(A WEN CYCLE MUST PRECEDE A PREN CYCLE)
DS011807-11
PRCLEAR:
(A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRCLEAR CYCLE)
DS011807-12
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PrintDate=1997/08/29 PrintTime=12:23:34 10402 ds011807 Rev. No. 5 cmserv Proof
10
Timing Diagrams (Continued)
†
PRWRITE :
(A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRWRITE CYCLE.)
DS011807-13
PRDS:
(ONE TIME ONLY INSTRUCTION. A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRDS CYCLE.)
DS011807-14
Book
Extract
End
11
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PrintDate=1997/08/29 PrintTime=12:23:34 10402 ds011807 Rev. No. 5 cmserv Proof
11
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Small Out-Line Package (M8)
Package Number M08A
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12
PrintDate=1997/08/29 PrintTime=12:23:35 10402 ds011807 Rev. No. 5 cmserv Proof
12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Pin Molded TSSOP, JEDEC (MT8)
Package Number MTC08
13
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PrintDate=1997/08/29 PrintTime=12:23:35 10402 ds011807 Rev. No. 5 cmserv Proof
13
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Package Number N08E
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor
Corporation
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
Americas
Customer Response Center
Tel: 1-888-522-5372
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 8 141-35-0
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: 81-3-5620-6175
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English Tel: +44 (0) 1 793-85-68-56
Italy
Tel: +39 (0) 2 57 5631
Tel: +852 2737-7200
Fax: +852 2314-0061
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
14
PrintDate=1997/08/29 PrintTime=12:23:35 10402 ds011807 Rev. No. 5 cmserv Proof
14
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