OCX96PB304 [FAIRCHILD]
Crossbar Switch, CMOS, PBGA304, 1.27 MM PITCH, PLASTIC, BGA-304;
| 型号： | OCX96PB304 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Crossbar Switch, CMOS, PBGA304, 1.27 MM PITCH, PLASTIC, BGA-304 |
| 文件： | 总31页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OCX961 Crosspoint Switch
Advanced Mini Data Sheet
Features
• 1.6 Gb/s port data bandwidth, >77Gb/s aggregate bandwidth • Full Broadcast and multicast capability
– One-to-One and One-to-Many connections
– Special broadcast mode routes one input to
all outputs at maximum data rate
• Low power CMOS, 2.5V and 3.3V power supply
• SRAM-based, in-system programmable
• 96 configurable I/O ports
• Low jitter and signal skew
• Low duty cycle distortion
– 48 dedicated differential input ports
– 48 dedicated differential output ports
– Supports LVPECL and LVDS I/O
– LVTTL control interface
• RapidConfigure™ parallel interface for
configuration and readback
– Output Enable control for all outputs
• Serial programming interface for
• Non-blocking switch matrix
configuration
– Patented ActiveArray™ matrix for superior performance
– Double-buffered configuration RAM cells for simultaneous
global updates
• 304 BGA package with 1.27mm ball spacing
• Intergrated Termination Resistors
– ImpliedDisconnect™ function for single cycle disconnect/
connect
Description
The OCX961 SRAM-based device is a non-blocking 48 X 48 digital crosspoint switch capable of data rates of
1.6 Gigabits per second per port. The I/O ports are fixed as either input or output ports. The input and output
ports operate in flow-through (asynchronous) mode.
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a
traditional n:1 multiplexer architecture. The OCX™ devices support various operating modes covering one input
to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input
to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained
on all unchanged data paths.
The RapidConfigure parallel interface allows fast configuration of the Output Buffers and the switch matrix.
Readback is supported for device test and verification purposes. The OCX961 also includes a JTAG-like serial
interface for configuration of the device. A functional block diagram of the OCX961 is shown in Figure 1.
Applications
• SONET/SDH and DWDM
• Digital Cross-Connects
• System Backplanes and Interconnects
• High Speed Test Equipment
• ATM Switch Cores
• Video Switching
96
96
OUT[47:0]
IN[47:0]
48 x 48
Crosspoint
Switch Matrix
Input
Buffers
Output
Buffers
OE#
7
RCA[6:0]
RCB[6:0]
RCI[3:0]
SCLK
SMS
SDI
7
4
Serial
RapidConfigure
Signals
Programming
Interface
Configuration and
Programming Logic
RCO[2:0] 3
RC_CLK#
RC_EN#
SRST#
SDO
HW_RST#
UPDATE#
Figure 1 OCX961 Functional Block Diagram
I-Cube, Inc.
[Rev. 1.0] 4/25/01
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Contents
1.
Introduction ........................................................................................................................... 7
1.1 Input and Output Buffers...................................................................................................... 8
1.1.1 Input and Output Port Function Mode ........................................................................... 8
1.1.2 Broadcast Mode ............................................................................................................. 8
1.2 Output Control Signals......................................................................................................... 9
1.3 RapidConfigure Interface..................................................................................................... 9
1.3.1 RapidConfigure Programming Instructions.................................................................... 9
1.4 Serial Interface Configuration Controller........................................................................... 12
1.4.1 Serial Interface............................................................................................................. 12
1.4.2 Output Port Configuration ........................................................................................... 12
1.4.3 Switch Matrix Configuration ....................................................................................... 12
1.4.4 Mode Control Register Configuration.......................................................................... 12
1.4.5 Serial Interface Architecture ........................................................................................ 13
1.4.6 Serial Interface State Machine ..................................................................................... 14
1.4.7 Serial Input Format ...................................................................................................... 14
1.4.8 Serial Interface Instructions ......................................................................................... 15
1.5 ImpliedDisconnect ............................................................................................................. 17
1.6 Device Reset Options......................................................................................................... 18
Pin Description .....................................................................................................................19
Differential I/O Standards ...................................................................................................20
3.1 LVPECL............................................................................................................................. 20
3.2 LVDS ................................................................................................................................. 20
Electrical Specifications .......................................................................................................21
4.1 Absolute Maximum Ratings .............................................................................................. 21
4.2 Recommended Operating Conditions ................................................................................ 21
4.3 Pin Capacitance ................................................................................................................. 21
4.4 DC Electrical Specifications .............................................................................................. 22
4.5 LVPECL AC Electrical Specifications............................................................................... 23
4.6 Timing Diagrams................................................................................................................ 24
2.
3.
4.
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
5.
Power Consumption ............................................................................................................ 27
5.1 Power for LVPECL I/O ..................................................................................................... 27
Component Availability and Ordering Information ......................................................... 28
Glossary................................................................................................................................ 28
Product Status Definition .................................................................................................... 30
6.
7.
8.
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
OCX961 Functional Block Diagram .................................................................................................... 1
OCX961 Switch Matrix........................................................................................................................ 7
Input and Output Buffer Configuration ................................................................................................ 8
OCX961 Serial Interface Architecture ............................................................................................... 13
OCX961 Serial Interface State Machine ............................................................................................ 14
OCX961 Operating in LVPECL Mode .............................................................................................. 20
Flow-Through Mode Timing.............................................................................................................. 24
Output Enable Timing ........................................................................................................................ 24
Duty Cycle Distortion......................................................................................................................... 24
RapidConfigure Write Cycle .............................................................................................................. 25
RapidConfigure Read Cycle ............................................................................................................... 25
Serial Timing ...................................................................................................................................... 26
Typical Performance........................................................................................................................... 26
Power Consumption Diagram for the OCX961 using LVPECL........................................................ 27
I-Cube, Inc.
[Rev. 1.0] 4/25/01
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Summary for Programmable I/O Attributes for OCX961................................................................. 8
RapidConfigure Programming Instructions ...................................................................................... 9
RCO[2:0] Readback Pin Assignment..............................................................................................11
Programming an Output Buffer using RapidConfigure ..................................................................11
Mode Control Register ....................................................................................................................12
Serial Input Format..........................................................................................................................14
Serial Interface Instructions.............................................................................................................15
Programming an Output using the Serial Interface.........................................................................16
Number of Cycles and Configuration Time....................................................................................17
Device Reset Options ......................................................................................................................18
OCX961 Pin Description.................................................................................................................19
Absolute Maximum Ratings............................................................................................................21
Recommended Operating Conditions..............................................................................................21
Pin Capacitance ...............................................................................................................................21
LVTTL DC Electrical Specifications..............................................................................................22
LVPECL DC Electrical Specifications ...........................................................................................22
LVPECL AC Electrical Specifications ...........................................................................................23
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1. Introduction
The OCX961 is a differential crosspoint-switching device. The main functional block of the device is a Switch
Matrix as shown in Figure 1. The Switch Matrix is a x-y structure supporting an input-to-output data flow.
Figure 2 shows a conceptual view of the switch matrix with inputs connected to the horizontal trace and outputs
to the vertical trace. Connections between vertical and horizontal lines are implemented with a proprietary high-
performance buffering circuit. Signal path delays through the Switch Matrix are very well balanced, resulting in
predictable and uniform pin-to-pin delays.
Note – For the purpose of clarity, the logic diagrams within this data sheet are conceptual
representations only and do not show actual circuit implementation.
Loading
SRAM
Cell
Active
SRAM
Cell
Data
UPDATE#
Proprietary High-performance
Buffering Circuit
Figure 2 OCX961 Switch Matrix
The Active SRAM cells are responsible for establishing connections in the switch matrix by turning on the
interconnect circuit, while the Loading SRAM cell can be used to store a second configuration that can be
transferred to the Active SRAM cell at a later time. The two SRAM cells are arranged so that a double buffered
scheme can be employed. Through the use of an internal signal (generated automatically during a programming
cycle) it is possible to store a second configuration map in the Loading SRAM while the Active SRAM
maintains its present connection status. When the UPDATE# signal is asserted low, the contents of the Loading
SRAM cell are transferred to the Active SRAM cell and the switch matrix connection is either made or broken.
The UPDATE# signal can be used to control when the switch matrix is reconfigured. For instance, as long as the
UPDATE# signal is asserted high, the Loading SRAM cells for the entire switch matrix could be changed
without affecting the current configuration of the switch. When the UPDATE# signal is asserted low, the entire
switch matrix would be reconfigured simultaneously. If the UPDATE# signal is asserted continuously, all
crosspoint programming commands (generated by RapidConfigure or Serial programming cycles) will take
effect immediately, since the Loading SRAM cell’s contents will be transferred directly to the Active SRAM
cell.
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[Rev. 1.0] 4/25/01
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.1 Input and Output Buffers
All of the I/O buffers are differential with flow-through mode. Figure 3 shows the basic block diagram of
the input and output blocks with the sources for the output control signals (OE#). The control signals are
explained in more details in the following sections.
Input
Output
Switch
Matrix
OE#
Figure 3 Input and Output Buffer Configuration
1.1.1 Input and Output Port Function Mode
The following legend describes the various modes of the Input and Output Ports and the
specification used by the OCXPro™ Software.
Legend:
Ax–Switch Matrix Signal
Px–Port Signal
OE#–Output Enable (# means “Active Low”)
Table 1
Summary for Programmable I/O Attributes for OCX961
I/O Port Function
Symbol
Mnemonic
IN
Input – The external signal is buffered from the Input Port pin
Px
Ax
to the corresponding Switch Matrix line.
Output – The internal signal is buffered from the
OP
NC
Px
Ax
Ax
corresponding Switch Matrix line to the Output Port pin. In
this mode an optional output enable (OE#) can be selected.
The default state is logic high with enable set to ON.
OE#
No Connect – In this mode, the output Port pin is isolated
from the Switch Matrix.
Px
1.1.2 Broadcast Mode
The OCX961 has a special Broadcast Mode which connects any input to all outputs without
performance degradation. The input is selected using RapidConfigure or Serial interface and
disconnects all other inputs. The Global Update pin (UPDATE#) must be held high during
Broadcast Mode. Asserting the UPDATE# pin returns the array to the previous program condition.
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.2 Output Control Signals
Every output port of the OCX961 has a global Output Enable signal (OE#). All output buffers
have output enables that have programmable polarity and are individually configurable.
Additionally each output can be permanently enabled (always ON) or disabled (always OFF)
which is useful for applications which need to tri-state outputs (for example when using multiple
chips in expansion mode) or for power saving in designs that do not need to use all the outputs
available.
Two control bits are used to control the function of the output enable.
1.3 RapidConfigure Interface
RapidConfigure (RC) is a 23 signal parallel interface that is used to program the OCX961 device. The 23
pins are allocated as follows:
RCA[6:0] = RapidConfigure Address A. RCA are input pins.
RCB[6:0] = RapidConfigure Address B. RCB are input pins.
RCI[3:0] = RapidConfigure Instruction Bits
RCO[2:0] = RapidConfigure Readback. RCO are output pins.
RC_CLK#= RapidConfigure Clock (negative edge clock)
RC_EN# = RapidConfigure Cycle Enable (active low)
1.3.1 RapidConfigure Programming Instructions
The RC interface supports both write and read types of operations:
1. Write Operations (reset crosspoint and Input or Output Buffer (IOB), configure an
Output Buffer, connect/disconnect crosspoint)
2. Read Operations (Output Buffer and crosspoint configuration read).
Table 2
RapidConfigure Programming Instructions
RCI[3:0] RCA[6:0]
RCB[6:0]
RCO[2:0]
Instruction
Reserved
Reserved
Description
0000
0001
0010
X
X
X
Reset Crosspoint
Array
Reset, along with an Update operation
(UPDATE# pin or Update command)
resets the entire crosspoint array to no
connect. All Output Buffers remain
unchanged by this operation.
0011
Input Port
Address
Set Array to Broadcast Connects the input selected by RCB[6:0]
mode
to all output ports and disconnects all
other inputs. The Global Update
(UPDATE#) pin must be held high
during Broadcast mode. Activating the
Global Update pin returns the array to
the previous program condition.
0100
Output Port
Address
Data
Configure an Output Program an Output Buffer specified by
Buffer
RCA[6:0].
See Table 4 for RCB[6:0] bit assignment
and buffer functionality.
I-Cube, Inc.
[Rev. 1.0] 4/25/01
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Table 2
RapidConfigure Programming Instructions (Continued)
RCI[3:0] RCA[6:0]
RCB[6:0]
RCO[2:0]
Instruction
Description
0101
Readback Crosspoint, This is a two-cycle instruction.
Output Buffer status
Cycle 1 Output Port
Address
Input Port
Address
X
Specify the crosspoint connect status at
input location specified by RCA[6:0] to
the output location specified by
RCB[6:0].
Cycle 2
X
X
Output Data
Readback (using RCO[2:0]) the status of
the input buffer specified in Cycle 1 by
RCA[6:0], the output buffer specified in
Cycle 1 by RCO[2:0] and the crosspoint
connect status.
See Table 3 for RCO[2:0] readback pin
assignment.
0110
0111
X
X
X
Update
Program the Global Update function
without the use of the UPDATE# pin.
Input Port
Address
Disconnect Input
Disconnect the crosspoint cells of the
input row location specified by
RCA[6:0].
1000
Output Port
Address
Input Port
Address
Disconnect Input and Disconnect the crosspoint cell at the
Output
input location specified by RCA[6:0] to
the output location specified by
RCB[6:0].
All other connections from the source
input address or to the same output
address remain the same as before.
1001
1010
Output Port
Address
Input Port
Address
Connect, with
ImpliedDisconnect
Connect the crosspoint cell at the input
location specified by RCA[6:0] to the
output location specified by RCB[6:0].
All other connections from the same
input address or to the same output
address are set to no connect (NC).
Output Port
Address
Input Port
Address
Connect, without
ImpliedDisconnect
Connect the crosspoint cell at the input
location specified by RCA[6:0] to the
output location specified by RCB[6:0].
All other connections to the same output
address are set to “no connect” while all
other connections from the same input
address remain the same as before.
1011
1100
1101
Reserved
Reserved
Reset All
X
X
Reset the switch matrix to no connects
(NC). Update is forced internally. Sets
the Output buffer to Flow-through mode
with Output Enabled.
1110
1111
Reserved
Reserved
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I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Note – X = Don’t care.
Table 3
RCO[2:0] Readback Pin Assignment
RCO[2:0]
Readback Location
Signal/Function
Connection Status:
O2
Crosspoint
0 = No connection (NC) — (default state at reset)
1 = Connected
O1, O0
0,0
0,1
Output Buffer
Output Enable:
Output enabled (ON) – this is the default state at reset
Output disabled (OFF)
1,0
1,1
Output controlled by OE (active high)
Output controlled by OE# (active low)
Table 4
Programming an Output Buffer using RapidConfigure
RCB[6:0]
Signal/Function
B6, B5, B4, B3, B2 Don’t care
B1, B0
0,0
0,1
Output Enable:
Output enabled (ON) – this is the default state at reset
Output disabled (OFF)
1,0
1,1
Output controlled by OE (active high)
Output controlled by OE# (active low)
I-Cube, Inc.
[Rev. 1.0] 4/25/01
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.4 Serial Interface Configuration Controller
The Output port attributes and the Switch Matrix connections can be programmed using the serial bus. The
RapidConfigure Interface can be enabled or disabled using the serial bus.
The serial interface mode is always available for configuration regardless of whether the RapidConfigure
mode is enabled or disabled. However, proper care must be taken when switching between Serial Interface
and RapidConfigure for configuring the devices. Before attempting to change Switch Matrix connections
or output port configuration through the Serial Interface, the user must first ensure that the RapidConfigure
mode is disabled by using the Serial Interface serial mode to set the RCE bit to zero in the Mode Control
Register.
1.4.1 Serial Interface
The dedicated Serial interface has five pins: Serial Data Out (SDO), Serial Mode Select (SMS),
Serial Data In (SDI), Serial Reset (SRST#), and Serial Clock (SCLK), for device configuration
and verification. The I-Cube supplied software will automatically generate the necessary bitstream
from a higher-level textual description of the required configuration. Data on the SDI and SMS
pins are clocked into the device on the rising edge of the SCLK signal, while the valid data
appears on the SDO pin after the falling edge of SCLK. For more detailed information on Serial
programming, refer to the OCX Family Register Programming Manual.
1.4.2 Output Port Configuration
Output port configuration is accomplished by loading the appropriate bitstream into the
programming registers present at each Output port. The serial bus is used to load configuration
data into the Output port programming registers, one Output port at a time.
1.4.3 Switch Matrix Configuration
The contents of the SRAM cells controlling Switch Matrix connection can be modified using the
Serial interface. This is accomplished by loading the configuration data, one word at a time, into
the SRAM cells in the Switch Matrix.
1.4.4 Mode Control Register Configuration
The OCX961 contains a single bit Mode Control Register used to store user flags for
RapidConfigure Enable (RCE). These are required for proper functioning of the device. The
contents of this register can be changed using the Serial interface and a special Serial instruction.
Table 5
Mode Control Register
RCE
Mode
0
1
RapidConfigure interface disabled (OFF)
RapidConfigure interface enabled (ON)
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.4.5 Serial Interface Architecture
Programming Registers
(189 x 2 = 378 Bits)
Data Register - 1 Bit
Device Identification Register - 32 Bits
Mode Control Register - 1 Bits
MUX BUF SDO
SDI
Address Register - 7 Bits
Bypass Register - 1 Bit
Instruction Register - 16 Bits
Serial Interface
Controller
SMS
SCLK
SRST#
Figure 4 OCX961 Serial Interface Architecture
I-Cube, Inc.
[Rev. 1.0] 4/25/01
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.4.6 Serial Interface State Machine
Test Logic
Reset
1
0
1
1
1
Run Test/
Idle
Select DR
Scan
Select IR
Scan
0
0
0
1
1
Capture
DR
Capture
IR
0
0
Shift DR
1
Shift IR
1
0
0
Exit 1 DR
0
Exit 1 IR
0
1
1
Pause DR
1
Pause IR
1
0
0
0
0
Exit 2 DR
1
Exit 2 IR
1
Update DR
Update IR
1
0
1
0
Figure 5 OCX961 Serial Interface State Machine
1.4.7 Serial Input Format
Table 6
Instruction
Serial Input Format
Data
Address A
Bit Number
Bit Name
15
I3
14
I2
13 12 11 10
9
8
7
6
5
4
3
2
1
0
I1 I0 BB BA B9 B8 B7 A6 A5 A4 A3 A2 A1 A0
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.4.8 Serial Interface Instructions
Table 7
B7
Serial Interface Instructions
I [3:0]
BB
X
BA
X
B9
X
B8
X
A6-A0
Instruction
Sample/EXTEST
Sample/EXTEST
Description
Places the device in scan mode.
Places the device in scan mode.
0
0
0
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset the Crosspoint Reset, along with an Update operation (UPDATE# pin
Array
or Update command) resets the entire Crosspoint Array
to no-connect (B7 and B8 are not changed).
0
0
1
1
X
X
X
X
X
X
Set Array for
Broadcast mode
Use the Address Register as the Input address to be the
broadcast input. Connects the selected Input to all
Output cells and disconnects all other Inputs.
Activating the Global Update instruction returns the
Crosspoint array from the Broadcast mode to the
previous programed state.
0
0
1
1
0
0
0
1
X
X
X
X
X
X
OE
X
OE
X
Output Buffer Program a Buffer
Address
Programs the Output Buffer address specified in the
Serial instruction (A6-A0). The configuration data is
also specified in the Serial instruction bits BA-B7. See
Table 8 for bit assignment of the Buffer functionality.
Output Address/ Configuration
Readback the connectivity of the Crosspoint cell with
the Input location specified in the Address Register
and the Output location specified Serial instruction
(A0-A6). It also returns the configuration of the Output
Buffer addressed in the Serial instruction (A0-A6).
The readback data is shifted out of SDO in the
following sequence:
Buffer
readback
1. Crosspoint Connect (1=connected, 0=no
connection)
2. Output Enable—B7 (see Table 8)
3. Output Enable—B8 (see Table 8)
4. Reserved (Don’t Care)
5. Reserved (Don’t Care)
6. State of Broadcast bit
7. State of the RCE bit
NOTE: This instruction does not increment the
Address Register. This instruction also requires two
DR cycles
0
0
1
1
1
0
1
1
0
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Update the
Crosspoint Array
Update the programmed connection from the Loading
SRAM to the Active SRAM.
Disconnect Input
cell
Disconnect the Crosspoint connections from the Input
address specified in the Address Register.
Output Address Disconnect Input
and Output
Disconnect the Crosspoint cell at the Input location
specified at the Address Register and the Output
location specified in the Disconnect instruction (A6-
A0).
All other connections from the same input address or
to the same output address remain the same.
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Table 7
Serial Interface Instructions (Continued)
A6-A0 Instruction
Output Address Connect with
I [3:0]
BB
BA
B9
B8
B7
Description
1
0
0
1
X
X
X
X
X
Connects the Crosspoint cell at the Input location
ImpliedDisconnect specified on the Address Register and the output
location specified in the Connect Serial instruction
(A6-A0).
All other connections from the same Input address or
the same Output address are set to no-connects.
NOTE: This instruction increments the Address
Register (Input address).
1
1
0
0
1
1
0
1
X
X
X
X
X
X
X
X
X
X
Output Address Connect—no
Connects the Crosspoint cell at the Input address
ImpliedDisconnect specified in the Address Register and the Output
address specified in the Connect instruction (A6-A0).
All connections to the same output address are set to
“no connect” while all other connections from the
same input remain the same as before.
Input Address Set the Address
Sets the 7-bit Address Register with the 7-bit address
(A6-A0) of the Instruction Register. The 7-bit address
of the Address Register becomes the Input port address
for Crosspoint Access.
Register
1
1
1
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
Device ID out
Serialize the device ID and revision history out to
SDO. ID for the OCX961 is 0x0000D89F
Reset Output Buffer Resets the Crosspoint Array to no-connects. Sets the
and Crosspoint
Array
Output buffer to Flow-through mode with Output
Enabled. The device ID is serialized to SDO.
1
1
1
1
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
Set RCE Bit
Sets the RCE bit of the Mode Control Register with the
Serial instruction bit A0.
To turn ON the RCE bit, encode bit A0 to 1.
To turn OFF the RCE bit, encode bit A0 to 0.
Bypass
Places device in a mode to pass SDI data to SDO with
one clock delay. Used for programming and testing
devices through serial connected controls.
Table 8
Programming an Output using the Serial Interface
Signal/Function
BA, B9, B8, B7
B8, B7
0,0
0,1
Output Enable:
Output enabled (ON) – this is the default state at reset
Output disabled (OFF)
1,0
1,1
Output controlled by OE (active high)
Output controlled by OE# (active low)
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OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Table 9
Number of Cycles and Configuration Time
Operation
OCX961
Serial
Cycles
Reset Sequence (SMS = “11111”)
7
28
Enable or Disable RapidConfigure
Change attributes of ONE Output Port
28
Change attributes of ALL Output Ports
2,240
35
Reset Controller + Reset ALL Output Ports + Clear ALL SRAM cells
Connect or disconnect two Ports
56
Configure Entire Switch Matrix (All Switch Matrix Connections)
Completely Configure the Device (All Output Ports and All Switch Matrix Connections)
181,440
183,680
1.5 ImpliedDisconnect
ImpliedDisconnect is a feature that provides the ability to make fast switch connection changes.
When using the normal “Connect” command, all other connection to the specified output are set
to “no connect”. However, the specified input remains connected to any other outputs to which it
was connected before.
The “Connect with ImpliedDisconnect” commands allow the user to disconnect the specified
input from all other outputs as well. This enables the user to make a complete connection change
in one RapidConfigure cycle.
I-Cube, Inc.
[Rev. 1.0] 4/25/01
17
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
1.6 Device Reset Options
The power-on reset, RapidConfigure reset, hardware reset, and Serial reset functions will program the
output buffers to flow-through mode (with Global Clock selected), and Output Enabled (ON). The Serial
interface can be reset via the SRST# pin or by clocking five consecutive one to the SMS pin. The
hardware reset pin can be done accomplished through the HW_RST# pin (active low). RC reset can be
accomplished by applying the RC instruction 1101 to the RCI[3:0] pins.
Table 10 Device Reset Options
Programming
Interface
Output
Ports
Switch
Matrix
RCE Mode
Control
Reset Method
Power-on Reset
Serial TAP
OP
NC
1
TLR1
(RC Enabled)
Hardware Reset
HW_RST# (low pulse)
OP
NC
1
TLR
(RC Enabled)
1. Low Pulse on SRST# Unchanged Unchanged
Unchanged
Unchanged
TLR
TLR
2. SMS high for 5
TCLK cycles
Unchanged Unchanged
Serial Reset
3. Device Reset
(instruction 1101)
OP
NC
NC
NC
NC
1
TLR
(RC Enabled)
4. Reset Crosspoint
Array (instruction 0010)
Unchanged
OP
Unchanged
Unchanged
Unchanged
Unchanged
1. Device reset
(instruction 1101)
1
(RC Enabled)
RapidConfigure
Reset
2. Reset Crosspoint
Unchanged
Unchanged
Array (instruction 0010)
1. TLR = Test Logic Reset state.
18
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I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
2. Pin Description
Table 11 OCX961 Pin Description
Pin Name
INP[47:0]
# of Pins
Type
Input
Input
Output
Output
Input
Input
Input
Description
Non-inverting differential input signals
Inverting differential input signals
Non-inverting differential input signals
Inverting differential input signals
Global Output Enable
48
48
48
48
1
INN[47:0]
OUTP[47:0]
OUTN[47:0]
OE#
HW_RST#
UPDATE#
1
Hardware Reset
1
Global Update
RC Pins
RCA[6:0]
RCB[6:0]
RCO[2:0]
RCI[3:0]
RC_CLK#
RC_EN#
7
7
3
4
1
1
Input
Input
Output
Input
Input
Input
RapidConfigure Address A
RapidConfigure Address B
RapidConfigure Readback
RapidConfigure Instruction Bits
RapidConfigure Clock
RapidConfigure Cycle Enable
Serial Interface Pins
SCLK
SMS
1
1
1
1
1
Input
Input
Input
Input
Output
Serial Clock
Serial Mode Select
Serial Data In
Serial Reset
SDI
SRST#
SDO
Serial Data Out
Power and Ground Pins
VDD.CORE
12
8
2.5V Power
Core Voltage
(2)
VDD.PAD
3.3V Power
3.3V Power
Differential Output Buffer Voltage
(1, 3)
VDD.IN
8
LVTTL Control pins Voltage and Differential Input
Buffer Voltage
VSS
NC
38
3
Ground
Ground
No Connect
No Connect
NOTES:
1. Dedicated differential input buffers can receive both LVPECL and LVDS voltage levels using
3.3V supply.
2. VDD.PAD is 3.3V for LVPECL outputs.
3. The LVTTL control, Serial pins, and differential input ports are 3.3V—they are not 5V tolerant.
I-Cube, Inc.
[Rev. 1.0] 4/25/01
19
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
3. Differential I/O Standards
The OCX961 support the two most popular differential signaling standards: Low Voltage Positive Emitter
Coupled Logic (LVPECL) and Low Voltage Differential Signaling (LVDS).
LVPECL is commonly used in video switching applications or those designs requiring transmission of high-
speed clock signals. This is the default I/O supported by the OCX961 device.
LVDS is typically used in communication systems as high speed, low noise point-to-point links. The OCX961
conforms to the ANSI/TIA/EIA-644 standard covering electrical specifications for output drivers and receiver
inputs.
3.1 LVPECL
LVPECL is a differential signaling standard that specifies two pins per input or output. The voltage swing
between these two signal lines is approximately 850 mV. The use of a reference voltage or a board
termination voltage is not required.
Transmitting and receiving circuits for LVPECL are shown in Figure 6 with termination resistors
integrated on-chip, thus, removing the need for any external resistors. Integrated Output Attenuation
resistors produce the required LVPECL output swing while providing a 100 ohm output impedance to
minimize return reflections.
OCX961
Device
Z
0=50
Ω
Z0=50Ω
VDD.PAD
= 3.3V
OUTP
INP
Switch
Matrix
From LVPECL
Driver
+
–
RT
To Receiver
110
Z
0=50
Ω
Z0=50Ω
INN
OUTN
Figure 6 OCX961 Operating in LVPECL Mode
3.2 LVDS
LVDS is a differential signaling standard that requires the use of two pins per input or output. It requires
that one data bit is carried through two signal lines. As with all differential signaling standards, LVDS has
an inherent noise immunity over single-ended standards. The voltage swing between two signal lines is
approximately 350mV. The use of a reference voltage or a board termination voltage is not required.
Note – It is possible to operate the OCX961 device withh VDD.PAD = 2.5V that will allow the
outputs to closely approximate “true LVDS” levels. Refer to the application note “Operating the
OCX961 in LVDS Mode” for further details.
20
[Rev. 1.0] 4/25/01
I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
4. Electrical Specifications
4.1 Absolute Maximum Ratings
Table 12 Absolute Maximum Ratings1
Symbol
VDD.CORE
VDD.IN
Parameter
Supply Voltage (core)
Supply Voltage (inputs)
Limits
Units
V
-0.3 to +3.0
-0.3 to +3.6
V
VDD.PAD
Supply Voltage (differential outputs) -0.3 to +3.6
V
-0.3 to +3.63
V
2
VIN
Input Voltage
TJ
Junction Temperature
Storage Temperature
Maximum Power Dissipation
Electrostatic Discharge
+150
°C
°C
W
V
TSTG
PMAX
ESD6
-65 to +150
6
2000
4.2 Recommended Operating Conditions
Table 13 Recommended Operating Conditions
Parameter Limits
Supply Voltage (core)
Symbol
VDD.CORE
VDD.PAD4
VDD.IN
Units
V
+2.375 to +2.625
3.3V ±10%
Supply Voltage (differential output buffers)
Supply Voltage (inputs)
V
+3.0 to +3.6
V
Operating Temperature: Commercial
Operating Temperature: Industrial
0 to +70
-40 to +85
TA
°C
4.3 Pin Capacitance
Table 14 Pin Capacitance5
Symbol
Parameter
Max
Units
CPIN
Signal Pin Capacitance
10
pF
1. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2. A maximum undershoot of 2V for a maximum duration of 20 ns is acceptable. Overshoot to 3.6V is acceptable.
3. All inputs are 3.3V tolerant with the V pin at 2.5V or 3.3V.
DD
for differential outputs are I/O Standard dependent.
4. Note that min and max values for V
DD
5. Capacitance measured at 25°C. Sample tested only.
6. Measured using Human Body Model.
I-Cube, Inc.
[Rev. 1.0] 4/25/01
21
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
4.4 DC Electrical Specifications
(TA = -40°C to 85°C, VDD.IN = 3.3V ±10%, VDD.CORE = 2.5V ±5%)
Table 15 LVTTL DC Electrical Specifications
Symbol
VIH
Parameter
High-level Input
Conditions
Ports are 3.3V tolerant
Ports are 3.3V tolerant
Min
2.0
Max
3.6
Units
V
VIL
Low-level Input
-0.3
2.4
0.8
V
VOH
High-level Output
VDD.PAD = Min
IOH = -4mA
V
DD.PAD+ 0.3
V
VOL
ILIH, ILIL
ILOZ
Low-level Output
VDD.PAD = Min
IOL = 8mA
0.4
V
(1)
Input Pin Leakage Current
VDD.IN= Max
0.0 < In < VDD.PAD
+5
-50
µΑ
µΑ
Tristate Leakage Output OFF State VDD.PAD = Max
0.0 < In < VDD.PAD
+5
-5
Power
(2)
PDDQ
Quiescent Power
All VDD = Max
0.5
W
Table 16 LVPECL DC Electrical Specifications
Symbol
VIN_DIFF
VIN_COM
VOUT_DIFF
DC Parameters
Min
±100
0.25
Max
Units
mV
V
Input Differential Voltage
Input Common Mode Voltage
Output Differential Voltage
2.25
±650
±900
mV
V
VOUT_COM Output Common Mode Voltage
VDD.PAD
2
VDD.PAD
2
1. All LVTTL input pins have pull-up resistors.
2. See section 5 for dynamic power consumption calculation.
3. Maximum capacitive load is 12 pF.
The VOH levels are 200mV below standard single-ended LVPECL levels and are compatible with devices
tolerant of lower common-mode ranges. The above table summarizes the DC output specifications of
LVPECL.
22
[Rev. 1.0] 4/25/01
I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
4.5 LVPECL AC Electrical Specifications
(VDD.IN = 3.3V ±10%, VDD.CORE = 2.5V ±5%, , VDD.PAD = 3.3V ±10%)
Table 17 LVPECL AC Electrical Specifications
0°C to 70°C
-40°C to +85°C
Symbol
Parameter
Min
Max
1.6
Min
Max
1.6
Units
Gb/s
ns
(1)
RDATA
tPHL, tPLH
tW+
NRZ Data Rate
One Way Signal Propagation Delay, Fanout = 1
Input Flow-through Positive Pulse Width
Input Flow-through Negative Pulse Width
3.0
3.5
0.6
0.6
0.6
0.6
ns
tW-
ns
tDCD+, tDCD- Duty Cycle Distortion
0.12
TBD
0.2
0.12
TBD
0.25
5
ns
tJITTER
tSK
tPHZ_OT
tPLZ_OT
tPZH_OT
tPZL_OT
Output Jitter
TBD
TBD
ps
(1)
Skew between Output Ports
Output Enable to Valid Data
ns
,
5
ns
,
Output Enable to High Z State
5
5
ns
tRC
RapidConfigure Clock Period
12
5
12
5
ns
ns
tW+_RC
tW-_RC
RapidConfigure Clock Pulse Width
tS_RC
tH_RC
tP_UD
fSI
RapidConfigure Address Setup to RC_CLK#
RapidConfigure Address and Enable Hold Time to RC_CLK#
Update of Crosspoint to Data Out
3
3
4
4
ns
ns
10
20
30
10
20
30
ns
Serial Clock Frequency (SCLK)
MHz
ns
tW_SI
tS_SI
tH_SI
tP_SI
Serial Clock Pulse Width (SCLK) @ 20MHz cycle
Serial Setup Time
20
4
20
4
ns
Serial Hold Time
0
0
ns
Serial Clock to Output Data Valid (SDO)
20
20
ns
NOTES:
1. These parameters are guaranteed but not tested in production.
I-Cube, Inc.
[Rev. 1.0] 4/25/01
23
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
4.6 Timing Diagrams
Note – For the purpose of clarity, the timing diagrams within this data sheet are conceptual
representations only and do not show actual circuit implementation.
InPort 1
InPort 2
tW+
tPLH
tPHL
IN
OP
OutPort 1
InPort 1
InPort 2
OutPort 1
OutPort 2
tSK
tSK
Switch
Matrix
OutPort 2
Figure 7 Flow-Through Mode Timing
OE#
t
InPort
t
PZH_OT
PHZ_OT
IN
OP
t
Switch
Matrix
PZL_OT
t
PLZ_OT
OutPort
InPort
OutPort
OE#
Figure 8 Output Enable Timing
tIN-
tIN+
InPort
Switch
Matrix
IN
OP
InPort
OutPort
tOUT-
tOUT+
OutPort
tDCD+ = tIN+ - tOUT+
tDCD- tIN- - tOUT-
=
Figure 9 Duty Cycle Distortion
24
[Rev. 1.0] 4/25/01
I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
tRC
tRC
tW+_RC
tW-_RC
RC_CLK#
tS_RC
tH_RC
RCA/RCB Address,
Instruction
tS_RC tH_RC
RC_EN#
Figure 10 RapidConfigure Write Cycle
tRC
tRC
tW+_RC
tW-_RC
RC_CLK#
tS_RC
tH_RC
RCA/RCB Address,
Instruction
tS_RC tH_RC
RC_EN#
Data Valid
High Impedance
RCO
Figure 11 RapidConfigure Read Cycle
I-Cube, Inc.
[Rev. 1.0] 4/25/01
25
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
tW_SI
tW_SI
SCLK
tS_SI
tH_SI
SDI, SMS
tP_SI
SDO
Figure 12 Serial Timing
Typical Performance at 1.6 Gb/s with PRBS Data
(Currently not available for this document)
Figure 13 Typical Performance
26
[Rev. 1.0] 4/25/01
I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
5. Power Consumption
Chip power, consists of three integral elements (refer to Figure 14):
1. Input Power—This element is fixed (always ON) due to the DC current for differential outputs.
2. Core Power—This element is the same for LVPECL or LVDS outputs. Core power is a function of
data rate (Mb/s) and the number of connection paths through the switch matrix.
3. Output Power—This element is a fixed amount for each differential output. The value is zero if the
Output Enable (OE#) is disabled or set to OFF.
5.1 Power for LVPECL I/O
Core
Power
Output
Power
Input
Power
(always ON)
Switch
Matrix
Output
Buffer
OE#
320mW
0.015mW/Mbs/Connection
32mW/Output
+
+
Example: Worst Case = (320mW) + (0.015mW x 667 x 48) + (32mW x 48)
320mW
1536mW
480mW
+
+
= 2.34 watts
Figure 14 Power Consumption Diagram for the OCX961 using LVPECL
I-Cube, Inc.
[Rev. 1.0] 4/25/01
27
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
6. Component Availability and Ordering Information
OCXxxxs - PP###T
Family
# I/O Ports
Speed Grade
Blank = 667 Mb/s
1 = 1.6 Gb/s
Package Code
PB304 = Ball Grid Array
Temperature Range
Blank - Commercial (0°C to 70°C)
I - Industrial (-40°C to +85°C)
7. Glossary
CROSSPOINT: A single cell controlled by two RAM bits. The RAM bits are connected in a master-slave
configuration to provide an update for programming and changing program information all at once.
CROSSPOINT ARRAY: An array of Crosspoint cells used to connect any input port to any output port.
INPUT OR OUTPUT PATH: The signal flow from pin to array and array to pin. Each path has a register with
selectable clocks, drivers for the loaded outputs with selectable enables, and sense circuits to detect changes on
either side of the IO Buffer.
PORT: A name followed by a number to identify a pin on the device.
RAPIDCONFIGURE: A parallel programming method for the OCX devices. The RC mode uses 23 dedicated
pins to program the Crosspoint Array and the IO Buffers. The 23 pins consist of an enable, a clock, four
instruction bits, two seven-bit address fields, and a three-bit data field.
28
[Rev. 1.0] 4/25/01
I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
Revision History
Date/
Version No.
Description
4/25/2001
Revision 1.0
Preliminary release of “Advanced” mini data sheet.
I-Cube, Inc.
[Rev. 1.0] 4/25/01
29
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
8. Product Status Definition
Data Sheet Identification
Product Status
Definition
This data sheet contains the design specifications for
product development. Specification may change in any
manner without notice.
Advanced
Formative or In Design
This data sheet contains the preliminary data, and
supplementary data will be published at a later date. I-Cube
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
Preliminary
Preproduction Product
This data sheet contains final specifications. I-Cube
reserves the right to make changes at any time without
notice in order to improve design and supply the best
possible product.
No Identification
Obsolete
Full Production
This data sheet contains specifications for a product that
has been discontinued by I-Cube. The data sheet is
provided for reference information only.
No longer in Production
I-Cube® is a registered trademark and RapidConnect, RapidConfigure, ActiveArray, ImpliedDisconnect, IQ, IQX,
MSX, MSXPro, OCX, OCXPro, and PSX are trademarks of I-Cube, Inc. All other trademarks or registered trademarks
are the property of their respective holders. I-Cube, Inc., does not assume any liability arising out of the applications
or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights
of others.
The information contained in this document is believed to be current and accurate as of the publication date. I-Cube
reserves the right to make changes, at any time, in order to improve reliability, function, performance or design in order
to supply the best product possible.
I-Cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction
if such be made.
This product is protected under the U.S. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814,
5559971, 5625780, 5710550, 5717871, 5734334, 5781717, 5790048. Additional patents pending.
OCX961 Crosspoint Switch Advanced Mini Data Sheet— Rev 1.0, April 2001
Copyright © 1992-2001 I-Cube, Inc. All rights reserved. Unpublished—rights reserved under the copyright laws of
the United States. Use of copyright notices is precautionary and does not imply publication or disclosure.
I-Cube®, Inc.
2605S. WinchesterBlvd.
Campbell, CA95008 USA
Phone: +(408)341-1888
OCX961CrosspointSwitch—AdvancedMiniDataSheet
Revision1.0, April2001
Fax:
+(408)341-1899
Email:
marketing@icube.com
Document#:OCX961_DS_1.0
Internet: http://www.icube.com
30
[Rev. 1.0] 4/25/01
I-Cube, Inc.
OCX961 Crosspoint Switch—Advanced Mini Data Sheet
I-Cube, Inc.
[Rev. 1.0] 4/25/01
31
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