RC4200N [FAIRCHILD]
Analog Multiplier; 模拟乘法器
| 型号： | RC4200N |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Analog Multiplier |
| 文件： | 总23页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
RC4200
Analog Multiplier
Description
Features
The RC4200 analog multiplier has complete compensation
for nonlinearity, the primary source of error and distortion.
This multiplier also has three onboard operational amplifiers
designed specifically for use in multiplier logging circuits.
These amplifiers are frequency compensated for optimum
AC response in a logging circuit, the heart of a multiplier,
and can therefore provide superior AC response.
• High accuracy
• Nonlinearity – 0.1%
Temperature coefficient – 0.005%/°C
• Multiple functions
• Multiply, divide, square, square root, RMS-to-DC
conversion, AGC and modulate/demodulate
• Wide bandwidth – 4 MHz
• Signal-to-noise ratio – 94 dB
The RC4200 can be used in a wide variety of applications
without sacrificing accuracy. Four-quadrant multiplication,
two-quadrant division, square rooting, squaring and RMS
conversion can all be easily implemented with predictable
accuracy. The nonlinearity compensation is not just trimmed
at a single temperature, it is designed to provide compensa-
tion over the full temperature range. This nonlinearity
compensation combined with the low gain and offset drift
inherent in a well-designed monolithic chip provides a very
high accuracy and a low temperature coefficient.
Applications
• Low distortion audio modulation circuits
• Voltage-controlled active filters
• Precision oscillators
Block Diagram
I
I
2
1
Q1
Q2
–
+
V
OS1
–
+
V
OS2
+
–
Q4
Q3
I
I
3
4
RC4200
65-4200-01
REV. 1.2.1 6/14/01
RC4200
PRODUCT SPECIFICATION
Previous multiplier designs have suffered from an additional
undesired linear term in the above equation; the collector
Functional Description
The RC4200 multiplier is designed to multiply two input
current times the emitter resistance. The I r term intro-
C E
currents (I and I ) and to divide by a third input current (I ).
1
2
4
duces a parabolic nonlinearity even with matched transistors.
Fairchild Semiconductor has developed a unique and propri-
etary means of inherently compensating for this undesired
The output is also in the form of a current (I ). A simplified
circuit diagram is shown in the Block Diagram. The nominal
relationship between the three inputs and the output is:
3
I r term. Furthermore, this Fairchild Semiconductor devel-
C E
oped circuit technique compensates linearity error over tem-
perature changes. The nonlinearity versus temperature is
significantly improved over earlier designs.
I1I2
---------
I3
=
(1)
I4
The three input currents must be positive and restricted to a
range of 1 µA to 1 mA. These currents go into the multiplier
chip at op amp summing junctions which are nominally at
zero volts. Therefore, an input voltage can be easily
From equation (2) and by assuming equal transistor junction
temperatures, summing base-to-emitter voltage drops around
the transistor array yields:
I1
I2
I3
I4
converted to an input current by a series resistor. Any
number of currents may be summed at the inputs. Depending
on the application, the output current can be converted to a
voltage by an external op amp or used directly. This capa-
bilty of combining input currents and voltages in various
combinations provides great versatility in application.
KT
-------
q
-------
IS1
-------
IS2
-------
IS3
-------
IS4
In
= In
– In
–In
= 0 (3)
This equation reduces to:
IS1 S2
I
I1I2
---------------
--------- =
I3I4
(4)
IS3 S4
I
Inside the multiplier chip, the three op amps make the
collector currents of transistors Q1, Q2 and Q4 equal to their
respective input currents (I , I , and I ). These op amps are
The rate of reverse saturation current I I /I I , depends
S1 S2 S3 S4
on the transistor matching. In a monolithic multiplier this
matching is easily achieved and the rate is very close to
unity, typically 1.0 1%. The final result is the desired
relationship:
1
2
4
designed with current source outputs and are phase-compen-
sated for optimum frequency response as a multiplier. Power
drain of the op amps was minimized to prevent the introduc-
tion of undesired thermal gradients on the chip. The three op
amps operate on a single supply voltage (nominally -15V)
and total quiescent current drain is less than 4 mA. These
special op amps provide significantly improved performance
in comparison to 741-type op amps.
I1I2
---------
I3
=
(5)
I4
The inherent linearity and gain stability combined with low
cost and versatility makes this new circuit ideal for a wide
range of nonlinear functions.
The actual multiplication is done within the log-antilog
configuration of the Q1-Q4 transistor array. These four
transistors, with associated proprietary circuitry, were
specially designed to precisely implement the relationship.
ICN
kT
------ --------
VBEN
=
In
(2)
Q
ISN
Pin Assignments
I
1
2
3
4
8
7
6
5
I
1
2
V
V
OS2
–V
OS1
GND
S
I
(Output)
I
4
3
65-4200-07
2
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Absolute Maximum Ratings
Parameter
Supply Voltage1
Min.
Max.
-22
Unit
V
Input Current
-5
mA
°C
°C
Storage Temperature Range
Operating Temperature Range
Notes:
RC4200/4200A
RC4200/4200A
-55
0
+125
+70
1. For a supply voltage greater than -22V, the absolute maximum input voltage is equal to the supply voltage.
2. Observe package thermal characteristics.
Thermal Characteristics
(Still air, soldered into PC board)
8-Lead Plastic DIP
+125°C
8-Lead SOIC
Maximum Junction Temperature
Maximum P T < 50°C
+125˚C
300mW
—
468mW
D
A
Thermal Resistance θ
Thermal Resistance θ
—
JC
JA
160°C/W
6.25mW/°C
240˚C/W
4.17mW/˚C
For T > 50°C Derate at
A
Electrical Characteristics
(Over operating temperature range, V = -15V unless otherwise noted)
S
4200A
4200
Parameters
Test Conditlons
Min.
Typ.
Max. Min.
Typ.
Max. Units
Total Error as Multiplier
TA = +25°C
Untrimmed1
2.0
3.0
%
%
With External Trim
Versus Temperature
0.2
0.005
0.1
0.2
0.005
0.1
%/°C
%/V
%
Versus Supply (-9 to -18V)
Nonlinearity2
50µA ≤ I
1,2,4
A
≤ 250 µA,
0.1
0.3
T = +25°C
Input Current Range
1.0
1000 1.0
5.0
1000 µA
(I , I and I )
1
2
4
Input Offset Voltage
I = I = I = 150 µA
T = +25°C
A
10
mV
nA
1
2
4
Input Bias Current
I = I = I = 150 µA
300
500
1
2
4
T = +25°C
A
Average Input Offset
Voltage Drift
I = I = I = 150 µA
50
100 µV/°C
1
2
4
Output Current Range (I )3
1.0
1000 1.0
1000 µA
3
REV. 1.2.1 6/14/01
3
RC4200
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
(Over operating temperature range, V = -15V unless otherwise noted)
S
4200A
4200
Parameters
Test Conditlons
Min.
Typ.
Max. Min.
Typ.
Max. Units
Frequency Response,
-3dB point
Supply Voltage
4.0
-15
4.0
-15
MHz
V
-18
-9.0 -18
4.0
-9.0
4.0
Supply Current
I = I = I = 150 µA
mA
1
2
4
T = +25°C
A
Notes:
1. Refer to Figure 6 for example.
2. The input circuits tend to become unstable at I , I , I < 50 µA and linearity decreases when I , I , I > 250 µA
1
2
4
1 2 4
(eq. @ I = I = 500 µA, nonlinearity error ≈ 0.5%).
1
2
3. These specifications apply with output (I ) connected to an op amp summing junction. If desired, the output (I ) at pin (4) can
3
3
be used to drive a resistive load directly. The resistive load should be less than 700Ω and must be pulled up to a positive
supply such that the voltage on pin (4) stays within a range of 0 to +5V.
Applications Discussion
Current Multiplier/ Divider
Dynamic Range and Stability
The basic design criteria for all circuit configurations using
the RC4200 multiplier is contained in equation (1), that is,
The precision dynamic range for the RC4200 is from +50
µA
to +250 µA inputs for I , I and I . Stability and accuracy
degrade if this range is exceeded.
1
2
4
I1I2
I3 = ---------
I4
To improve the stability for input currents less than 50 µA,
The current-product-balance equation restates this as:
filter circuits (R C ) are added to each input (see Figure 2).
S S
I1I2 = I3I4 (6)
R
4
R
1
8
5
+V
Z
V
X
I
I
4
1
R
S
R
S
R
Z
4
R
1
7
8
5
V
V
X
Y
C
S
C
S
+
+
+
RC4200
I
I
I
1
4
+V
Z
R
2
V
R
X
7
1
1
2
I
=
1
V
I
=
V
4
Y
1
R
4
I
2
R
RC4200
O
4
R
S
V
O
R
2
I
3
+V
S
3
S
6
C
S
Ammeter
A
2
–
4
A1
V
R
–V
Y
I
=
2
2
+
2
I
3
3
6
–V
S
R
C
= 10k Ohms
= 0.005 µF
S
S
65-4200-02
65-4200-03
–V
S
Figure 2. Current Multiplier/Divider with Filters
Figure 1. Current Multiplier/Divider
Amplifier A1 is used to convert the I current to an output
3
voltage.
Multiplier: Vz = constant ≠ 0
Divider: Vy = constant ≠ 0
4
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Resistors R and R extend the range of the V and V
Y
inputs by picking values such that:
Voltage Multiplier/Divider
a
b
X
R
4
R
1
8
5
VX(min.) VREF
V
Z
V
V
X
Y
I1(min.) = ----------------------- + ------------- = 50 µA,
I
I
1
R1
Ra
4
7
VX(max.) VREF
and I1(max.) = ----------------------- + ------------- = 250 µA,
R1 Ra
RC4200
R
2
1
2
VY(min.) VREF
also I2(min.) = ---------------------- + ------------- = 50 µA,
I
2
R2
Rb
4
V
R
O
O
I
VY(max.) VREF
3
3
S
6
and I2(max.) = ----------------------- + ------------- = 250 µA.
R2
Rb
–V
V V
R R
1
V V
O Z
R R
O 4
X
Y
=
Resistor R supplies bias current for I which allows the
C
3
65-4200-04
2
output to go negative.
Figure 3. Voltage Multiplier/Divider
Resistors R and R permit equation (6) to balance, ie.:
CX
CY
VXVY R0R4
Solving for V0 = -------------------------------------
V
V
V
V
V
V
V
V
V
VZ
R1R2
REF
X
REF
Y
REF
0
REF
X
Y
---------------
-------- + --------------- -------- + ---------------
=
------ + --------------- + ------------ + ------------
R
D
R
R
R
R
R
R
R
R
1
a
2
b
0
C
CX
CY
For a multiplier circuit VZ = VR = constant
V
V
V
V
V
V V
REF
Y
X
X
REF
Y REF
---------------
----------------- + ------------------------- + ------------------------- +
=
R R
R R
1
R R
R R
R0R4
a
b
2
1
b
2 a
Therefore: V0 = VXVYK where K = ---------------------
VRR1R2
2
V
V V
V
V
V V
REF
0
REF
X
REF
Y REF
----------------
----------------------- + ------------------------- + ------------------------- +
R R
R R
R
R
R
R
c
d
0
d
cx
d
CY d
For a divider circuit VY = VR = constant
VX
VRR0R4
Cross-Product Cancellation
Cross-products are a result of ths V V and V V terms.
-------
VZ
Therefore: V0
=
K where K = ---------------------
R1R2
X
R
Y R
To the extend that R R = R R , and R R = R
R
CY d
1 b CX D 2 a
cross-product cancellation will occur.
Extended Range
The input and output voltage ranges can be extended to
include 0 and negative voltage signals by adding bias
Arithmetic Offset Cancellation
The offset caused by the V
REF
2 term will cancel to the
currents. The R C filter circuits are eliminated when the
S S
extent that R R = R R , and the result is:
a b
0 d
input and biasing resistors are selected to limit the respective
currents to 50 µA min. and 250 µA max.
V0VREF
VYVX
--------------------
R0Rd
--------------- =
R1R2
or V0 = VXVYK
Extended Range Multiplier
R0Rd
+VREF
---------------------------
where K =
VREFR1R2
R
R
R
5
R
D
A
B
C
I
8
V
X
Resistor Values
(Input)
R
1
I
1
4
Inputs:
7
VX(min.) ≤ VX ≤ VX(max.)
∆VX = VX(max.) – VX(min.)
VY(min.) ≤ VY ≤ VY(max.)
∆VY = VY(max.) = VY(min.)
VREF = Constant (+7V to +18V)
V0
RC4200
R
2
1
2
V
Y
V
O
(Input)
I
2
R
O
(Output)
4
I
3
3
6
S
+V
S
R
–V
C4
R
–V
S
CX
---------------
K =
(Design Requirements)
VXVY
65-4200-05
Figure 4. Extended Range Multiplier
REV. 1.2.1 6/14/01
5
RC4200
PRODUCT SPECIFICATION
∆VX
----------------
∆VY
200µA
VREF
----------------
R1
=
, R2
=
, Rd = ----------------
Multiplying Circuit Offset Adjust
10K ≤ R = R = R ≤ 50K
200µA
250µA
5
9
16
∆VXVREF
R = R = R , = 100Ω
7
11 14
Ra = --------------------------------------------------------------------------------
250µA∆VX – 200µA VX(max.)
R = R = 100Ω (V /0.05)
6
10
S
∆VXVREF
250µA∆VY – 200µA VY(max.)
R
= 100Ω (V /0.10)
15
S
Rb = --------------------------------------------------------------------------------
R = R | | R
8
1
a
R
R
= R | | R
2 b
12
13
RaRb
R1Rb
R2Ra
------------
Rd
-------------
Rd
Rc
=
, RCX
=
, Rcy = ------------
Rd
= R | | R | | R | | R
0
C
CX
CY
∆VX∆VYK
R0 = ----------------------------
160µA
+V
REF
+V
S
R
R
a
b
I
R
R
5
d
c
I
100 R
R19
d
R
1
8
7
R20
Z
OS
V
X
+V
R
S
17
(Input)
1
R
4
8
R
6
R
18
R
5
–V
S
X
OS
R
7
0.1 µF
RC4200
–V
S
R
–R can be used to help cancel
17 20
1
2
crossproduct errors caused by resistor
product mismatch.
V
Y
R
+V
2
(Input)
S
I
2
R
9
R
O
4
R
R
V
O
R
12
11
Y
10
OS
(Output)
I
3
3
6
0.1 µF
–V
–V
S
R
S
CY
–
R
CX
RC5534
+
+V
S
0.1 µF
R
13
R
V
OS
16
R
15
R
14
–V
S
65-4200-06
Figure 5. Multiplying Circuit Offset Adjust
Procedure
1. Set all trimmer pots to 0V on the wiper.
3. Connect V input to ground. Put in a full scale square
Y
wave on V input. Adjust Y (R ) for no square wave
OS
X
9
2. Connect V input to ground. Put in a full scale square
X
on V output (adjust for 0 feedthrough).
0
wave on V input. Adjust X (R ) for no square wave
OS
Y
5
on V output (adjust for 0 feedthrough).
4. Connect V and V to ground. Adjust V (R ) for 0V
X Y OS 16
0
on V output.
0
6
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Notice that it is necessary to match the above resistor cross-
products to within the amount of error tolerable in the out-
put offset, i.e., with a 10V F.S. output, 0.1% resistor cross-
product match will give 0.1% x 10V. untrimmable output
offset voltage.
Extended Range Divider
+V
REF
+V
REF
Resistor Values
Inputs:
R
R
R
5
R
d
b
c
a
R
az
R4
R1
V (min.) ≤ V ≤ V (max.)
8
X
X
X
V
X
V
(Input)
Z
∆V = V (max.) = V (min.)
X
X
X
I1
I4
(Output)
V (min.) ≤ V ≤ V (max.)
Z
Z
Z
7
1
RC4200
Multiplier
∆V = V (max.) = V (min.)
Z
Z
Z
V
REF
= Constant (+7V to +18V)
V
O
Outputs:
V (min.) ≤ V ≤ V (max.)
I2
RO
(Output)
4
2
0
0
0
I3
3
6
∆V = V (max.) = V (min.)
0
0
0
+VS
-VS
V0VZ
--------------
VX
K =
(Design Requirement)
RC5534
∆V0
750µA
∆VREF
250µA
∆VZ
200µA
-VS
R
----------------
-----------------
= , R4 = ----------------
R0
=
, Rb
ao
65-4200-08
∆V0VREF
750µA∆V0 – 700µA V0(max.)
Figure 6. Extended Range Divider
Rc = ------------------------------------------------------------------------------
As with the extended range multiplier, resistors R and R
az
ao
are added to cancel the cross-product error caused by the
biasing resistors, i.e.
∆VXVREF
250µA∆VZ – 200µA VZ(max.)
Rd = -------------------------------------------------------------------------------
V
---------------
V
V
V
V
V
V
V
V
REF
R
b
X
0
Z
REF
0
REF
Z
REF
-------- + --------- + --------- + ---------------
=
------ + --------------- ------- + ---------------
R
R
R
R
R
R
R
R
1
ao
az
a
0
C
4
D
RcRd
RcR4
R0Rd
------------
Rb
------------
Rb
Ra
=
, Raz
=
, Rao = -------------
Rb
2
V
V
V
V V
V
V
REF
X
REF
0
REF
Z
REF
R
----------------
------------------------- + ----------------------- + ------------------------ +
=
R R
R R
R
R
R
a
b
1
b
ao
b
az b
∆V0∆VZ
R1 = ----------------------
600µAK
2
V
V V
V V
V V
REF
0
Z
0
REF
Z
REF
----------------
--------------- + ----------------------- + ------------------------ +
R R
R R
R R
R R
c
d
0
4
0
d
4 c
To cancel cross-product and arithmetic offset:
R
R = R R , R R = R R and R R = R R
ao b 0 d az b 4 c a b c d
and the result is:
V0VZ
--------------
VX
-----------
or V0 =
VXVREF
--------------------- =
R1Rb
R0R4
VZK
V
REFR0R4
---------------------------
where K =
R1Rb
REV. 1.2.1 6/14/01
7
RC4200
PRODUCT SPECIFICATION
Divider Circuit with Offset Adjustment
+VREF
R
R
5
R
R
d
c
b
a
RAX
V Z
(Input)
R4
R1
8
VX
(Input)
+VS
+VS
VX (Offset)
I
I
1
4
R10
R11
R12
R8
R6
7
R13 ZOS
R5
RC4200
Multiplier
VZ (Offset)
XOS
R7
-VS
1
2
+VS
-VS
µ
0.1
F
I
RO
2
R21 = R
b
4
I
YOS
R18
VO
(Output)
R19
3
3
6
R20
R9
0.1µF
-VS
-VS
µ
0.1
F
R
ao
+VS
R14
R15
R16
R18-R21 can be used in place of R9 to help
cancel gain error due to resistor product
mis-match (See Appendix 1).
R17 VOS
VO (Offset)
-VS
65-1878
General
Example: Two-Quad Divider
V = K(V /V ), K = k, V = +V = +15V
10K ≤ R = R = R ≤ 50K
5
13 17
0
X
Z
REF
S
R + R ≈ R | | R | | R | | R
-10 ≤ V ≤ +10, therefore ∆V = 20
7
8
1
a
az
ao
X
X
R
6
≈ R (V /0.05)
0 ≤ V ≤ +10, therefore ∆V = 20
Z Z
7
S
R = R
-10 ≤ V ≤ +10, therefore ∆V = 20
9
b
0 0
R
10
R
11
R
12
R
14
R
16
≈ 100 x R
= 20K
= 100K
R = 26.7K
R = 333K
1
4
0
R = 60K
R , R , R = 10K
13 17
b
5
R = 50K
R , R = 1K
15
4
7
+ R ≈ R | | R
15
R = 37.5K
R , R = 20K
11
0
c
c
8
≈ R (V /0.10)
R = 300K
d
R , R , R = 300K
15
S
6
9
16
R = 187.5K
R
10
R
12
= 4.7M
= 100K
a
R
az
R
ao
= 31.25
= 133K
Figure 7. Divider Circuit with Offset Adjustment
8
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Divider Circuit Offset Adjustment Procedure
Square Root Circuit V = N√V
0
X
1. Set each trimmer pot to 0V on the wiper.
+VREF
2. Connect V (input) to ground. Put a DC voltage of
X
approximatey 1/2 V (max.) DC on the V (input) with
Z
Z
R
R
R
5
R
d
b
c
an AC (squarewave is easiest) voltage of 1/2 V (max.)
a
Z
peak-to-peak superimposed on it. Adjust X (R5) for
OS
zero feedthrough. (No AC at V )
0
R4
R1
8
VX
(Input)
I
I
1
4
V
(Max.)
7
z
RC4200
Multiplier
1/2 V (Max.)
z
1
2
1/2 V (Max.)
z
VO
(Output)
I
RO
2
4
I
0V
3
3
6
+VS
-VS
3. Connect V (input) to V (input) and put in the
X
Z
1/2 V (max.) DC with an AC of approximately 20 mV
Z
less than V (max.).
Z
R
-VS
ao
Adjust Z (R ) for zero feedthrough.
OS 13
65-1877
Figure 8.
V
(Max.)
z
2
2
2
V
V
V
V V
V
V V
V V
V
1/2 V (Max.)
z
X
REF
REF
0
REF
0
0
REF
0
REF
REF
------------------------- + ---------------- + ----------------------- = -------------- + ----------------------- + ----------------------- + ----------------
R R
R R
R
R
R R
R R
R
R
R R
1
b
a
b
ao
b
0
4
c
4
d
c d
0
0V
If R R = R R and R R R R + R R R R = R R R R
a
b
c
d
ao
b
0
d
ao
b
c
4
c
d 0 4
2
~
10 mV
V
V
V
V
R R
~
0
X
REF
REF 0 4
2
--------------
-------------------------
-------------------------------
Then
=
or V = V K where K =
0
X
R R
R R
R R
0
4
1
b
1 b
65-1868
and V = N
V
where N =
K
0
X
4. Return V (Input) to ground and connect V (max.)
X
Z
DC on V (input). Adjust output V (R ) for V
=
O
Z
OS 17
0 ≤ V ≤ V (max.)and V (max.) = N
V (max.)
X
X
X
0
0V
O
V
------------
V
X
5. Connect V (input) to V (input) and and in V (max.)
X
Z
Z
0
N =
(Design Requirements)
DC. (The output will equal K.) Decrease the input
slowly until the output (V - K) deviates beyond the
0
desired accuracy. Adjust Z to bring it back into toler-
OS
ance and return to Step 4. Continue steps 4 and 5 until
2
V (max.)
0
R
1
= ---------------------------
2
74µA N
V reduces to the lowest value desired.
Z
V
REF
R
R
= R = ---------------
a
d
Notice that as the input to VX and VZ gets closer to zero (an
illegal state) the system noise will predominate so much that
an integrating voltmeter will be very helpful.
50µA
V
REF
= R = -----------------
b
c
150µA
V (max.)
0
50µA
R
= ------------------------
4
V (max.)
0
125µA
R
R
= ------------------------
ao
0
V (max.)
0
= ------------------------
225µA
REV. 1.2.1 6/14/01
9
RC4200
PRODUCT SPECIFICATION
Square Root Circuit Offset Adjust
+VREF
R
R
5
R
R
d
c
b
a
R4
R1
8
VX
(Input)
I
I
4
1
+VS
RC4200
Multiplier
R8
R6
7
XOS
R5
R7
1
2
+VS
YOS
-VS
µ
µ
0.1
F
F
I
RO
R17 = R
2
b
4
I
VO
(Output)
R14
R15
+VS
3
3
6
R16
R9
0.1
-VS
-VS
µ
F
0.1
R
-VS
ao
+VS
R10
R11
R12
R14-R17 can be used in place of R9 to help
reduce linearity error due to resistor product
mis-match (See Appendix 1).
R13 VOS
-VS
65-1876
Figure 9. Square Root Circuit Offset Adjust
10K ≤ R5 = R13 ≤ 50K
Procedure
1. Set both trimmer pots to 0V on the wiper.
R7 = 100Ω
2. Put in a full scale (0 to V (max.) squarewave on V
X
X
VS
input. Adjust X (R5) for proper peak-to-peak ampli-
OS
tude on V output. (Scaling adjust)
0
---------
R6 = R7
0.05
||
||
3. Connect V input to ground. Adjust V (R13) for 0V
R8 = R1 Ra Rao
X
OS
on V output.
0
R9 = Rb
||
R10 = R0 RC
R11 = 100Ω
VS
11 0.1
------
R12 = R
10
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
2
Squaring Circuits V = K V
0
X
+VREF
R
R
R
c
R
d
b
a
R1
8
5
VX
(Input)
I
I
1
4
7
RC4200
Multiplier
R1
1
2
VO
(Output)
I
RO
2
4
I
3
3
6
+VS
-VS
RCX
RC5534
-VS
65-1875
Figure 10. Squaring Circuit
2
2
2
VX 2VXVREF VREF
V0VREF VREF VXVREF
-------2 + ------------------------- + ------------- = -------------------- + ------------- + ---------------------
2
R1Ra
R0Rd
RcRd
RcRd
R1
Ra
2
if Ra = RcRd and R1Ra = 2RCXRD
2
V0VREF
VX
R0Rd
2
--------------------
R0Rd
-------
or V0 = KVX where K =
2
--------------------
VREFR1
then
=
2
R1
V (min.) ≤ V ≤ V (max.) ∆V = V (max.) – V (min.)
X
X
X
X
X
X
V0
-------2
VX
K =
(Design Requirement)
∆VX
----------------
=
R1
Ra
200µA
∆VXVREF
--------------------------------------------------------------------------------
=
250µA∆VX – 200µA VX(max.)
VREF
----------------
Rd
Rc
=
=
250µA
2
Ra
------
Rd
R1Ra
------------
2Rd
Rcx
=
∆VX2K
------------------
160µA
R0
=
REV. 1.2.1 6/14/01
11
RC4200
PRODUCT SPECIFICATION
Squaring Circuits Offset Adjust
+VREF
+V
S
R
R
R
a
b
I
R
5
d
c
I
R
100 R
=
7
R
8
9
d
R
1
8
7
R
Z OS
10
VX
(Input)
1
R
4
5
R
-VS
RC4200
Multiplier
R -R can be used to cancel all
10
7
µ
0.1
F
linearity errors caused by input
offsets and resistor product
mis-match (See Appendix 1).
R
1
1
2
I
2
R
6
RO
4
V
O (Output)
I
3
3
6
µ
0.1
F
-VS
RCX
+V
S
+V
S
R
R
14
16
VOS
R
13
-VS
R
15
-VS
0.1µ F
65-1874
Figure 11. Squaring Circuit Offset Adjust
10K ≤ R10 = R11 ≤ 50K
R8, R15 = 100Ω
VS
Procedure
1. Set both trimmer pots to 0V on the wiper.
2. Put in a full scale ( V ) squarewave on V input.
X
X
Adjust Z (R10) for uniform output.
OS
------
R9, R14 = 100Ω
0.1
3. Connect V input to ground. Adjust V (R ) for 0V
X
OS 11
||
on V outputs.
0
R5, R6 = R1 Ra
||
||
R16 = R0 Rc Ra
12
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Errors Caused by Input Offsets
Appendix 1—System Errors
There are four types of accuracy errors which affect overall
system performance. They are:
R R
V
V
V
Z
1
V
Z
0
4
4
X
Y
V
=
V
V
V
V
V V
V V
OSX OSY
0
Y
OSX
X
OSY
0
OSZ
R R
0
• Nonimearity—Incremental deviation from absolute
accuracy. See Note 1.
• Scaling Error—Linear deviation from absolute accuracy.
• Output Offset—Constant deviation from absolute
accuracy.
V
V
Feedthrough
Feedthrough
Y
X
Scaling Error
Output Offset Error
• Feedthrough.—Cross-product errors caused by input
offsets and external circuit limitations. See Note 2.
System errors can be greatly reduced by externally trimming
the input offset voltages of the RC4200. ( 3.0% F.S. for
RC4200 and 0.1% for RC4200A.)
This nonlinearity error in the transfer function of the
RC4200 is 0.1% maximum ( 0.03 maximum for the
RC4200A). That is,
VZ
R
R
4
1
8
7
5
VX
+VS
+VS
I1I2
---------
0.1% F.S.(4)
R
1
I3
=
100 R
4
I4
XOS
ZOS
RC4200
Multiplier
R
2
-VS
1
2
-VS
VY
The other system errors are caused by voltage offsets on the
inputs of the RC4200 and can be as high as 3.0% ( 2.0%
for RC4200A).
+VS
RO
R
2
4
VO
VXVY R0R4
--------------- -------------
3
6
V0
=
3.0% F.S.(3)(4)
-VS
VZ R1R2
-VS
Ideal Op-Amp
VOS = 0
R
R
1
4
5
65-1870
8
VZ
VX
I
I
1
4
If X
OS
= X , Y
OSX OS
= Y
, Z
= -V ,
OSZ
OSY OS
7
RC4200
Multiplier
VXVY R0R4
(3)
R
2
--------------- -------------
VZ R1R2
then VO
0.3% F.S.
1
VY
I
RO
2
4
VO
2
Figure 13. RC4200 with Input Offset Adjustment
I
3
3
6
+VS
Extended Range Circuit Errors
-VS
The extended range configurations have a disadvantage in
that additional accuracy errors may be introduced by resistor
product mismatching.
Ideal Op-Amp
VOS = 0
Multiplier
65-1871
An error in resistor product matching will cause an
equivalent feedthrough or output offset error. See Figure 6.
Figure 12.
Notes:
1. The input circuits tend to become unstable at
I , I , I < 50 µA and linearity decreases when I , I , I >
R R = R α, V feedthrough (V = 0) = IαV
R
1 b CX d X Y X
1
2
4
1 2 4
250 µA (e.g., @ I = I = 500µA nonlinearity error ≈ 0.5%).
1
2
R R = R
2 a
R
β, V feedthrough (V = 0) = βV
CY d Y X Y
2. This section will not deal with feedthrough which is
proportional to frequency of operation and caused by stray
capacitance and/or bandwidth limitations. (refer to
Figure 12.)
3. Not including resistor tolerance or output offset on the
operational amplifier.
R R = R R γ, V offset (V = V = 0) = γV *
a b REF
C d
0
X
Y
Note:
*
Output offset errors can always be trimmed out with the
output op amp offset adjust, VOS (R16).
4. For 50 µA ≤ I , I , I ≤ 250 µA.
1
2 4
REV. 1.2.1 6/14/01
13
RC4200
PRODUCT SPECIFICATION
Select R to be 1% or 2% below (or above) the calculated
d
value. This will cause α and β to both be positive (or nega-
tive) by nearly the same amount. Now the effective value of
Reducing Mismatch Errors
You need not use 0.01% resistors to reduce resistor product
mismatch errors. Here are a couple of ways to obtain
maximum accuracy out of the extended range multiplier
(see Figure 4) using 1% resistors.
R can be trimmed with an offset adjustment Z (R ) on
d
OS 20
pin 5.
This technique causes: a slight gain error which can be com-
pensated with the R value, and an output of offset error that
Method 1
0
V
X
feedthrough, for example, occurs when V = 0 and
Y
can be trimmed with V (R ) on the output op amp.
OS 16
V
≠ 0. This V feedthrough will equal V V .
X OSY
OSY
X
Also, if V
≠ 0, there is a V feedthrough equal to
OSZ
X
Extended Range Divider
The only cross-product error of interest is the V
Z
V V
. A resistor-product error of α will cause a V
X OSZ
feedthrough of αV . Likewise, V feedthrough errors are:
X
X
Y
V V
Y OSX
, V V
and βV
feedthrough (V = 0 and V ≠ 0) which is easily adjusted
Y OSZ
Y
X
OSX
with X (R ). See Figure 6.
OS
5
Total feedthrough:
V V V V
αV βV (V + V ) V
OSZ
Resistor product mismatch will cause scaling errors (gain)
that could be a problem for very low values of V . Adjust-
X OSY Y OSX
X
Y
X
Y
Z
By carefully abusing X (R ), Y (R ) and Z (R ) this
OS OS OS 20
equation can be made to very nearly equal zero and the
feedthrough error will practically disappear.
5
9
ments to Y (R ) can be made to improve the high gain
OS 18
accuracy.
Square Root and Squaring
These circuits are functions of single variables so
feedthrough, as such, is not a consideration. Cross product
errors will effect incremental accuracy that can be corrected
A residual of set will probably remain which can be trimmed
outwith V (R ) at the output of amp.
OS 16
Method 2
Y (R ) or Z (R ). See Figure 9 and Figure 11.
OS 14 OS 10
Notice that the ratios of R R :R R and R R :R R are
1 b CX d 2 a CY d
both dependent of R also that R , R , R and R are all
d
1
2
a
b
functions of the maximum input requirements. By designing
a multiplier for the same input ranges on both V and V
X
Y
then R = R , R
= R and R = R . (Note: it is accept-
1
2
CX
CY
a
b
able to design a four quadrant multiplier and use only two
quadrants of it.)
14
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Therefore, the rms value of Asinωt becomes:
Appendix 2—Applications
A
Vrms = ------
Design Considerations for RMS-to-DC Circuits
Average Value
2
Consider V = Asinωτ. By definition,
in
RMS Value for Rectified Sine Waves
Consider V = |A sin ωt|, a rectified wave. To solve,
in
T
---
integrate of each half cycle.
VAG
=
2 VINdt
∫
0
1
T
---
i.e.
TVin2 dt =
∫
Where T = Period
0
ω = 2πf
T
T
1
---
T
2π
= ------
T
-2--A2sin2ωt dt+ T (–Asinωt)2dt
∫
∫
---
0
2
1
1
This is the same as TA2sin2ωt dt
--
∫
VIN
A
0
so, |Asinωt|rms = Asinωtrms
t
Practical Consideration: |Asinωt| has high-order harmonics;
Asinωt does not. Therefore, non-ideal integrators may cause
different errors for two approaches.
0
T
2
T
65-1873
T
---
2
(a)
---
VAG
=
2Asinωt dt
∫
T
Low Pass
2
0
V
IN
a
VO = VIN
rms
Filter
T
2
---
2
(b)
V
IN
2A
T
1
ω
------- ---
=
–
cos ωt
V
IN
VO
2
a
Absolute
Value
Low Pass
Filter
2
0
V
IN
VO
=
A VGVIN
b
2A
-------
2π
=
[– cos(π) + cos(0)]
65-4200-09
2
--
π
Average Value of Asinωt is
A
Figure 14.
2
RMS Value
Again, consider V = Asinωt
VIN
---------
V0
Avg
= V0
IN
T [VIN]2dt
1
T
---
Vrms
=
VAVG
=
2
∫
0
implies V0
=
Avg( V
)
IN
Vrms for Asinωtdt:
2
V0 Avg V
=
IN
T
1
T
Vrms
=
=
A2sin2ωt dt
---
∫
0
A2
------
T
1
1
T
--
-- – cos 2 cos 2 ωt dt
Vrms
∫
2
2
0
A2
------
2
1
4ω
T
0
T
------
sin2 ωt
Vrms
Vrms
Vrms
=
=
=
--- –
2
A2
T
2
------ ---
2
A2
------
2
REV. 1.2.1 6/14/01
15
RC4200
PRODUCT SPECIFICATION
+VREF
300K
200K
60K
300K
100K
100K
167K
5
100K
5
100K
100K
VIN
8
7
8
7
13.3K
µ
22
F
RC4200A
Multiplier
RC4200A
Multiplier
10K
1
50K
1
X2
X
100K
250K*
44.4K**
50K
60K
4
4
VOUT
2
2
3
6
3
6
1/2
RC5532
-VS
-VS
83.3K
1/2
RC5532
µ
F
0.1
µ
F
0.1
80K
+VS
15K
+VS
30K
45.5 K
100
10K
30K
10K
100
-VS
*Determines sacle factor (K) for X2 function.
**Determines sacle factor (K) for function.
-VS
X
65-1869
+V = +VREF = +15V
s
s
-V = -15V
2
Figure 15. RMS to DC Converter V =√V
OUT IN
If V is made proportional to the average value of Asinωt
Amplitude Modulator with A.G.C.
H
(i.e., 2A/π) and scaled by a value of π/2 then:
In many AC modulator applications, unwanted output
modulation is caused by variations in carrier input ampli-
tude. The versatility of the RC4200 multiplier can be utilizes
to eliminate this undesired fluctuation. The extended range
multiplier circuit (Figure 4) shows an output amplitude
V =A
H
and if: V = Modulating input (V )
X
M
inversely proportional to the reference voltage V
.
REF
and: V Carrier input (Asinωt)
Y
R0Rd
VXVY R0Rd
-------------
R1R2
Then: V = K V sinωt where K =
0
M
--------------- -------------
=
i.e., V0
VREF R1R2
The resistor scaling is determined by the dynamic range of
the carrier variation and modulating input.
By making V
REF
proportional to V (where V is the car-
Y Y
rier input) such that:
The resistor values are solved, as with the other extended
range circuits, in terms of the input voltages.
VREF = VH ( VY
=
)
∫
Input voltages:
Then the denominator becomes a variable value that auto-
matically provides constant gain, such that the modulating
Modulation voltage (V ): 0 ≤ V ≤ V (max.)
M
M
X
Carrier (V ): V = Asinωt
Y
Y
input (V ) modulates the carrier (V ) with a fixed scale
X
Y
Carrier amplitude fluctuation (∆A):
factor even though the carrier varies in amplitude.
A(min.) sint ≤ V ≤ A(max.) sinΩωt
Y
Dynamic Range (N): A(max.)/A(min.),
A(max.) = V (max.) and A(min.) = V (min.)
H
H
16
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
R
R
a
a
R
a
R1
5
8
7
VM
+V
S
R1
R
30K
a
R
a
10K
-VS
100
RO
µ
RC4200
Multiplier
0.1
F
R2
1
2
VY
=
ASIN ω
t
+VS
10K
R2
R
30K
a
4
µ
F
0.1
1/4
RC4156
100
3
6
VO
VM sin ω
=
-VS
t
-VS
+V
µ
0.1 F
R1
S
R*
R2
10K
R3
30K
30K
470
C1
-VS
1/2 R3
15K
R3
30K
R3
30K
p
2
R3 47K
1N914
p
2
t
= A
ω
VH
=
AVG A sin
1/4
RC4156
1/4
RC4156
*R1 R2
R
RO
a
1N914
65-1866
Figure 16. Amplitude Modulator with A.G.C.
Example 1
= Asinωt 2.5V ≤ A ≤ 10V, therefore N = 4
The maximum and minimum values for I and I lead to:
1
2
V
Y
VX(max.) VH(max.)
0V ≤ V ≤ 10V, therefore V (max.) = 10V
M
X
I1(max.) = ------------------------ + ------------------------ = 250µA
K = 1, therefore V = V sinωt
R1
Ra
0
M
VX(max.)
VH(min.)
10V
50µA
R1 = ----------------------- = ------------- = 2 0 0 K
I1(min.) = ----------------------- = 50µA VM(min.) = 0
50µA
Ra
A(max.)
50µA
10V
50µA
VH(max.)
A(max.)
R1 = ------------------- = ------------- = 2 0 0 K
I2(max.) = -------------------- + ------------------------ = 250µA
R2
Ra
A(min.)
2.5V
50µA
Ra = ------------------ = ------------- = 5 0 K
VH(min.)
50µA
I2(min.) = ----------------------- = 50µA
Ra
R1R2
200K × 200K
-------------
---------------------------------
= 800K
RO = K
= 1
Ra
50K
For a dynamic range of N, where
A(max.)
Example 2
= Asinωt 3 ≤ A ≤ 6, therefore N = 2
--------------------
N =
< 5,
A(min.)
V
Y
0V ≤ V ≤ 8V, therefore V (max.) = 8V
M
X
These equations combine to yield:
V (max.)
K = 0.2, therefore V = 0.2 V sinwt
0
M
so:
R = 53.3K, R = 40K
A(max.)
(5 – N)50µA
----------X----------------------
--------------------------------
,
R1
=
, R2
1
2
(5 – N)50µA
R = 60K and R = 7.11K
a
0
R1R2
A(min.)
------------------
-------------
,
Ra
=
and RO = K
50µA
Ra
REV. 1.2.1 6/14/01
17
RC4200
PRODUCT SPECIFICATION
Inputs
VZ
+VS
VOS4 ADJ
R1
8
7
VX
R4
100 R4
I
1
5
R
s
C
s
+V
I
S
4
-VS
VOS1
50 mV
RC4200
Multiplier
R1
100
RO
0.1 µF
50 mV
R2
-VS
1
VY
I
2
Gain
Adj.
R
s
4
C
s
+V
Output
VO
S
1/4
4156
I
3
VOS3
VOS2
2
µ
F
0.1
3
6
100
µ
0.1
F
50 mV
-VS
+V
S
-VS
R O
µ
RS = 10K, CS = 0.005
VX VY
F
µ
100 V
-VS
V
=
K
s
V
z
65-1867
RO R4
R1 R2
Where K =
Limited Range, First Quadrant Applications
Thermal Symmetry
The following circuit has the advantage that cross-product
errors are due only to input offsets and nonlinearity error is
sightly error is slightly less for lower input currents.
I
1
2
3
4
8
7
6
5
I
1
2
V
V
The circuit also has no standby current to add to the noise
content, although the signal-to-noise ratio worsens at very
low input currents (1-5 µA) due to the noise current of the
input stages.
Thermal
Symmetry
Line
OS2
–V
OS1
GND
S
Output I
I
4
3
The R C filter circuits are added to each input to improve
S S
the stability for input currents below 50 µA.
65-0070
The scale factor is sensitive to temperature gradients across
the chip in the lateral direction. Where possible, the package
should be oriented such that forces generating temperature
gradients are located physically on the line of thermal sym-
metry. This will minimize scale-factor error due to thermal
gradients.
Caution!
The bandpass drops off significantly for lower currents
(<50 µA) and non-symmetrical rise and fall times can cause
second harmonic distortion.
18
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
+3
+1
-1
200 µA ac*
µ
250 A dc
5
4
8
V
x
V
z
µ
150 A dc
7
1
2
4200
µ
250 A dc
-3
VY
-5
V
o
-7
6
3
-15V
-9
* Peak to Peak
-11
10
102
103
104
105
106
107
Frequency (Hz)
+3
+1
-1
250 µA dc
µ
250 A dc
5
4
8
7
1
2
V
V
x
z
4200
µ
200 A ac*
-3
VY
µ
150 A dc
-5
V
o
-7
6
3
-15V
-9
* Peak to Peak
-11
10
102
103
104
105
106
107
Frequency (Hz)
+3
+1
-1
250 µA dc
µ
83.4 A ac*
5
4
8
7
1
2
V
V
x
z
µ
167 A dc
4200
µ
250 A dc
-3
VY
-5
V
o
-7
6
3
-15V
-9
* Peak to Peak
-11
10
102
103
104
105
106
107
Frequency (Hz)
Figure 18. Outputs
REV. 1.2.1 6/14/01
19
RC4200
PRODUCT SPECIFICATION
300
250
200
150
100
50
250
200
150
100
50
5 nA
4 nA
3 nA
2.5 nA
2 nA
1.0 nA
1.2 nA
150
1.5 nA
50
100
200
I2 ( µA)
Figure 19a. Output Noise Current (I )
250
300
150
50
100
200
250
I1 ( µA)
Figure 19b. Output Noise Current (I )
3
3
vs. Input Currents (I , I ) for I = 250µA
vs. Input Currents (I , I ) for I = 250µA
4 1 2
1
2
4
250
200
150
100
50
Multiplier Configuration
VXVY
V
=
o
10
VY = 0
VX = 10 sin
ω
t
VX = 0
ω
VY = 10 sin
t
0
1.0
10
100
1K
10K
1M
100K
Frequency (Hz)
Figure 20. AC Feedthrough vs. Frequency
20
REV. 1.2.1 6/14/01
PRODUCT SPECIFICATION
RC4200
Mechanical Dimensions
8-Lead SOIC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
A
.053
.004
.013
.008
.189
.150
.069
.010
.020
.010
.197
.158
1.35
0.10
0.33
0.20
4.80
3.81
1.75
0.25
0.51
0.25
5.00
4.01
A1
B
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
C
D
E
5
2
2
e
.050 BSC
1.27 BSC
H
h
.228
.010
.016
.244
.020
.050
5.79
0.25
0.40
6.20
0.50
1.27
L
3
6
N
α
8
8
0°
8°
0°
8°
ccc
—
.004
—
0.10
8
5
E
H
1
4
h x 45°
D
C
A1
A
α
SEATING
PLANE
– C –
L
e
LEAD COPLANARITY
ccc C
B
REV. 1.2.1 6/14/01
21
RC4200
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
8-Lead Plastic DIP Package
Notes:
Inches
Millimeters
Min. Max.
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E1" do not include mold flashing. Mold flash or protrusions
shall not exceed .010 inch (0.25mm).
A
—
.210
—
—
.38
5.33
—
A1
A2
B
.015
.115
.014
.045
.008
3. Terminal numbers are for reference only.
.195
.022
.070
.015
2.93
.36
4.95
.56
4. "C" dimension does not include solder finish thickness.
5. Symbol "N" is the maximum number of terminals.
B1
C
1.14
.20
1.78
.38
4
2
D
.348
.005
.300
.240
.430
—
.325
.280
8.84
.13
10.92
—
D1
E
7.62
6.10
8.26
7.11
2
5
E1
e
.100 BSC
2.54 BSC
eB
L
—
.430
.160
—
10.92
4.06
.115
2.92
N
8°
8°
D
1
4
E1
D1
5
8
e
E
A2
A
A1
C
L
eB
B1
B
22
REV. 1.2.1 6/14/01
RC4200
PRODUCT SPECIFICATION
Ordering Information
Part Number
RC4200N
Package
Operating Temperature Range
8-Lead Plastic DIP
8-Lead Plastic DIP
8-Lead SOIC
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
RC4200AN
RC4200M
RC4200AM
8-Lead SOIC
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/14/01 0.0m 003
Stock#DS30004841
© 2001 Fairchild Semiconductor Corporation
相关型号：
RC4207GN
Operational Amplifier, 2 Func, 250uV Offset-Max, BIPolar, PDIP8, MINI, PLASTIC, DIP-8
FAIRCHILD
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