SG6510DY1 [FAIRCHILD]
Power Supply Support Circuit, Fixed, 1 Channel, GREEN, MS-001BA, DIP-8;
| 型号： | SG6510DY1 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, GREEN, MS-001BA, DIP-8 |
| 文件： | 总12页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2008
SG6510X1 — PC Power Supply Supervisors
Features
Description
SG6510 is designed to provide the voltage supervisor
function, remote on/off PSON function, power-good
(PGO) indicator function, and fault protection (FPO)
function for switching power systems.
Over-Voltage Protection (OVP) for 3.3V, 5V, 12V
Under-Voltage Sense (UVS) and Under-Voltage
Protection (UVP) for 3.3V, 5V
Open-Drain Output for PGO and FPO Pins
300ms Power-Good Delay
For the supervisor function, it provides the over-voltage
protection (OVP) monitoring for 3.3V, 5V, and 12V (12V
via VDD pin); under-voltage sense (UVS) monitoring for
3.3V and 5V; and under-voltage protection (UVP)
monitoring for 3.3V and 5V. When 3.3V or 5V voltage is
decreasing to 2.8V and 4.2V, respectively, the under-
voltage sense (UVS) function is enabled to reset the
PGO signal from high to low. If 3.3V or 5V voltage is
further decreasing to 2.5V and 3.6V, respectively, FPO
is set high to turn off the PWM controller IC. To achieve
better immunity for lighting surge glitch and to prevent
accidental power shut down during dynamic loading
condition, the debounce time for UVP and UVS is
2ms/1ms, respectively. The deglitch time for OVP is
75µs for better noise immunity. During an AC sag or
brownout situation, UVP functions can still be enabled
to protect power supply in case of output short circuit.
75ms Turn-on Delay for 3.3V and 5V
2.8ms PSON Control to FPO Turn-off Delay
38ms /38ms PSON Control Debounce
350μs Width Noise Deglitches
2ms UVP Debounce Time
1ms UVS Debounce Time
No Lockup During the Fast AC Power On/Off
Brownout Protection Function for 3.3V and 5V
Wide Supply Voltage Range from 4V to 15V
The power supply is turned on after 38ms debounce
time when the PSON signal is set from high to low. To
turn off the power supply, the PSON signal is set from
low to high and the debounce time is 38ms. The PGI
circuitry provides a sufficient power-down warning
signal for PGO. When PGI input is lower than the
internal 1.2V reference voltage, after 350μs debounce
time, the PGO signal is pulled low.
Ordering Information
Part Number Operating Temperature Range
Package
Packing Method
Eco Status
Green
SG6510DY1
SG6510DZ1
SG6510SZ1
SG6510SY1
DIP-8
DIP-8
Tube
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
RoHS
Tube
SOP-8
SOP-8
RoHS
Tape & Reel
Tape & Reel
Green
For Fairchild’s definition of “green” please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
Application Diagram
5V
5V
SG6510
12V
1
2
3
4
8
7
6
5
PGI
PGI
PGO
VDD
VS5
5VSB
GND
FPO
PSON
5V
PSON
3.3V
VS33
Figure 1.
Typical Application
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
2
Internal Block Diagram
Figure 2.
Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
3
Timing Diagram
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
4
Marking Information
8
T: D = DIP
P: Z = Lead Free
SG6510TP1
Null = regular package
XXXXXXX: Wafer Lot
YY: Year; WW: Week
V: Assembly Location
XXXXXXXYYWWV
1
※ Marking for SG6510DZ1 (Pb-free)
SG6510SZ1 (Pb-free)
1’st line
Z: Assembly plant code
X: Year code
Y: Week code
TT: Die run code
3’rd line
T: Package type (D = DIP, S=SOP)
P: Y=Green package
M: Manufacture flow code
※ Marking for SG6510DY1 (Green-compound)
SG6510SY1 (Green-compound)
Figure 3.
Top Mark
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
5
Pin Configurations
PGI
PGO
VDD
GND
FPO
VS5
VS33
PSON
Figure 4.
Pin Configuration
Pin Definitions
Pin # Name
Type
Description
Power-good input. For ATX SMPS, it detects main AC voltage under-
voltage and/or failure.
1
2
PGI
Analog Input
Supply
GND
Ground.
Fault protection output (invert). Output signal to control the PWM IC.
For example, it controls the PWM IC of primary side through an opto-
coupler. When FPO is low, the main SMPS is operational.
3
FPO
Logic Output
Remote on/off logic input from CPU or main-board. Turn on/off the
PWM output after a 38ms delay.
4
PSON
Logic Input
5
6
VS33
VS5
Analog Input
Analog Input
3.3 V over/under-voltage control sense input.
5 V over/under-voltage control sense input.
Supply voltage; 4V ~ 15V. For ATX SMPS, it is connected to 5V-
standby and 12V through diodes, respectively.
7
8
VDD
PGO
Supply
Power-good logic output, 0 or 1(open-drain). Power good = 1 means
that the power is good for operation. The power-good delay is 300ms.
Logic Output
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
6
Function Table
UV Sense
(3.3V or 5V)
UV Protection
(3.3V or 5V)
PGI
PSON
OV Protection
FPO
PGO
PGI<1.2V
PGI<1.2V
PGI<1.2V
PGI<1.2V
PGI<1.2V
PGI<1.2V
PGI<1.2V
PGI<1.2V
PGI>1.2V
PGI>1.2V
PGI>1.2V
PGI>1.2V
PGI>1.2V
PGI>1.2V
PGI>1.2V
PGI>1.2V
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
No
Yes
No
No
No
No
No
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
Yes
No
No
L
No
Yes
No
H
L
Yes
Yes
No
Yes
No
Yes
Yes
Yes
No
H
H
H
L
Yes
Yes
No
Yes
No
Yes
No
No
No
L
Yes
No
No
H
H
H
H
H
H
H
No
Yes
No
Yes
Yes
No
Yes
No
Yes
Yes
Yes
X
Yes
Yes
X
Yes
X
X = Don’t care
FPO = L means: fault IS NOT latched
FPO = H means: fault IS latched
PGO = L means: fault
PGO = H means: No fault
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
7
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Min.
-0.3
-0.3
-0.3
Max.
16
Unit
V
DC Supply Voltage
Input Voltage
Vi
PSON, VS33, VS5, PGI
8.0
16
V
FPO
PGO
V
VOUT
Output Voltage
-0.3
-40
-55
8.0
+85
+150
+260
2
V
TA
TSTG
TL
Operating Free Air Temperature Range
Storage Temperature Range
Soldering Temperature
°C
°C
°C
KV
ESD
Electrostatic Discharge Capability
Human Body Model
Note:
1. Stresses above those listed may cause permanent damage to the device.
Recommended Operating Conditions
Symbol
VDD
Parameter
Min.
Max.
15
7
Unit
V
DC Supply Voltage
Input Voltage
4
VIL
PSON, VS33, VS5, PGI
V
FPO
PGO
FPO
PGO
15
7
VOUT
Output Voltage
V
20
10
IoSINK
Output Sink Current
mA
TR
TA
Supply Voltage Rising Time(2)
1
ms
°C
Operating Free Air Temperature Range
-30
85
Note:
2.
VDD rising and falling slew rate must be less than 14V/ms.
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
8
Electrical Characteristics
Unless otherwise noted, VDD=12V and TA=25°C.
Symbol
Over-Voltage Protection
Over-Voltage Protection VS33
Parameter
Conditions
Min.
Typ.
Max.
Units
3.7
5.7
3.9
6.1
4.1
6.5
14.4
5
VOVP
V
Over-Voltage Protection VS5
Over-Voltage Protection VDD
Leakage Current (FPO)
13.2
13.8
ILKG
VOL
μA
V
V
FPO = 5V
Isink 20mA
Low-Level Output Voltage (FPO)
Timing, OVP to Protection
0.7
110
tD-VDDOVP
ms
33
75
Under-Voltage and PGI, PGO
VPGI
Input Threshold Voltage PGI
Under-Voltage Sense VS33
Under-Voltage Sense VS5
Under-Voltage Protection VS33
Under-Voltage Protection VS5
Timing UVS to Sense (PG)
Timing UVP to Protection (FPO)
Leakage Current (PGO)
1.15
2.6
4.0
2.3
3.4
0.6
1.3
1.20
2.8
4.2
2.5
3.6
1.0
2.0
1.25
3.0
4.4
2.7
3.8
1.5
3.0
5
V
V
V
VUVS
VUVP
tUVS
tUVP
ILKG
VOL
tUVE
ms
ms
μA
V
PGO = 5V
Low-Level Output Voltage (PGO)
Under-Voltage Enable Delay Time
Timing PG Delay
VDD = 12V, ISINK 10mA
0.7
114
450
450
49
75
ms
ms
μs
PGI to PGO
PGI to PGO
200
200
300
350
tPG
Noise Deglitch Time
PSON Control
IPSON Input Pull-up Current
VIH
PSON = 0V
100
160
1.85
1.35
38
220
μA
V
High-Level Input Voltage
Low-Level Input Voltage
2.40
VIL
1.2
57
V
On
Off
24
24
tPSON
Timing, PSON to On/Off
ms
ms
38
57
tPSOFF
Timing PG Low to Power Off
1.6
2.8
4.5
Total Device
IDD
Supply Current
PSON = 5V/VDD = 5V
0.7
1.5
mA
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
9
Physical Dimensions
9.83
9.00
6.67
6.096
8.255
7.61
3.683
3.20
7.62
5.08 MAX
0.33 MIN
3.60
3.00
(0.56)
2.54
0.356
0.20
0.56
0.355
9.957
7.87
1.65
1.27
7.62
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSIONS AND TOLERANC
ASME Y14.5M-1994
ES PER
E) DRAWING FILENAME AND REVSION: MKT-N08FREV2.
Figure 5.
8-Pin, DIP-8 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
10
Physical Dimensions (Continued)
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 6. 8-Pin SOP Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
11
© 2008 Fairchild Semiconductor Corporation
SG6510X1 • Rev. 1.1.1
www.fairchildsemi.com
12
相关型号：
SG6510SZ1
Power Supply Support Circuit, Fixed, 1 Channel, PDSO8, ROHS COMPLIANT, MS-012AA, SOP-8
FAIRCHILD
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