SN74ACT534SC [FAIRCHILD]
Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO16, PLASTIC, SOP-16;型号: | SN74ACT534SC |
厂家: | FAIRCHILD SEMICONDUCTOR |
描述: | Bus Driver, ACT Series, 1-Func, 8-Bit, True Output, CMOS, PDSO16, PLASTIC, SOP-16 光电二极管 |
文件: | 总6页 (文件大小:165K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
April 1998
74ACT534
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
Features
n ICC and IOZ reduced by 50%
n Edge-triggered D-type inputs
n Buffered positive edge-triggered clock
n 3-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
The ACT534 is a high-speed, low-power octal D-type flip-flop
featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all
flip-flops. The ACT534 is the same as the ACT374 except
that the outputs are inverted.
n ACT534 has TTL-compatible inputs
n Inverted output version of ACT374
Ordering Code:
Order Number
74ACT534SC
74ACT534PC
74ACT534SJ
Package Number
M16A
Package Description
16-Lead Molded Small Outline Package
N16E
16-Lead Molded Dual-In-Line Package
M16D
16-Lead (0.300" Wide) Molded Small Outline Package, EIAJ
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
DS009965-1
IEEE/IEC
DS009965-3
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE
3-STATE Output Enable Input
DS009965-2
O0–O7
Complementary 3-STATE Outputs
™
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1998 Fairchild Semiconductor Corporation
DS009965
www.fairchildsemi.com
Functional Description
The ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and hold
times requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation
of the OE input does not affect the state of the flip-flops.
Logic Diagram
DS009965-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Function Table
Inputs
Output
CP
N
N
OE
L
D
H
L
O
L
L
H
L
L
X
X
O0
Z
X
H
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
N =
LOW-to-HIGH Clock Transition
High Impedance
=
Z
=
O
Value stored from previous clock cycle
0
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2
Absolute Maximum Ratings (Note 1)
PDIP
140˚C
Supply Voltage (VCC
)
−0.5V to +7.0V
Recommended Operating
Conditions
DC Input Diode Current (IIK
)
=
VI −0.5V
−20 mA
+20 mA
=
VI VCC + 0.5V
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
DC Output Diode Current (IOK
)
Output Voltage (VO)
0V to VCC
=
VO −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
VIN from 0.8V to 2.0V
−40˚C to +85˚C
=
VO VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
@
VCC 4.5V, 5.5V
125 mV/ns
±
±
or Sink Current (IO
)
50 mA
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Farichild does not recom-
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
™
mend operation of FACT circuits outside databook specifications.
Storage Temperature (TSTG
Junction Temperature (TJ)
)
−65˚C to +150˚C
DC Electrical Characteristics
=
TA −40˚C to +85˚C
VCC
=
Symbol
Parameter
TA +25˚C
Units
Conditions
(V)
Typ
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
1.5
VOUT 0.1V
1.5
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High Level
Output Voltage
4.49
5.49
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
=
IOH −24 mA (Note 2)
=
IOUT 50 µA
VOL
Maximum Low Level
Output Voltage
0.001
0.001
0.1
0.1
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.36
0.36
0.44
0.44
V
=
IOL 24 mA (Note 2)
=
±
±
IIN
Maximum Input Leakage
Current
0.1
1.0
µA
µA
VI VCC, GND
=
±
±
IOZ
Maximum 3-STATE
Current
5.5
5.5
0.25
2.5
VI VIL, VIH
=
VO VCC, GND
=
VI VCC − 2.1V
ICCT
Maximum
0.6
1.5
mA
ICC/Input
=
VOLD 1.65V Max
IOLD
IOHD
Minimum Dynamic
5.5
5.5
75
mA
mA
=
VOHD 3.85V Min
Output Current
(Note 3)
−75
=
ICC
Maximum Quiescent
Supply Current
5.5
4.0
40.0
µA
VIN VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
3
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AC Electrical Characteristics
VCC
(V)
(Note 4)
=
=
TA −40˚C to +85˚C
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Min
Typ
Max
Min
Max
fmax
tPLH
tPHL
Maximum Clock
5.0
5.0
5.0
100
120
MHz
ns
Frequency
Propagation Delay
CP to Qn
2.5
2.0
6.5
6.0
11.5
10.5
2.0
2.0
12.5
12.0
Propagation Delay
CP to Qn
ns
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
2.5
2.0
1.5
1.5
6.5
6.0
7.0
5.5
12.0
11.0
12.5
10.5
2.0
2.0
1.0
1.0
12.5
11.5
13.5
10.5
ns
ns
ns
ns
±
Note 4: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
VCC
(V)
(Note 5)
=
=
TA −40˚C to +85˚C
TA +25˚C
Symbol
Parameter
Units
=
=
CL 50 pF
CL 50 pF
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
5.0
1.0
3.5
1.0
3.5
4.0
1.5
3.5
ns
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
−1.0
2.0
tW
CP Pulse Width
HIGH or LOW
±
Note 5: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
Conditions
=
VCC OPEN
CIN
pF
pF
=
VCC 5.0V
CPD
40.0
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4
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Molded Small Outline Package
Package Number M16A
16-Lead Molded Dual-In-Line Package
Package Number N16E
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead (0.300" Wide) Molded Small Outline Package, EIAJ
Package Number M16D
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Fairchild Semiconductor
Corporation
Fairchild Semiconductor
Europe
Fairchild Semiconductor
Hong Kong Ltd.
Fairchild Semiconductor
Japan Ltd.
Americas
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 8 141-35-0
8/F Room 808 Empire Centre
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Kowloon, Hong Kong
Tel: 852-2722-8338
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Tel: 1-888-522-5372
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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