SPT7835SCD [FAIRCHILD]
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, CDIP28, 0.300 INCH, CERDIP-28;
| 型号： | SPT7835SCD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, CDIP28, 0.300 INCH, CERDIP-28 CD 转换器 |
| 文件： | 总12页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7835
10-BIT, 5 MSPS, 75 mW A/D CONVERTER
FEATURES
APPLICATIONS
• Monolithic 5 MSPS Converter
• 75 mW Power Dissipation
• On-Chip Track-and-Hold
• Single +5 V Power Supply
• TTL/CMOS Outputs
• All High-Speed Applications Where
Low Power Dissipation is Required
• Video Imaging
• Medical Imaging
• 5 pF Input Capacitance
• Low Cost
• IR Imaging
• Scanners
• Tri-State Output Buffers
• High ESD Protection: 3,500 V Minimum
• Selectable +3 V or +5 V Logic I/O
• Digital Communications
GENERAL DESCRIPTION
The SPT7835 is a 10-bit monolithic, low cost, ultralow power
analog-to-digital converter capable of minimum word rates of
5 MSPS. The on-chip track-and-hold function assures very
good dynamic performance without the need for external
components.Theinputdriverequirementsareminimizeddue
to the SPT7835's low input capacitance of only 5 pF.
The SPT7835 has incorporated proprietary circuit design
andCMOSprocessingtechnologiestoachieveitsadvanced
performance. Inputs and outputs are TTL/CMOS-compat-
ible to interface with TTL/CMOS-logic systems. Output data
format is straight binary.
The SPT7835 is available in 28-lead 300 mil cerdip and
PDIP, 28-lead SOIC and 32-lead small (7 mm square) TQFP
packagesoverthecommercialtemperaturerange.For avail-
ability of extended temperature ranges, and /883 processing
requirements consult the factory.
Power dissipation is extremely low at only 75 mW typical at
5 MSPS with a power supply of +5.0 V. The digital outputs
are+3Vor+5Vandareuserselectable.TheSPT7835ispin-
compatiblewiththeentirefamilyofSPT10-bit, CMOSconvert-
ers (SPT7835/40/50/55/60/61) which simplifies upgrades.
BLOCK DIAGRAM
ADC Section 1
D10 Overrange
Auto-
1:8
Mux
11-Bit
SAR
11
Zero
A
T/H
IN
CMP
D9 (MSB)
11
D8
DAC
P1
P2
D7
11
11
ADC Section 2
.
.
.
.
.
.
CLK In
Enable
.
.
.
.
.
.
D6
Timing
and
Control
11-Bit
8:1
Mux/
Error
Correction
P7
ADC Section 7
D5
P8
ADC Section 8
11
D4
Auto-
Zero
CMP
11-Bit
SAR
T/H
Data
Valid
D3
11
D2
DAC
D1
Ref
In
DØ (LSB)
Reference Ladder
V
Ref
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AV .........................................................................+6 V
Output
Digital Outputs .......................................................10 mA
DD
DV
........................................................................+6 V
DD
Input Voltages
Temperature
Analog Input ................................ -0.5 V to AV
+0.5 V
Operating Temperature ................................... 0 to 70 °C
Junction Temperature........................................... 175 °C
Lead Temperature, (soldering 10 seconds) ......... 300 °C
Storage Temperature ...............................-65 to +150 °C
DD
V
........................................................................... 0 to AV
REF
DD
CLK Input .................................................................. V
AV - DV
DD
.............................................................±100 mV
DD
DD
AGND - DGND..................................................±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T =T
A
to T
, AV =DV =OV =+5.0 V, V =0 to 4 V, f
=10 MHz, f =5 MSPS, V = 4.0 V, V =0.0 V, unless otherwise specified.
CLK S RHS RLS
MIN
MAX
DD
DD
DD
IN
TEST
CONDITIONS
TEST
LEVEL
SPT7835
TYP
PARAMETERS
Resolution
MIN
MAX
UNITS
10
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
VI
VI
VI
±1.0
±0.5
Guaranteed
LSB
LSB
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
VI
IV
V
V
V
V
V
RHS
V
kΩ
pF
MHz
LSB
LSB
RLS
50
5.0
100
±2.0
±2.0
(Small Signal)
Gain Error
V
Reference Input
Resistance
Bandwidth
Voltage Range
VI
V
400
100
500
150
600
2.0
Ω
MHz
V
RLS
V
RHS
V
RHS
IV
IV
V
V
V
0
3.0
1.0
-
-
V
V
V
mV
mV
AV
DD
- V
4.0
90
75
5.0
RLS
)
)
∆(V
∆(V
- V
RHF
RLS
RHS
- V
RLF
Reference Settling Time
V
RHS
V
RLS
V
V
15
20
Clock Cycles
Clock Cycles
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
VI
IV
IV
V
5
2
MHz
MHz
Clock Cycles
ns
12
5
Aperture Jitter Time
V
10
ps
Dynamic Performance
Effective Number of Bits
f
=1 MHz
IN
VI
9.2
Bits
SPT7835
SPT
2
2/10/98
ELECTRICAL SPECIFICATIONS
T =T
to T
, AV =DV =OV =+5.0 V, V =0 to 4 V, f
=10 MHz, f =5 MSPS, V = 4.0 V, V =0.0 V, unless otherwise specified.
CLK S RHS RLS
A
MIN
MAX
DD
DD
DD
IN
TEST
CONDITIONS
TEST
LEVEL
SPT7835
TYP
PARAMETERS
MIN
MAX
UNITS
Dynamic Performance
Signal-to-Noise Ratio
(without Harmonics)
f
=1 MHz
VI
VI
54
59
59
63
dB
dB
IN
Harmonic Distortion
=1 MHz
f
IN
Signal-to-Noise and Distortion
(SINAD)
f
=1 MHz
IN
VI
52
57
dB
Spurious Free Dynamic Range
Differential Phase
V
V
V
V
63
TBD
TBD
TBD
dB
Degree
%
Differential Gain
Intermodulation Distortion
dB
Digital Inputs
Logic "1" Voltage
Logic "0" Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
VI
VI
VI
V
2.0
V
V
µA
µA
pF
0.8
+10
+10
-10
-10
5
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
(I =0.5 mA)
(I =1.6 mA)
OL
15 pF load
15 pF load
VI
VI
V
V
V
3.5
V
V
ns
ns
ns
ns
OH
0.4
t
t
10
10
10
22
RISE
FALL
Output Enable to Data Output Delay 20 pF load, T = +25 °C
A
50 pF load over temp.
V
Power Supply Requirements
Voltages
OV
DV
AV
IV
IV
IV
3.0
4.75
4.75
5.0
5.25
5.25
V
V
V
DD
DD
DD
5.0
5.0
Currents
AI
VI
VI
VI
9
6
75
12
10
110
mA
mA
mW
DD
DI
DD
Power Dissipation
f
=1 MHz
IN
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
followingconditions:Allparametershavingmin/
max specifications are guaranteed. The Test
Level column indicates the specific device test-
ing actually performed during production and
Quality Assurance inspection. Any blank sec-
tion in the data column indicates that the speci-
fication is not tested at the specified condition.
I
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
SPT7835
SPT
3
2/10/98
Figure 1A: Timing Diagram 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ANALOG IN
CLOCK IN
(Internal)
INVALID
VALID
1
2
3
4
5
6
7
8
9
10
11
DIGITAL OUT
DATA VALID
Figure 1B: Timing Diagram 2
t
C
t
t
CL
CH
t
CLK
CLOCK
IN
t
OD
DATA
OUTPUT
Data Ø
Data 1
Data 2
t
DAV
t
DAV
DATA
VALID
t
S
Table I - Timing Parameters
DESCRIPTION
Conversion Time
Clock Period
PARAMETERS
MIN
TYP
MAX
UNITS
tc
2*t
ns
ns
%
CLK
t
100
40
CLK
Clock High Duty Cycle
Clock Low Duty Cycle
Output Delay
tCH
50
50
20
60
60
25
tCL
40
%
tOD
15
ns
ns
ns
DAV Pulse Width
Clock to DAV
tDAV
tS
t
CLK
16
21
26
SPT7835
SPT
4
2/10/98
SPECIFICATION DEFINITIONS
APERTURE DELAY
DIFFERENTIAL NONLINEARITY (DNL)
Aperture delay represents the point in time, relative to the
rising edge of the CLOCK input, that the analog input is
sampled.
Error in the width of each code from its theoretical value.
N
(Theoretical = V /2 )
FS
INTEGRAL NONLINEARITY (INL)
APERTURE JITTER
Linearity error refers to the deviation of each individual code
(normalized) from a straight line drawn from -Fs through
+Fs. The deviation is measured from the edge of each
particular code to the true straight line.
The variations in aperture delay for successive samples.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on various
DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes at
these DC levels.
OUTPUT DELAY
Time between the clock's triggering edge and output data
valid.
DIFFERENTIAL PHASE (DP)
SIGNAL-TO-NOISE RATIO (SNR)
A signal consisting of a sine wave superimposed on various
DC levels that is applied to the input. Differential phase is the
maximum variation in the sampled sine wave phases at
these DC levels.
Theratioofthefundamentalsinusoidpowertothetotalnoise
power. Harmonics are excluded.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
Theratioofthefundamentalsinusoidpowertothetotalnoise
and distortion power.
EFFECTIVE NUMBER OF BITS (ENOB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
TOTAL HARMONIC DISTORTION (THD)
SINAD - 1.76
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
N =
6.02
SPURIOUS FREE DYNAMIC RANGE (SFDR)
INPUT BANDWIDTH
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
Small signal (50 mV) bandwidth (3 dB) of analog input stage.
SPT7835
SPT
5
2/10/98
TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
THD vs Input Frequency
80
70
80
70
fs = 5 MSPS
fs = 5 MSPS
60
50
60
50
40
30
40
30
20
20
-1
0
10
-1
0
10
10
10
Input Frequency (MHz)
Input Frequency (MHz)
Total Power Dissipation Vs. Sample Rate
Reference is excluded = 30 mW Typ
SINAD vs Input Frequency
110
80
70
90
70
fs =5 MSPS
60
50
50
30
40
30
20
10
0
5
-1
10
0
10
Input Frequency (MHz)
Sample Rate (CLK/2) MHz
SPT7835
SPT
6
2/10/98
TYPICAL INTERFACE CIRCUIT
ThehighsamplerateisachievedbyusingmultipleSARADC
sections in parallel, each of which samples the input signal in
sequence. Each ADC uses 16 clock cycles to complete a
conversion. The clock cycles are allocated as follows:
Very few external components are required to achieve the
stated device performance. Figure 1 shows the typical inter-
face requirements when using the SPT7835 in normal circuit
operation. The following sections provide descriptions of the
major functions and outline critical performance criteria to
consider for achieving the optimal device performance.
Clock
Operation
1
2
3
4
Reference zero sampling
Auto-zero comparison
Auto-calibratecomparison
Input sample
Figure 1 - Typical Interface Circuit
5-15
16
11-bit SAR conversion
Data transfer
Ref In
(+4 V)
V
V
RHF
D10
RHS
V
V
V
The 16 phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by two clock cycles so that the
analoginputissampledoneveryothercycleoftheinputclock
byexactlyoneADCsection.After16clockperiods,thetiming
cycle repeats. The sample rate for the configuration is one-
half of the clock rate, e.g., for a 10 MHz clock rate, the input
sample rate is 5 MHz. The latency from analog input sample
to the corresponding digital output is 12 clock cycles.
RLS
RLF
Interfacing
Logics
SPT7835
V
IN
IN
V
CAL
D0
EN
CLK
CLK IN
DAV
AV
D
D
DV
DD
AGND DGND*
FB1
FB2
+D5
• Since only eight comparators are used, a huge power
savings is realized.
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators
response to a reference zero.
Enable/Tri-State
(Enable = Active Low)
+A5
+A5
+D5
AGND
DGND
FB3
• The auto-calibrate operation, which calibrates the gain of
theMSBreferenceandtheLSBreference,isalsodonewith
aclosedloopsystem.Multiplesamplesofthegainerrorare
integrated to produce a calibration voltage for each ADC
section.
• Capacitive displacement currents, which can induce sam-
pling error, are minimized since only one comparator
samples the input during a clock cycle.
+
+
10 µF
10 µF
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
+5 V
Analog
+5 V
Analog
RTN
+5 V
Digital
RTN
+5 V
Digital
NOTES: 1) FB3 is to be located as closely to the device as possible.
2) There should be no additional connections to the right of FB1 and FB2.
3) All capacitors are 0.1 µF surface-mount unless otherwise specified.
4) FB1, FB2 and FB3 are 10 µH inductors or ferrite beads.
• Thetotalinputcapacitanceisverylowsincesectionsofthe
converter which are not sampling the signal are isolated
from the input by transmission gates.
POWER SUPPLIES AND GROUNDING
SPT suggests that both the digital and the analog supply
voltages on the SPT7835 be derived from a single analog
supply as shown in figure 1. A separate digital supply should
be used for all interface circuitry. SPT suggests using this
power supply configuration to prevent a possible latch-up
condition on power up.
VOLTAGE REFERENCE
The SPT7835 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. The lower side of the
ladder is typically tied to AGND (0.0 V) but can be run up to
2.0 V with a second reference. The analog input voltage
range will track the total voltage difference measured be-
OPERATING DESCRIPTION
tween the ladder sense lines, V
and V
.
RLS
RHS
The general architecture for the CMOS ADC is shown in the
block diagram. The design contains eight identical succes-
sive approximation ADC sections (all operating in parallel),
a 16-phase clock generator, an 11-bit 8:1 digital output
multiplexer, correction logic, and a voltage reference gen-
erator which provides common reference levels for each
ADC section.
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations. By
using the configuration shown in figure 2, offset and gain
errors of less than ±2 LSB can be obtained.
SPT7835
SPT
7
2/10/98
Figure 2 - Ladder Force/Sense Circuit
Figure 3 - Reference Ladder
+4.0 V
External
Reference
1
AGND
90 mV
R/2
V
+
-
RHS
2
3
V
V
(+3.91 V)
RHF
R
R
RHS
R
R
R
R
R=30 Ω (typ)
All capacitors are 0.01 µF
4
5
N/C
V
RLS
-
+
6
7
V
RLF
V
RLS
(0.075 V)
75 mV
R/2
V
IN
V
(AGND)
RLF
0.0 V
All capacitors are 0.01 µF
Thedriverequirementsfortheanaloginputsareveryminimal
whencomparedtomostotherconvertersduetotheSPT7835's
extremely low input capacitance of only 5 pF and very high
input resistance of 50 kΩ.
In cases where wider variations in offset and gain can be
tolerated, V canbetieddirectlytoV andAGNDcanbe
Ref
RHF
tied directly to V
as shown in figure 3. Decouple force and
RLF
sense lines to AGND with a .01 µF capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 4.
CALIBRATION
The reference ladder circuit shown in figure 3 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
The SPT7835 uses an autocalibration scheme to ensure 10-
bitaccuracyovertimeandtemperature.Gainandoffseterrors
are continually adjusted to 10-bit accuracy during device
operation. This process is completely transparent to the user.
ladder, the voltage drop from V
to V
is not equivalent
RHF
RHS
to the voltage drop from V
to V
.
RLS
RLF
Typically, the top side voltage drop for V
equal:
to V
will
RHS
Upon power-up, the SPT7835 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 10-
bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10k clock cycles are required. This
results in a minimum calibration time upon power-up of
1 msec for a 5 MHz sample rate. Once calibrated, the
SPT7835 remains calibrated over time and temperature.
RHF
V
- V
= 2.25 % of (V
- V
) (typical),
RHF
RHS
RHF
RLF
RLS
and the bottom side voltage drop for V
- V = 1.9 % of (V - V
to V
will equal:
RLF
V
RLS
) (typical).
RLF
RHF
RLF
Figure 3 shows an example of expected voltage drops for a
specific case. V of 4.0 V is applied to V and V is
Ref
RHF
RLF
Since the calibration cycles are initiated on the rising edge of
the clock, the clock must be continuously applied for the
SPT7835 to remain in calibration.
tied to AGND. A 90 mV drop is seen at V
(= 3.91 V) and
RHS
a 75 mV increase is seen at V
(= 0.075 V).
RLS
ANALOG INPUT
INPUT PROTECTION
VIN is the analog input. The input voltage range is from VRLS
to VRHS (typically 4.0 V) and will scale proportionally with
respect to the voltage reference. (See the Voltage Refer-
ence section.)
All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge condi-
tions without degrading analog transition times.
SPT7835
SPT
8
2/10/98
Figure 4 - Recommended Input Protection Circuit
CLOCK INPUT
The SPT7835 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising
edge of the clock input, the device can operate over a wide
range of input clock duty cycles without degrading the dy-
namic performance. The device's sample rate is 1/2 of the
input clock frequency. (See the timing diagram.)
+V
AV
DD
D1
D2
Buffer
ADC
DIGITAL OUTPUTS
47 Ω
The digital outputs (D0-D10) are driven by a separate supply
(OVDD) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7835's TTL/CMOS-compatible out-
puts with the user's logic system supply. The format of the
output data (D0-D9) is straight binary. (See table II.) The
outputs are latched on the rising edge of CLK. These outputs
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
can be switched into a tri-state mode by bringing
high.
EN
Table II - Output Data Information
Figure 5 - On-Chip Protection Circuit
ANALOG INPUT
OVERRANGE
D10
OUTPUT CODE
D9-D0
V
+F.S. + 1/2 LSB
+F.S. -1/2 LSB
+1/2 F.S.
1
1 1 1111 1111
11 1111 111Ø
ØØ ØØØØ ØØØØ
OO OOOO OOOØ
OO OOOO OOOO
DD
O
O
O
O
Analog
120 Ω
120 Ω
+1/2 LSB
0.0 V
(Ø indicates the flickering bit between logic 0 and 1).
Pad
OVERRANGE OUTPUT
The Overrange Output (D10) is an indication that the analog
inputsignalhasexceededthepositivefullscaleinputvoltage
by 1 LSB. When this condition occurs, D10 will switch to
logic 1. All other data outputs (D0 to D9) will remain at logic 1
as long as D10 remains at logic 1. This feature makes it
possibletoincludetheSPT7835intohigherresolutionsystems.
POWER SUPPLY SEQUENCING CONSIDERATIONS
EVALUATION BOARD
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants which could delay
VDD power to the device.
The EB7835 evaluation board is available to aid designers in
demonstrating the full performance of the SPT7835. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7835 is
also available. Contact the factory for price and availability.
SPT7835
SPT
9
2/10/98
PACKAGE OUTLINES
28-Lead Cerdip, 300 mil
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
A
B
C
D
E
F
G
H
I
0.005
0.13
0.200
0.200
0.018
0.100
0.056
15°
5.08
0.125
3.18
0.00
5.08
0.46
2.54
1.42
15°
10°
0°
A
N
0.010
0.317
0.291
0.25
8.05
7.39
0.311
0.285
0.150
0.015
1.440
7.90
7.24
28
J
K
L
3.81
0.060
1.460
0.098
0.38
1.52
37.08
2.49
M
N
36.58
1
M
J
L
B
K
I
C
E
F
D
H
G
28-Lead SOIC
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
B
C
D
E
F
G
H
I
0.696
0.004
0.712
0.012
.050 typ
0.019
0.012
0.100
0.050
0.419
0.299
17.68
0.10
18.08
0.30
1.27 typ
0.48
28
0.014
0.009
0.080
0.016
0.394
0.291
0.36
0.23
2.03
0.41
10.01
7.39
0.30
2.54
I
H
1.27
10.64
7.59
1
A
H
F
B
C
D
G
E
SPT7835
SPT
10
2/10/98
PACKAGE OUTLINES
28-Lead Skinny PDIP
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
A
0.288 TYP
1.386 TYP
0.130 TYP
0.060 TYP
0.100 TYP
0.020 TYP
0.130 TYP
0.310 TYP
0.345 TYP
7.3 TYP
35.2 TYP
3.3 TYP
1.5 TYP
2.5 TYP
0.5 TYP
3.3 TYP
7.9 TYP
8.8 TYP
B
A
C
D
E
F
G
H
I
C
D
B
F
G
E
H
I
32-Lead TQFP
INCHES
MILLIMETERS
MIN MAX
8.90
G
H
A
B
SYMBOL
MIN
MAX
A
B
C
D
E
F
G
H
I
0.347
0.269
0.347
0.269
0.027
0.012
0.053
0.002
0.039 typ
0.004
0°
0.355
0.277
0.355
0.277
0.035
0.018
0.057
0.006
9.10
7.10
9.10
7.10
0.89
0.45
1.45
0.15
6.90
8.90
6.90
0.68
C
D
0.30
1.35
0.05
1.00 typ
0.09
I
J
0.008
7°
0.20
7°
J
K
L
0°
0.018
0.029
0.45
0.75
E
F
K
L
SPT7835
SPT
11
2/10/98
PIN ASSIGNMENTS
PIN FUNCTIONS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
D10
D9
D8
D7
D6
D5
OV
AGND
NAME
FUNCTION
2
V
RHF
AGND
Analog Ground
3
4
V
RHS
N/C
V
Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Analog Input
RHF
5
V
V
RLS
RHS
6
V
RLF
V
V
V
V
RLS
RLF
CAL
IN
Cerdip
PDIP and
SOIC
7
V
IN
DD
AGND
8
OGND
D4
V
9
CAL
10
11
12
13
14
AV
D3
DD
AV
DV
Analog V
DD
DD
DD
DV
DD
D2
Digital V
DD
DGND
CLK
D1
DGND
CLK
Digital Ground
Input Clock f
DØ
EN
=fs (TTL)
DAV
CLK
Output Enable
D0-9
D10
Tri-State Data Output, (DØ=LSB)
Tri-State Output Overrange
Data Valid Output
V
RLF
1
2
3
4
5
6
7
8
24 D7
DAV
V
IN
23 D6
22 D5
21 OV
OV
Digital Output Supply
AGND
AGND
DD
OGND
Digital Output Ground
DD
TQFP
V
CAL
20 OGND
19 D4
AV
DD
AV
DD
18 D3
DV
DD
17 D2
ORDERING INFORMATION
PART NUMBER
SPT7835SCD
SPT7835SCN
SPT7835SCS
SPT7835SCT
SPT7835SCU
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
28L Cerdip (300 mil)
28L Plastic DIP (300 mil)
28L SOIC
0 to +70 °C
0 to +70 °C
0 to +70 °C
32L TQFP
+25 °C
Die*
*Please see the die specification for guaranteed electrical performance.
Covered by Patent Numbers 5262779 and 5272481.
SignalProcessingTechnologies,Inc.reservestherighttochangeproductsandspecificationswithoutnotice.Permissionisherebyexpressly
granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
SPT7835
SPT
12
2/10/98
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