SSI1N50BTU_技术文档

SSW1N50B / SSI1N50B

520V N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for high efficiency switch mode power supplies,

power factor correction and electronic lamp ballasts based

on half bridge.

•

1.5A, 520V, R

= 5.3Ω @V = 10 V

DS(on) GS

Low gate charge ( typical 8.3 nC)

Low Crss ( typical 5.5 pF)

Fast switching

100% avalanche tested

Improved dv/dt capability

D

!

D

●

◀

▲

●

G!

D²-PAK

SSW Series

I²-PAK

SSI Series

G

S

G D S

!

S

Absolute Maximum Ratings

T = 25°C unless otherwise noted

C

Symbol

Parameter

SSW1N50B / SSI1N50B

Units

V

I

Drain-Source Voltage

520

1.5

DSS

- Continuous (T = 25°C)

Drain Current

A

D

C

- Continuous (T = 100°C)

0.97

5.0

A

C

I

(Note 1)

Drain Current

- Pulsed

A

DM

V

E

I

Gate-Source Voltage

± 30

100

V

GSS

AS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

mJ

A

1.5

AR

E

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

3.6

mJ

V/ns

W

AR

dv/dt

5.5

Power Dissipation (T = 25°C) *

3.13

36

P

A

D

Power Dissipation (T = 25°C)

W

C

- Derate above 25°C

Operating and Storage Temperature Range

0.29

-55 to +150

W/°C

°C

T , T

J

stg

Maximum lead temperature for soldering purposes,

T

300

°C

L

1/8" from case for 5 seconds

Thermal Characteristics

Symbol

Parameter

Typ

--

Max

3.44

40

Units

°C/W

R

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient *

Thermal Resistance, Junction-to-Ambient

θJC

θJA

--

62.5

* When mounted on the minimum pad size recommended (PCB Mount)

Rev. C, May 2002

Electrical Characteristics

T = 25°C unless otherwise noted

C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

BV

V

= 0 V, I = 250 µA

GS D

Drain-Source Breakdown Voltage

520

--

V

DSS

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

I

= 250 µA, Referenced to 25°C

0.54

V/°C

D

/

∆T

J

I

V

= 520 V, V = 0 V

--

10

100

-100

µA

nA

DSS

DS

GS

Zero Gate Voltage Drain Current

= 400 V, T = 125°C

DS

GS

C

I

= 30 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

GSSF

DS

I

= -30 V, V = 0 V

GSSR

DS

On Characteristics

V

= V , I = 250 µA

Gate Threshold Voltage

2.0

--

4.0

5.3

--

V

Ω

S

GS(th)

DS

GS

DS

GS

D

R

Static Drain-Source

On-Resistance

DS(on)

= 10 V, I = 0.75 A

4.1

1.8

D

g

= 40 V, I = 0.75 A

(Note4)

Forward Transconductance

--

FS

D

Dynamic Characteristics

C

Input Capacitance

--

260

25

340

33

pF

iss

V

= 25 V, V = 0 V,

GS

DS

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

5.5

7.2

Switching Characteristics

t

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

--

14

40

90

80

11

--

ns

d(on)

V

= 250 V, I = 1.5 A,

DD

D

r

R

= 25 Ω

G

35

ns

d(off)

f

(Note4, 5)

35

ns

Q

8.3

1.5

3.4

nC

g

V

= 400 V, I = 1.5 A,

DS

D

= 10 V

gs

gd

GS

--

Drain-Source Diode Characteristics and Maximum Ratings

I

Maximum Continuous Drain-Source Diode Forward Current

--

1.5

5.0

1.4

--

A

S

I

Maximum Pulsed Drain-Source Diode Forward Current

SM

V

t

V

= 0 V, I = 1.5 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

--

V

SD

GS

S

= 0 V, I = 1.5 A,

230

0.94

ns

µC

rr

GS

S

dI / dt = 100 A/µs

(Note4)

Q

Reverse Recovery Charge

--

F

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 80mH, I = 1.5A, V = 50V, R = 25 Ω, Starting T = 25°C

AS

DD

G

J

3. I ≤ 1.5A, di/dt ≤ 300A/µs, V ≤ BV

Starting T = 25°C

SD

DD

DSS,

J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. C, May 2002

Typical Characteristics

V_GS

Top :

15.0V

10.0 V

8.0 V

7.0 V

6.5 V

6.0 V

5.5 V

10⁰

Bottom: 5.0V

10⁰

150^oC

25^oC

-1

10

-55^oC

※

Notes :

※

Notes :

1. V = 40V

2. 250 s Pulse Test

μ

1. 250 s Pulse Test

^DSμ

℃

2. T_C= 25

-1

10

-2

10

-1

2

4

6

8

10

10⁰

10¹

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

15

12

9

V_GS= 10V

V_GS= 20V

10⁰

℃

150

℃

25

6

※

Notes :

1. V = 0V

^GSμ

2. 250 s Pulse Test

※

℃

Note: T = 25

J

-1

3

10

0

1

2

3

4

5

0.2

0.4

0.6

0.8

1.0

1.2

1.4

I_D, Drain Current [A]

V_SD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation with Source Current

and Temperature

500

400

300

200

100

0

12

10

8

C

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C

gd

V_DS= 100V

V_DS= 250V

C_rss= C_gd

V_DS= 400V

C

iss

6

C

oss

4

※

Notes :

1. V_GS= 0 V

2. f = 1 MHz

C

2

rss

※

Note: I_D= 1.5 A

7.5

0

0.0

-1

10

10⁰

10¹

1.5

3.0

4.5

6.0

9.0

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. C, May 2002

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※Notes :

0.9

1. V_GS= 0 V

※

Notes :

1. V = 10 V

2. I_D= 250 μA

2. I_D^G=^S0.75 A

0.8

-100

-50

0

50

100

150

200

-50

0

50

100

150

200

T_J, Junction Temperature [^oC]

T, Junction Temperature [^oC]

J

Figure 7. Breakdown Voltage Variation

vs Temperature

Figure 8. On-Resistance Variation

vs Temperature

1.8

1.5

1.2

0.9

0.6

0.3

0.0

Operation in This Area

is Limited by R _DS(on)

10¹

100 µs

1 ms

10 ms

10⁰

DC

-1

10

※

Notes :

1. T_C= 25 ^oC

2. T = 150 ^oC

J

3. Single Pulse

-2

10

10¹

10²

10³

0

25

50

75

100

125

150

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs Case Temperature

D = 0 .5

1 0 ⁰

※

N otes

1. Z_θ_JC(t)

2. D uty Factor, D =t₁/t₂

3. T_JMT_CP _{D M}Z_θ_JC(t)

:

℃

/W M ax.

=

3.44

0 .2

-

=

*

0 .1

0 .0 5

P_DM

0 .0 2

1 0 ^-1

0 .0 1

t₁

sin g le p u lse

t₂

1 0^-5

1 0^-4

1 0^-3

1 0^-2

1 0^-1

1 0⁰

1 0¹

t₁, S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11. Transient Thermal Response Curve

Rev. C, May 2002

Gate Charge Test Circuit & Waveform

V_GS

Same Type

50Kꢀ

as DUT

Q_g

12V

200nF

10V

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

10V

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

L

1

2

----

E_AS

=

L I_AS

V_DS

I _D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V_DD

V_DS(t)

DUT

10V

t _p

Time

Rev. C, May 2002

Peak Diode Recovery dv/dt Test Circuit & Waveforms

+

DUT

V_DS

_

I _SD

L

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. C, May 2002

Package Dimensions

D²-PAK

4.50 ±0.20

9.90 ±0.20

+0.10

–0.05

1.30

0.10 ±0.15

2.40 ±0.20

0.80 ±0.10

1.27 ±0.10

+0.10

0.50

–0.05

2.54 TYP

10.00 ±0.20

(8.00)

(4.40)

10.00 ±0.20

(2XR0.45)

0.80 ±0.10

Dimensions in Millimeters

Rev. C, May 2002

Package Dimensions (Continued)

I²-PAK

4.50 ±0.20

9.90 ±0.20

+0.10

–0.05

1.30

1.27 ±0.10

1.47 ±0.10

0.80 ±0.10

+0.10

–0.05

0.50

2.40 ±0.20

2.54 TYP

10.00 ±0.20

Dimensions in Millimeters

Rev. C, May 2002

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarksꢀ

ACEx

PACMAN

POP

Power247

PowerTrench

QFET

QS

SPM

Stealth

SuperSOT-3

SuperSOT-6

SuperSOT-8

ImpliedDisconnect

ISOPLANAR

LittleFET

MicroFET

MicroPak

MICROWIRE

MSX

FACT

ActiveArray

Bottomless

CoolFET

CROSSVOLT

DOME

EcoSPARK

E²CMOS^TM

EnSigna^TM

FACT Quiet Series

â

FAST

â

FASTr

FRFET

GlobalOptoisolator

GTO

HiSeC

I²C

SyncFET

â

QT Optoelectronics TinyLogic

Quiet Series

RapidConfigure

RapidConnect

TruTranslation

UHC

UltraFET

MSXPro

OCX

â

OCXPro

OPTOLOGIC

Across the boardꢀAround the worldꢀ

The Power Franchise

ProgrammableActive Droop

â

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGNꢀ FAIRCHILD

DOES NOTASSUMEANY LIABILITYARISING OUT OF THEAPPLICATION OR USE OFANY PRODUCT

OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT

RIGHTS, NOR THE RIGHTS OF OTHERSꢀ

LIFE SUPPORT POLICY

FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUTTHE EXPRESS WRITTENAPPROVALOF FAIRCHILD SEMICONDUCTOR CORPORATIONꢀ

As used herein:

1ꢀ Life support devices or systems are devices or

systems which, (a) are intended for surgical implant into

the body, or (b) support or sustain life, or (c) whose

failure to perform when properly used in accordance

with instructions for use provided in the labeling, can be

reasonably expected to result in significant injury to the

userꢀ

2ꢀ A critical component is any component of a life

support device or system whose failure to perform can

be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or

effectivenessꢀ

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or

In Design

This datasheet contains the design specifications for

product developmentꢀ Specifications may change in

any manner without noticeꢀ

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later dateꢀ

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

designꢀ

No Identification Needed

Obsolete

Full Production

This datasheet contains final specificationsꢀ Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve designꢀ

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductorꢀ

The datasheet is printed for reference information onlyꢀ

Revꢀ I2


型号：	SSI1N50BTU
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET, PSIP-3 晶体晶体管功率场效应晶体管开关脉冲
文件：	总9页 (文件大小：600K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SSI1N50BTU [FAIRCHILD]

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