TDC1016J7AX [FAIRCHILD]
Video Speed D/A Converter 10-Bit, 20 Msps; 视频高速D / A转换器，10位， 20 Msps的
| 型号： | TDC1016J7AX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Video Speed D/A Converter 10-Bit, 20 Msps |
| 文件： | 总12页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TDC1 0 1 6
Vid e o S p e e d D/A Co n ve rt e r
1 0 -Bit , 2 0 Ms p s
Features
Description
• 20 Msps conversion rate
• 8, 9, or 10-bit linearity
The TDC1016 is a bipolar monolithic digital-to-analog
converter which can convert digital data into an analog volt-
age at rates up to 20 Msps (Megasamples Per Second). The
device includes an input data register and operates without
an external deglitcher or amplifier.
• Voltage output, no amplifier required
• Single supply operation (-5.2V, ECL compatible)
• Dual supply operation (±5.0V, TTL compatible)
• Internal 10-bit latched data register
• Low glitch energy
• Disabling controls, forcing full-scale, zero, and inverting
input data
• Binary or two’s complement input data formats
• Differential gain = 1.5%, differential phase = 1.0°
Operating the TDC1016 from a single -5.2V power supply
will bias the digital inputs for ECL levels, while operating
from a dual ±5V power supply will bias the digital inputs for
TTL levels.
All versions of the TDC1016 are 10-bit digital-to-analog
converters, but are available with linearity specifications of
either 8, 9, or 10 bits. The TDC1016 is patented under U.S.
patent number 3283120 with other patents pending.
Applications
• Construction of video signals from digital data 3x or 4x
NTSC or PAL color subcarrier frequency
• CRT graphics displays, RGB, Raster, Vector
• Waveform synthesis
Block Diagram
10 TTL INPUTS
(20 ECL INPUTS)
TTL/ECL
DIGITAL
INPUT
DATA
LATCHED
CURRENT
SWITCHES
R–2R
RESISTOR
NETWORK
CLK
A
OUT
(CLK)
10
10
10
BUFFERS
NDIS
V
CLK
REF
(NDIS)
NFL
NFH
N2C
V
A
REF
65-1016-01
COMP
Rev. 1.0.0
TDC1016
PRODUCT SPECIFICATION
The internal operational amplifier of the TDC1016 is fre-
quency stabilized by an external 1 mF tantalum capacitor
Functional Description
connected between the COMP pin and V . A minimum of
EE
1 mF is adequate for most applications, but 10 microfarads or
more is recommended for optimum performance. The nega-
General Information
TTL/ECL buffers are used for all digital inputs to the
TDC1016. Logic family compatibility depends upon the
connection of power supplies. When single power supply
(-5.2V) operation is employed, all data, clock, and disable
inputs are compatible with differential ECL logic levels. All
digital inputs become compatible with TTL levels when dual
power supply (±5.0V) operation is used.
tive side of this capacitor should be connected to V
.
EE
Controls
The NDIS inputs are used to disable the TDC1016 by
forcing its output to the zero-scale value (current sources
off). The NDIS inputs are asynchronous, active without
regard to the CLK inputs. The other digital control inputs are
synchronous, latched on the rising edge of the CLK pulse.
The internal 10-bit register latches data on the rising edge of
the clock (CLK) pulse. Currents from the current sources are
switched accordingly and combined in the resistor network
to give an analog output voltage. The magnitude of the out-
put voltage is directly proportional to the magnitude of the
digital input word.
The rising edge of the CLK pulse transfers data from the
input lines to the internal 10-bit register. In TTL mode, the
inverted inputs for CLK, DATA, and NDIS are inactive and
should be left open.
The NFL and NFH inputs can be used to simplify system
calibration by forcing the analog output voltage to either its
zero-scale or full-scale value. The TDC1016 can be operated
in binary, inverse binary, two’s complement or inverse two’s
complement input data formats.
The Input Coding Table illustrates the function of the digital
control inputs. A two’s complement mode is created by acti-
vating N2C with a Logic 0 When NFH and NFL are both
activated with a Logic 0 the input data to the 10-bit register is
inverted.
Power
Data Inputs
The TDC1016 can be operated from a single -5.2V power
Data inputs are ECL compatible when single power supply
operation is employed. The J5 and C2 packages allow for
differential ECL inputs while the J7 and B7 packages have
only single-ended inputs. When differential ECL data is
used, any data input can be inverted simply by reversing the
connections to the true and inverted data input pins. All
inverted input pins should be left open if single-ended ECL
or TTL modes are used. All data inputs have an internal
supply or from a dual ±5.0V power supply. For single power
supply operation, V is connected to D
CC GND
and all inputs
to the device become ECL compatible. When V is tied to
CC
+5.0V, the inputs are TTL compatible.
The return path for the output from the 10 current sources is
A . The current return path for the digital section is
GND
D
. D
and A should be returned to system
GND
GND GND
40 KW pullup resistor to V
.
power supply ground by way of separate conductive paths to
prevent digital ground noise from disturbing the analog cir-
CC
Analog Output
cuitry of the TDC1016. All A
system analog ground.
pins must be connected to
GND
The analog output voltage is negative with respect to A
GND
and varies proportionally with the magnitude of the input
data word. The output resistance at this point is 80W,
nominally.
Reference
The reference input is normally set to -1.0V with respect to
A
. Adjusting this voltage is equivalent to adjusting sys-
GND
tem gain The temperature stability of the TDC1016 analog
output (A ) depends primarily upon the temperature sta-
No Connects
OUT
There are several pins labeled no connect (NC) on the
TDC1016 J5 and C2 packages, which have no connections
to the chip. These pins should be left open.
bility of the applied reference voltage
2
PRODUCT SPECIFICATION
TDC1016
Pin Assignments
40 Lead Ceramic DIP
NC
1
2
3
4
5
6
7
8
9
10
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
NC
V
EE
COMP
V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
(LSB)
(LSB)
REF
10
10
9
A
A
GND
GND
A
OUT
GND
9
24 Lead Ceramic DIP
A
D
8
V
CC
8
V
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
14
13
COMP
REF
GND
7
A
A
V
EE
GND
GND
NDIS 11
CLK 12
CLK 13
NDIS 14
7
D
D
D
D
D
D
D
D
(LSB)
10
9
6
A
OUT
GND
6
A
D
8
5
V
CC
GND
7
(MSB) D
(MSB) D
15
16
1
1
5
6
4
NDIS
CLK
5
N2C 17
4
4
D
D
18
19
2
3
(MSB) D
1
3
2
3
N2C 11
NFL
NFH
NFH 20
NFL
D
2
12
65-1016-02
Pin Descriptions
Pin Number
Pin Name
Power
40-Lead
24-Lead
Value
Pin Function Description
V
V
A
9
2
6
23
+5.0V
-5.0V
0.0V
Positive Supply Voltage.
Negative Supply Voltage.
Analog Ground.
CC
EE
5, 6, 8
10
2, 3, 5
7
GND
D
0.0V
Digital Ground.
GND
Reference
V
4
3
1
-1.0V
Reference Voltage In.
Compensation.
REF
COMP
Controls
NDIS
24
1mF
11
14
12
13
17
20
21
8
TTL/ECL
ECL
Not Disable.
NDIS
—
9
Not Disable (Inv).
Clock.
CLK
TTL/ECL
ECL
CLK
—
11
13
14
Clock (Inv).
N2C
TTL/ECL
TTL/ECL
TTL/ECL
Not Two’s Complement.
Not Force HIGH.
Not Force LOW.
NFH
NFL
Data Inputs
D –D
1 10
16, 19, 23, 25, 10, 12, 15–20,
TTL/ECL
Data Bits 1–10. D is the MSB, D is the LSB.
10
1
27, 29, 31, 33,
35, 37
27, 22
3
TDC1016
PRODUCT SPECIFICATION
Pin Descriptions (continued)
Pin Number
Pin Name
D –D
40-Lead
24-Lead
Value
Pin Function Description
15, 18, 22, 24,
26, 28, 30, 32,
34, 36
—
ECL
Data Bits 1–10 (Inv). D is the MSB, D is the
1 10
LSB.
1
10
Analog Output
A
7
4
0V–1V
Open
Analog Output Voltage
No Connection
OUT
No Connection
NC
1, 38–40
—
Absolute Maximum Ratings (beyond which the device wille be damaged)1
Parameter
Min.
Max.
Unit
Supply Voltages
V
V
(measured to D
)
-0.5
-7.0
-0.5
+7.0
+0.5
+0.5
V
V
V
CC
EE
GND
(measured to A
)
GND
AG
ND
(measured to D
)
GND
Input Voltages
Digital (measured to D
)
-7.0
-1.5
+7.0
+0.5
V
V
GND
Reference (measured to A
)
GND
Output
2
Applied Voltage (measured to A
Short-Circuit Duration
Temperature
)
-2.0
+2.0
V
GND
Indefinite
Operating, Ambient
Operating, Junction
Lead, Soldering (10 seconds)
Storage
+125
+175
+300
+150
°C
°C
°C
°C
-65
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range.
4
PRODUCT SPECIFICATION
TDC1016
Operating Conditions
Temperature Range
Standard Extended
Min. Nom. Max. Min. Nom. Max.
Symbol Parameter
Unit
V
V
CC
Positive Supply Voltage
TTL Mode 4.75
ECL Mode -0.25
-4.5
5.0
0.0
-5.0
0.0
5.25
4.50
5.0
0.0
-5.0
0.0
5.50
0.25
-5.5
0.1
0.25 -0.25
V
V
V
Negative Supply Voltage
-5.5
0.1
-4.5
-0.1
V
EE
Analog Ground Voltage (Measured to
-0.1
V
AGND
D
GND
)
t
t
t
CLK Pulse Width, LOW
CLK Pulse Width, HIGH
Input Register Set-up Time
15
15
20
25
2
20
20
22
27
2
ns
ns
ns
ns
ns
V
PWL
PWH
S
TTL Mode
ECL Mode
t
Input Register Hold Time
Logic 0
H
V
V
V
TTL Mode
ECL Mode
TTL Mode
ECL Mode
D
0.8
D
0.8
IL
GND
GND
-1.67
-1.67
V
Logic 1
2.0
-1.0
-0.8
1.0
0
V
CC
2.01
-1.0
-0.8
1.0
V
V
IH
CC
V
Reference Voltage
-1.0
-1.2
70
-1.0
1.2
V
REF
C
Compensation Capacitor
Ambient Temperature
Case Temperature
mF
°C
°C
COMP
T
T
A
C
-55
125
Note:
1. V /NDIS = 2.2 Min.
IH
DC Electrical Characteristics
Temperature Range
Standard Extended
Min. Max. Min. Max. Unit
Symbol Parameter
Test Conditions
I
I
I
I
Power Supply Current
Power Supply Current
Reference Input Current
Logic 0 Input Current
TTL Mode, V
TTL Mode, V
= Max, V = Max
EE
20
-130
10
20
-150 mA
10 mA
mA
CC
EE
REF
IL
CC
CC
= Max, V = Max1
EE
VEE = Max, VREF = -10V
TTL Mode, V = Max, V = Max
-1.0
-300
75
-1.0 mA
CC
EE
ECL Mode, V
= 0.0, V = Max
EE
-300 mA
CC
CC
I
IH
Logic 1 Input Current
Output Capacitance
TTL Mode, V
ECL Mode, V
= Max, V = Max
EE
75
350
10
mA
mA
pF
pF
W
= 0.0, V = Max
EE
350
10
CC
C
C
R
A to A
OUT GND
(Figure 2)
OUT
Digital Input Capacitance Any Digital Input to D
GND
35
35
IN
Output Resistance
A to A
OUT GND
(Figure 2)
70
95
70
95
OUT
Note:
1. Return current from V flows through AGND.
EE
5
TDC1016
PRODUCT SPECIFICATION
AC Electrical Characteristics
Temperature Range
Standard Extended
Min. Max. Min. Max. Unit
Symbol Parameter
Test Conditions
F
Maximum Data Rate
TTL Mode Full-Scale Output Step
ECL Mode Full-Scale Output Step
RL = 75 Ohms
20
20
MSPS
MSPS
ns
C
17.8
17.8
t
t
Data Turn on Delay
Settling Time
30
30
35
40
5.5
30
30
35
40
5.5
DS
TDC1016-8 to 0.2%
ns
SET
TDC1016-9 to 0.1%
ns
TDC1016-10 to .05%
ns
t
Output 10% to 90%
Risetime
V
EE
= Nom., RL = 75W,
ns
RV
Full-Scale Step
Timing Diagram
tS
tH
DATA
CONTROLS
CLOCK
tPWL
tPWH
1CLOCK
±1/2 LSB
±1/2 LSB
OUTPUT
tDS
tSET
NOTE: 1. Differential ECL mode only
65-1016-06
Figure 1. Timing Diagram
System Performance Characteristics
Temperature Range
Standard Extended
Min. Max. Min. Max.
Parameter
Test Conditions
Unit
Bits
RES
Resolution
All TDC1016 Devices
TDC1016-8
10
0.2
10
0.2
0.1
ELI, ELD Linearity Error Integral and
Differential, Independent
Based
% FS
% FS
% FS
V
TDC1016-9
0.1
TDC1016-10
0.075
V
Full-Scale Output Voltage
Zero-Scale Output Voltage
V
V
= Nom, RL ³ 10kW,
-0.95 -1.05 -0.95 -1.05
OFS
OZS
EE
= -1.000V
REF
V
V
V
= Nom, RL ³ 10 kW,
±15
±15
mV
EE
= -1.000V
REF
DP
DG
Differential Phase
Differential Gain
Glitch Energy (Area)
Glitch Voltage
NTSC 4x Subcarrier1
NTSC 4x subcarrier1
RL = 50W, Midscale
RL = 50W, Midscale
1.0
1.5
125
35
1.0
1.5
125
35
Degrees
%
GE
pV-sec
mV
GV
Note:
1. In excess of theoretical DP and DG due to quantizing error.
6
PRODUCT SPECIFICATION
TDC1016
Equivalent Circuits
A
A
GND
R
80½
OUT
C
OUT
1
OUT
INPUT DATA DEPENDENT
CURRENT SINK
V
EE
NOTE: 1. 75½ requires outside trim
65-1016-03
Figure 2. Analog Output Equivalent Circuit, TTL and ECL Mode
VCC
(+5.0V)
VCC
(+5.0V)
40K
50K
40K
50K
35K
DGND
6.7K
13K
37K
DATA
DATA
DATA
I = 0
I = 75µA
DGND
VEE
VEE
65-1016-04
Figure 3. Digital Input Equivalent Circuit, TTL Mode
Figure 4. Digital Input Equivalent Circuit, ECL Mode
7
TDC1016
PRODUCT SPECIFICATION
Input Coding Table
NDIS
N2C
NFH
NFL
Data
Output
Description
0
x
x
x
xxxxxxxxxx
0.0
Output Disabled
1
1
1
1
1
1
1
1
1111111111
0000000000
0.0
-1.0
Binary (Default State for TTL Mode
Control) Inputs Open
1
1
1
1
0
0
0
0
1111111111
0000000000
-1.0
0.0
Inverse Binary
1
1
0
0
1
1
1
1
0111111111
1000000000
0.0
-1.0
Two’s Complement
Inverse Two’s Complement
1
1
0
0
0
0
0
0
0111111111
1000000000
-1.0
0.0
1
1
x
x
0
1
1
0
xxxxxxxxxx
xxxxxxxxxx
0.0
-1.0
Force HIGH
Force LOW
Notes:
1. For TTL, 0.0 < V < +0.8V is Logic 0.
IL
2. For TTL, +2.0 < V < +5.0V is Logic 1.
IH
3. For ECL, -1.85 < V < -1.67V is Logic 0.
IL
4. For ECL, -1.0 < V < -0.8V is Logic 1.
IH
5. x = don’t care.
The TDC1016 output and currents from the SYNC and
BLANKING inputs are summed and amplified by the
HA2539 wide-band operational amplifier. Note the careful
power supply decoupling at the power input pins of the
amplifier. The output of the circuit is a composite video sig-
nal with SYNC and BLANKING levels coming from exter-
nal sources. This technique allows the TDC1016 to use its
entire dynamic range for the video information while pulses
are added by other means.
Applications Discussion
Calibration
The TDC1016 is calibrated by adjusting the voltage refer-
ence to give the desired full-scale output voltage. The current
switches can be turned on either by loading the data register
with full-scale data or by bringing the NFH input to a logic
zero. Note that all 10 current switches are activated by the
NFH input and the resulting full-scale output voltage will be
greater than if the system used only eight or nine bits for
full-scale data.
The reference for the TDC1016 is generated by dividing the
output voltage from a two-terminal band-gap voltage refer-
ence. System gain is calibrated by adjusting variable resistor
R1. Analog and digital grounds should be routed back to sys-
tem power supply ground by separate paths.
Typical Application
The Typical Interface Circuit (Figure 5) shows the TDC1016
in a typical application, reconstructing video signals from
digital data. Television timing signals, SYNC and
BLANKING, are added by injecting current from the Wilson
current source into a resistor divider circuit at the output of
the TDC1016.
8
PRODUCT SPECIFICATION
TDC1016
+12V
+
+5V
C4
R15
R16 R22
R14
Q4
C1
CLOCK
U4
U4
SYNC
12
9
10
R17
R18
R20
Q2
Q1
CLK
D1 MSB
V
D
Q3
CC
GND
16
19
23
25
27
29
31
33
35
37
R4
D2
Q5
D3
BLANKING
D4
R21
7
TTL DATA
INPUTS
U1
D5
+5V
A
OUT
TDC1016
D6
C6
CR1
+12V
D7
R4
D8
D9
R6
R7
+5V
D10 LSB
CC
R12
R8
V
COMP
3
+
V
A
C9
L1
REF GND
+
4
2
5,6,8
C7
10
C2
R11
14
1
–
C3
COMPOSITE
VIDEO
OUT
8
R1 GAIN
U3
+
R2
OFFSET
R10
R9
3
R13
R3
C5
U2
L2
C8
C10
-5V
R12
65-1016-05
-12V
Figure 5. Typical Interface Circuit
Capacitors
Table 1. Bill of Materials
Resistors
Diodes
R1
5K
1K
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
10-turn
10-tum
5%
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
0.01mF
1.0mF
1.0mF
2.2mF
0.1mF
2–5pF
0.1mF
0.1mF
0.1mF
0.1mF
50V
CR1
1N4001
R2
10V
10V
25V
50V
50V
50V
50V
50V
50V
R3
1K
Transistors
R4
43
5%
Q1
Q2
Q3
Q4
Q5
2N2907
2N2907
2N2907
2N6660
2N6660
R5
33
5%
R6
330
750
10
5%
R7
5%
R8, R9
R10
5%
75
2%
R11, R12
R13
10K
220
100
390
2K
5%
Integrated Circuits
5%
U1
U2
U3
U4
TDC1016
R14, R15
R16, R22
R17, R18
R19
5%
RF Chokes
LM113
HA2539
SN7404
5%
L1, L2
Ferrite Beads
10-turn
5%
1K
R20, R21
1K
5%
9
TDC1016
PRODUCT SPECIFICATION
Mechanical Dimensions
40 Lead Sidebrazed Ceramic DIP
Notes:
Inches
Millimeters
Symbol
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
Min.
Max.
Min.
Max.
A
.120
.014
.040
.008
1.970
.575
.175
.023
.065
3.05
.360
4.44
.580
1.65
7
2
7
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 20, 21, and 40 only.
b1
b2
c1
D
1.02
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
.200
.015
2.030
.610
.380
51.56
15.49
50.04
14.60
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 40.
E
.100 BSC
.600 BSC
2.54 BSC
15.24 BSC
e
4, 8
6
eA
5. Applies to all four corners (leads number 1, 20, 21, and 40).
6. "eA" shall be measured at the centerline of the leads.
.125
.200
.060
—
3.18
5.08
1.52
—
L
Q
3
5
.025
.005
.005
.63
.13
.13
7. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat when lead finish is applied.
S1
S2
—
—
8. Thirty-eight spaces.
D
Note 1
1
20
E
21
40
S1
eA
S2
A
Q
L
b2
c1
e
b1
10
PRODUCT SPECIFICATION
TDC1016
Mechanical Dimensions (continued)
24 Lead Sidebrazed Ceramic DIP
Notes:
Inches
Millimeters
Symbol
Notes
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
Min.
Max.
Min.
Max.
A
.120
.014
.040
.008
1.180
.575
.175
.023
.065
3.05
.360
4.44
.580
1.65
7
2
7
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 12, 13, and 24 only.
b1
b2
c1
D
1.02
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
.200
.015
1.220
.610
.380
30.99
15.49
29.97
14.60
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 24.
E
.100 BSC
.600 BSC
2.54 BSC
15.24 BSC
e
4, 8
7
eA
5. Applies to all four corners (leads number 1, 12, 13, and 24).
6. "eA" shall be measured at the centerline of the leads.
.125
.200
.060
—
3.18
5.08
1.52
—
L
Q
3
5
.025
.005
.005
.630
.13
7. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat when lead finish is applied.
S1
S2
—
.13
—
8. Twenty-two spaces.
D
Note 1
12
1
E
13
24
S1
eA
S2
A
Q
L
b2
c1
e
b1
11
TDC1016
PRODUCT SPECIFICATION
Ordering Information
Product Number Temperature Range
Screening
Commercial
Package
Package Marking
1016J5CX
TDC1016J5CX
TDC1016J5AX
TDC1016J7CX
TDC1016J7AX
STD – T = 0°C to 70°C
40 Pin Ceramic
40 Pin Ceramic
24 Pin Ceramic
24 Pin Ceramic
A
EXT – T = -55°C to 125°C
High Reliability
Commercial
1016J5AX
C
STD – T = 0°C to 70°C
1016J7CX
A
EXT – T = -55°C to 125°C
High Reliability
1016J7AX
C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock#DS90001016
Ó 1998 Fairchild Semiconductor Corporation
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