TMC1175AN2B20 [FAIRCHILD]
ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, CMOS, PDIP24, DIP-24;
| 型号： | TMC1175AN2B20 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, CMOS, PDIP24, DIP-24 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TMC1175A
Video A/D Converter
8 bit, 40 Msps
Features
Description
• 8-Bit resolution
• 40 Msps conversion rate
The TMC1175A analog-to-digital (A/D) converter employs
a two-step flash architecture to convert analog signals into
8-bit digital words at sample rates of up to 40 Msps
(Megasamples per second). An integral Track/Hold circuit
delivers excellent performance on signals with full-scale fre-
quency components up to 12 MHz. Innovative architecture
and submicron CMOS technology limit typical power dissi-
pation to 100 mW.
• Low power: 100mW at 20 Msps
• Integral track/hold
• Integral and differential linearity error 0.5 LSB
• Single or dual +5 Volt supplies
• Differential phase 0.5 degree
• Differential gain 1.5%
• Three-state TTL/CMOS-compatible outputs
• Low cost
Power may be derived from either single or dual +5V
supplies. Internal voltage reference resistors allow self-bias
operation. Input capacitance is very low, simplifying or
eliminating input driving amplifiers. All digital three-state
outputs are TTL- and CMOS-compatible.
Applications
• Video digitizing
• VGA and CCD digitizing
• LCD projection panels
• Image scanners
• Personal computer video boards
• Multimedia systems
The TMC1175A is available in 24-lead plastic SOIC, and
28-lead J-lead PLCC packages. Performance specifications
are guaranteed from -20°C to 75°C.
• Low cost, high speed data conversion
Block Diagram
Coarse
Quantizer
Track/
Hold
V
IN
VR+
Digital
Error-
Corrector
R
Reference
Matrix
T
D
7-0
R
B
VR–
Fine
Quantizer
OE
CONV
24453A
REV. 1.3.3 2/28/02
TMC1175A
PRODUCT SPECIFICATION
V
Functional Description
DDA
The TMC1175A 8-bit A/D converter uses a two-step archi-
tecture to perform analog-to-digital conversion at rates up to
40 Msps. The input signal is held in an integral track/hold
stage during the conversion process. Operation is pipelined,
with one input sample taken and one output word provided
for each CONVert cycle.
R+
324Ω
VR+
+2.6V
R
T
The first step in the conversion process is a coarse 4-bit
quantization. This determines the range of the subsequent
fine 4-bit quantization step. To eliminate spurious codes, the
fine 4-bit A/D quantizer output is gray-coded and converted
to binary before it is combined with the coarse result to form
a complete 8-bit result.
RREF
270Ω
R
B
+0.6V
VR–
Analog Input and Voltage References
The TMC1175A converts analog signals in the range R to
R–
81Ω
B
R into digital data. Input signals outside that range produce
T
“saturated” 00h or FFh output codes. The device will not be
27010A
damaged by signals within the range A
GND
to V .
DDA
Input voltage range is very flexible and extends from the +5
Volt power supply to ground. Performance is specified over
the optimom 2 volt input range: 0.6V to 2.6V. However, the
part will function with a full-scale range from 1.0V to 5.0V.
A reduced input range may simplify analog signal condition-
ing circuitry, at the expense of additional noise sensitivity
and reduced differential linearity. Increasing the range can
improve differential linearity, but imposes a greater burden
on the input signal conditioning circuitry.
Figure 1. Reference Resistors
at 5.0V, connecting VR+ to R and grounding
With V
DDA
T
R
will provide an input range from 0.0V to 2.27V, while
B
connecting R to V
DDA
and R to VR- produces a full scale
B
T
range of 3.85V referenced to V . External resistors may
DDA
also be employed to provide arbitrary reference voltages, but
they will not match the temperature coefficient of the on-
chip resistors as well as R+ and R-, and will cause the con-
verter transfer function to vary with temperature.
In many applications, external voltage reference sources are
connected to the R and R pins. R can be grounded. Gain
and offset errors are directly related to the accuracy and sta-
bility of the applied reference voltages.
T
B
B
With this implementation, errors in the power supply voltage
end up on the conversion data output.
Because a two-step conversion process is employed, it is
important that the references remain stable during the
ENTIRE conversion process (two clock cycles). The refer-
ence voltage can then be changed, but any conversion in
progress during a reference change is invalid.
Two reference pull-up and pull-down resistors connected to
VR+ and VR– are provided internally for operation without
external voltage reference circuitry (Figure 1). The reference
voltages applied to R and R may be generated by connect-
T
B
ing VR+ to R and VR- to R . The power supply voltage is
T
B
divided by the on-chip resistors to bias the R and R points.
T
B
This sets-up the converter for operation in its nominal range
from 0.6V to 2.6V.
2
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
remain valid for t
(Output Hold Time), satisfying any
hold time requirement of the receiving circuit. The new data
Table 1. Output Coding
Input Voltage
HO
Output
FF
become valid t
of CONV.
(Output Delay Time) after this rising edge
DO
R + 1 LSB
T
R
FF
T
The outputs of the TMC1175A are CMOS- and TTL-com-
patible, and are capable of driving four low-power Schottky
TTL (54/74LS) loads. An Output Enable control, OE, places
the outputs in a high-impedance state when HIGH. The out-
puts are enabled when OE is LOW.
R – 1 LSB
FE
T
• • •
• • •
80
R + 128 LSB
B
R + 127 LSB
B
7F
Power and Ground
To minimize noise injection into the analog section, V
DDA
• • •
• • •
01
R + 1 LSB
B
may be connected to a separate regulated +5 volt supply.
may be connected to a digital supply. Power up
R
00
B
V
DDD
sequence is immaterial. Latch-up will not occur.
R – 1 LSB
00
B
Note:
1. LSB = (R – R ) / 255
A
and D pins should be connected to a common
GND
GND
T
B
ground plane. For optimum performance treat analog and
digital PWB traces as transmission lines. Route analog
connections cleanly to the TMC1175A. Segregate digital
connections and if necessary terminate clocks to eliminate
ringing. Prevent digital returm currents from flowing across
analog input sections of the TMC1175A.
Digital Inputs and Outputs
Sampling of the applied input signal takes place on the fall-
ing edge of the CONV signal (Figure 2). The output word is
delayed by 2 1/2 CONV cycles. It is then available after the
rising edge of CONV. The previous data on the output
t
STO
Sample N+3
Sample N
Sample N+2
V
IN
Sample N+1
t
PWH
1/f
S
t
PWL
CONV
t
DO
t
HO
D
ORP
ORN
7-0
Hi-Z
Data N–3
Data N–2
Data N–1
Data N
t
t
ENA
DIS
OE
24455A
Figure 2. Conversion Timing
REV. 1.3.3 2/28/02
3
TMC1175A
PRODUCT SPECIFICATION
V(1)
V(2)
V(3)
V(4)
Analog input
External Clock
S (1) C (1) S (2) C (2) S (3) C (3) S (4) C (4)
Upper comparators block
Upper data
MD (0)
MD (1)
MD (2)
MD (3)
Lower reference voltage
RV (0)
RV (1)
RV (2)
RV (3)
C (3)
Lower comparators A block
Lower data A
S (1)
H (1)
C (1) S (3)
H (3)
LD (-1)
LD (1)
H (0)
C (0) S (2)
H (2)
C (2) S (4)
H (94)
LD(2)
Lower comparators B block
Lower data B
LD(-2)
LD(0)
Out(-2)
Out(-1)
Out(0)
Out(1)
Digital output
65-7568
Figure 3. Internal Timing
Pin Assignments
OE
1
2
24
23
D
R
GND
D
GND
B
D
D
D
D
D
D
D
D
3
22 VR–
0
1
2
3
4
5
6
7
18
17
16
15
V
V
V
VR– 26
4
21
20
19
18
17
A
A
V
V
DDA
DDA
DDD
GND
GND
IN
R
27
28
1
5
B
D
6
GND
N/C
N/C
7
DDA
14 CONV
OE
2
8
R
T
V
DDD
13
12
D
3
9
16 VR+
GND
D
D
0
4
7
10
11
15
14
13
V
V
V
DDA
DDA
DDD
V
DDD
CONV 12
M7 Package
R3 Package
24454A
4
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
Pin Descriptions
Pin Number
M7 R3
Pin Name
Inputs
Pin Type Pin Function Description
V
19
17
23
20
R – R
Analog Input. The input voltage conversion range lies between the
voltages applied to the RT and RB pins.
IN
T
B
R
2.6V
0.6V
Reference Voltage Top Input. R is the top input to the reference
T
T
B
resistor ladder. A DC voltage applied to R defines the positive end
T
of the V conversion range.
IN
R
23
27
Reference Voltage Bottom Input. R is the bottom input to the
B
reference resistor ladder. A DC voltage applied to R defines the
B
negative end of the V conversion range.
IN
VR+
16
22
1
19
26
2
Reference Voltage Top Source. VR+ is the internal pull-up
reference resistor for self-bias operations.
VR–
Reference Voltage Bottom Source. VR- is the internal pull-down
reference resistor for self-bias operations.
OE
CMOS Output Enable. (CMOS-compatible) When LOW, D are enabled.
7-0
When HIGH, D
are in a high-impedance state.
7-0
CONV
12
14
CMOS Convert (Clock) Input. (CMOS-compatible) V is sampled on the
IN
falling edge of CONV.
Outputs
D
7-0
10–3
12–9,
7–4
CMOS/ Data Outputs (D7 = MSB). Eight-bit CMOS- and TTL-compatible
TTL
digital outputs. Data is output following the rising edge of CONV.
Power
V
V
A
14, 15, 18 17, 18,
21
+5V
+5V
Analog Supply Voltage. Independent +5 volt power connection to
analog comparator circuits.
DDA
DDD
GND
11, 13
13, 16
Digital Supply Voltage. Independent +5 volt power connection to
digital error correction and output drivers.
20, 21
2, 24
24, 25
3, 28
0.0V
0.0V
Analog Ground. Connect to the system analog ground plane.
Digital Ground. Connect to the system analog ground plane.
D
GND
No Connect
N/C
1, 8, 15,
22
open
Not Connected.
Bandwidth Specification Notes
The specification for bandwidth of an A/D converter is some-
what different from the normal frequency-response specifi-
cation used in amplifiers and filters. An understanding of the
differences will help in selecting converters properly for par-
ticular applications.
Sampling involves an aperture time, the time during which
the track/hold is trying to capture the input signal and settle
on a dc value to hold. It is analogous to the shutter speed of a
camera: the shorter the aperture (or faster the shutter) the less
the signal will be blurred, and the less uncertainty there will
be in the quantized value.
A/D conversion comprises two distinct processes: sampling
and quantizing. Sampling is “grabbing” a snapshot of the
input signal and holding it steady for quantizing. The quan-
tizing process is approximating the analog input, which may
be any value within the conversion range, with its nearest
numerical value. While sampling is a high-frequency pro-
cess, quantizing operates on a dc signal, held steady by the
track/hold circuit. Therefore, the sampling process is what
relates to the dynamic characteristics of the converter.
For example, a 10 MHz sinewave with a 1V peak amplitude
(2Vp-p) has a maximum slew rate of 2πfA at zero crossing,
or 62.8V/µs. With an 8-bit A/D converter, q (the quantization
step size) = 2V/255 = 7.8mV. The input signal will slew one
LSB in 124ps. To limit the error (and noise) contribution due
to aperture effects to 1/2LSB, the aperture must be shorter
than 62ps.
REV. 1.3.3 2/28/02
5
TMC1175A
PRODUCT SPECIFICATION
This is the primary reason that the signal to noise ratio drops
off as full scale frequency increases. Note, also, that the slew
rate is directly proportional to signal amplitude, A. A/Ds will
handle lower-amplitude signals of higher bandwidth.
sample on these pixel values, not on the slewing between
pixels. During the aperture time, the A/D sees essentially a
dc signal, and classic bandwidth considerations are not
important. As long as the input circuit can slew and settle to
the new value in the prescribed period, an accurate conver-
sion will be made.
All this is of particular interest in applications such as digi-
tizing analog VGA RGB signals, or the output of a CCD
imaging chip. These data are effectively pre-sampled: there
is a period of rapid slewing from one pixel value to another,
followed by a relatively stable dc level before the signal
slews to the next pixel value. The goal is, of course, to
The TMC1175A is capable of slewing a full 2V and settling
between samples taken as little as 25ns apart, making it ideal
for digitizing analog VGA and CCD outputs.
Equivalent Circuits and Threshold Level
V
V
DD
DD
p
p
Data or
Control
Input
Output
n
n
27011B
GND
27014B
GND
Figure 5. Equivalent Digital Output Circuit
Figure 4. Equivalent Digital Input Circuit
V
DDA
tENA
V
IN
tDIS
OE
0.5V
Three-State
Outputs
2.0V
0.8V
65-1175A-07
0.5V
High Impedance
A
GND
27052A
Figure 7. Threshold Levels for Three-State Measurements
Figure 6. Equivalent Analog Input Circuit
6
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Conditions
Min
Typ
Max
Unit
V
Power Supply Voltages
V
V
V
A
Measured to A
Measured to D
Measured to V
Measured to D
-0.5
-0.5
-0.5
-0.5
7.0
7.0
0.5
0.5
DDA
DDD
DDA
GND
GND
GND
DDD
GND
V
Digital Inputs
Applied Voltage2
Forced Current3,4
Analog Inputs
Applied Voltage2
Forced Current3,4
Outputs
Applied Voltage2
Forced Current3,4
Short Circuit Duration
Temperature
Measured to D
Measured to A
Measured to D
-0.5
V
V
V
+ 0.5
V
GND
GND
GND
DDD
-10.0
10.0
mA
-0.5
+ 0.5
V
DDA
-10.0
10.0
mA
-0.5
-6.0
+ 0.5
V
DDD
6.0
1
mA
sec
Single output in HIGH state to ground
Operating, Ambient
Junction
-20
-65
110
150
150
300
220
°C
°C
°C
°C
°C
Storage
Lead Soldering
Vapor Phase Soldering
Notes:
10 seconds
1 minute
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
operating conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device
REV. 1.3.3 2/28/02
7
TMC1175A
PRODUCT SPECIFICATION
.
Operating Conditions
Parameter
Min
4.75
4.75
-0.1
Nom
5.0
5.0
0
Max
5.25
5.25
0.1
Units
V
DDD
V
DDA
A
GND
Digital Power Supply Voltage
Analog Power Supply Voltage
Analog Ground (Measured to
V
V
V
D
GND
)
f
t
t
Conversion Rate
TMC1175A-20
TMC1175A-30
TMC1175A-40
TMC1175A-20
TMC1175A-30
TMC1175A-40
TMC1175A-20
TMC1175A-30
TMC1175A-40
20
30
40
Msps
Msps
Msps
ns
S
CONV Pulsewidth, HIGH
CONV Pulsewidth, LOW
15
13
12
15
12
12
2.0
0
PWH
PWL
ns
ns
ns
ns
ns
V
V
V
V
V
Reference Voltage, Top
Reference Voltage, Bottom
Reference Voltage Differential
Analog Input Range
2.6
0.6
V
V
RT
RB
DDA
3.0
V
V
1.0
5.0
V
RT- RB
V
RB
V
RT
V
IN
IH
Input Voltage, Logic HIGH
0.7 x
V
V
DDD
V
DDD
V
Input Voltage, Logic LOW
GND
0.3 x
V
IL
V
DDD
-4.0
4.0
I
I
Output Current, Logic HIGH
Output Current, Logic LOW
Ambient Temperature, Still Air
mA
mA
°C
OH
OL
T
A
-20
75
Electrical Characteristics
Parameter
Conditions
Min
Typ1 Max Units
I
Power Supply Current1
V
= V
DDA
= Max, C
= 35pF
DD
DDD
LOAD
f = 20Msps
20
25
30
30
35
40
mA
mA
mA
S
f = 30Msps
S
f = 40Msps
S
I
Power Supply Current,
Quiescent
V
= V
DDD DDA
= Max
DDQ
CONV = LOW
CONV = HIGH
7
18
20
mA
mA
10
P
Total Power Dissipation
V
DDD
= V
DDA
= Max, C
= 35pF
D
LOAD
f = 20Msps
100
125
150
4
160
185
210
mW
mW
mW
pF
S
f = 30Msps
S
f = 40Msps
S
C
R
Input Capacitance, Analog
Input Resistance
CONV = LOW
CONV = HIGH
AI
12
pF
500
1000
kΩ
IN
8
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
Electrical Characteristics (continued)
Parameter
Conditions
Min
Typ1 Max Units
I
Input Current, Analog
Reference Resistance
Input Current, HIGH
Input Current, LOW
Hi-Z Output Leakage
Hi-Z Output Leakage
Short-Circuit Current
Output Voltage, HIGH
1
340
5
µA
Ω
CB
R
200
270
REF
I
I
I
I
I
V
V
V
V
= Max, V = V
IN DDD
µA
µA
µA
µA
mA
V
IH
DDD
DDD
DDD
DDD
= Max, V = 0V
IN
5
IL
= Max, V = V
IN DDD
5
OZH
OZL
OS
= Max, V = 0V
IN
5
-30
V
I
I
I
I
= -100µA
= -2.5mA
= Max
V
-0.3
DDD
OH
OH
OH
OH
OL
3.5
V
2.4
V
V
Output Voltage, LOW
= Max
0.4
10
V
OL
C
C
Digital Input Capacitance
Digital Output Capacitance
4
pF
pF
DI
10
DO
Note:
1. Typical values with V
= V
DDA
= Nom and T = Nom, Minimum/Maximum values with V
DDD
= V = Max and T = Min.
DDA A
DDD
A
Switching Characteristics
Parameter
Conditions
Min
Typ
Max
Units
ns
t
t
t
t
t
Sampling Time Offset
Output Hold Time
2
5
5
8
STO
HO
C
C
= 15pF
= 15pF
ns
LOAD
Output Delay Time
Output Enable Time
Output Disable Time
20
27
42
ns
DO
LOAD
ns
ENA
DIS
ns
REV. 1.3.3 2/28/02
9
TMC1175A
PRODUCT SPECIFICATION
System Performance Characteristics
Parameter
Conditions
Min Typ1 Max Units
E
Integral Linearity Error,
Independent
V
RT
V
RB
= 2.6V
= 0.6V
0.5
1
LSB
LI
E
LD
Differential Linearity Error
V
RT
V
RB
= 2.6V
= 0.6V
0.3
1
LSB
BW
Bandwidth2
TMC1175A-20
TMC1175A-30
TMC1175A-40
10
12
12
MHz
MHz
MHz
E
E
E
Aperture Error
30
-25
40
ps
mV
mV
%
AP
OT
OB
Offset Voltage, Top
Offset Voltage, Bottom
Differential Gain
R – V for most positive code transition
IN
-8
-42
60
T
R – V for most negative code transition
B IN
30
dg
f = 14.3Msps
S
1.5
2.7
NTSC 40 IRE Mod Ramp
V
V
= +5.0V, T =25°C
DDA
= 2.6V, V
A
= 0.6V
RB
RT
dp
Differential Phase
f = 14.3Msps
NTSC 40 IRE Mod Ramp
0.5
1.0
deg
S
V
V
= +5.0V, T =25°C
DDA
= 2.6V, V
A
= 0.6V
RB
RT
SNR3 Signal-to-Noise Ratio
f = 20Msps, V = 2.6V, V
= 0.6V
= 0.6V
S
RT
RB
f
IN
f
IN
f
IN
f
IN
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
44
43
41
37
48
47
45
42
dB
dB
dB
dB
f = 30Msps, V = 2.6V, V
S
RT
RB
f
IN
f
IN
f
IN
f
IN
f
IN
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
= 12.0MHz
42
40
38
33
30
47
45
43
39
37
dB
dB
dB
dB
dB
f = 40Msps, V = 2.6V, V
= 0.6V
S
RT
RB
f
IN
f
IN
f
IN
f
IN
f
IN
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
= 12.0MHz
40
38
36
34
32
45
43
41
38
36
dB
dB
dB
dB
dB
10
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
System Performance Characteristics (continued)
Parameter
Conditions
Min Typ1 Max Units
SFDR4 Spurious-Free Dynamic
Range
f = 20Msps, V = 2.6V, V
= 0.6V
= 0.6V
S
RT
RB
f
IN
f
IN
f
IN
f
IN
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
46
44
41
38
52
51
45
43
dB
dB
dB
dB
f = 30Msps, V = 2.6V, V
S
RT
RB
f
IN
f
IN
f
IN
f
IN
f
IN
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
= 12.0MHz
42
40
37
35
34
49
45
41
40
39
dB
dB
dB
dB
dB
f = 40Msps, V = 2.6V, V
= 0.6V
S
RT
RB
f
IN
f
IN
f
IN
f
IN
f
IN
= 1.24MHz
= 2.48MHz
= 6.98MHz
= 10.0MHz
= 12.0MHz
40
39
38
36
36
44
43
41
40
39
dB
dB
dB
dB
dB
Notes:
1. Values shown in Typ column are typical for V
DDD
= V = +5V and T = 25°C.
DDA A
2. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes.
3. SNR values do not include the harmonics of the fundamental frequency.
4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude.
REV. 1.3.3 2/28/02
11
TMC1175A
PRODUCT SPECIFICATION
Typical Performance Characteristics
60
50
40
30
20
30
25
20
15
10
5
f
f
f
= 20 Msps
= 30 Msps
= 40 Msps
s
s
s
10
0
0
0
2
4
6
8
10
12
0
10
20
30
40
Figure 8. Typical I
DD
vs f
Figure 9. Typical SFDR vs f and f
IN
S
S
50
40
30
20
10
50
40
30
20
f
f
f
= 20 Msps
= 30 Msps
= 40 Msps
f
f
= 20 Msps
= 33 Msps
s
s
s
s
s
10
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
2
4
6
8
10
12
Figure 10. Typical SNR vs f and f
IN
Figure 11. Typical SNR vs Full Scale Input Range
S
Applications Discussion
The circuit in Figure 12 employs a band-gap reference to
generate a variable RT reference voltages for the
The circuit in Figure 13 shows self-bias of R and R by
T B
connection to VR+ and VR-. This sets up a 0.6 to 2.6 Volt
TMC1175A as well as a bias voltage to offset the wideband
input amplifier to mid-range. An "offset adjust"
is also shown for varying the mid-range voltage level.
The operational amplifier in the reference circuitry is a
standard 741-type.
input range for V . The input range is susceptible to power
IN
supply variation since the voltages on R and R are directly
T
B
derived from V . The video input is AC-coupled and
DDA
biased at a adjustable midpoint of the A/D input range.
This circuit offers the advantage of minimum support
circuitry for the most cost-sensitive applications.
The voltage reference at R can be adjusted from 0.0 to 2.4
T
volts while R is grounded. Diodes are used to restrict the
In Figure 14, an external band-gap reference sets R to +1.2
T
B
wideband amplifier output to between -0.7V and V
DD
Volts while R is grounded. The internal pull-up resistor,
B
+0.7V. Diode protection is good practice to limit the analog
input voltage at V to the safe operating range.
IN
R+, provides the bias current for the band-gap reference. The
A/D converter input is biased to the mid-point of the input
range.
12
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
Regulated +5V
+5V
0.1µF
0.1µF
1kΩ
LM385
V
V
DDD
+5V
DDA
0.1µF
Gain Adjust
VR+
R
T
20Ω
2V
+
2kΩ
0.1mF
-
1kΩ
0.1µF
TMC1175A
R
B
D
7-0
1kΩ
VR-
Wideband
Op-amp
+
-
OE
Video
Input
V
IN
CONV
455Ω
75Ω
A
D
GND
GND
455Ω
+5V
27056A
Figure 12. Typical Interface Circuit-High Performance
Grounding
+5V
0.1µF
0.1µF
The TMC1175A has separate analog and digital
circuits. To keep digital system noise from the A/D
converter, it is recommended that power supply voltages
V
V
DDD
DDA
Offset
Adjust
+5V
2.2kΩ
VR+
(V
and V
) originate from separate sources with
regulated, and that ground connections (D and
GND
DDD
DDA
R
T
V
DDA
0.1µF
TMC1175A
A ) be made to the analog ground plane. Power supply
GND
2kΩ
R
pins should be individually decoupled at the pin. The digital
circuitry that gets its input from the TMC1175A should be
referred to the system digital ground plane.
B
D
7-0
0.1µF
VR-
560Ω
0.1µF
OE
Video
Input
CONV
V
IN
Printed Circuit Board Layout
10µF
75Ω
A
D
GND
GND
Designing with high performance mixed-signal circuits
demands printed circuits with ground planes. Wire-wrap is
not an option, even for breadboarding. Overall system per-
formance is strongly influenced by the board layout. Capac-
itive coupling from digital to analog circuits may result in
poor A/D conversion. Consider the following suggestions
when doing the layout:
24458A
Figure 13. Typical Interface Circuit – Low Cost
+5V
0.1µF
0.1µF
1. Keep the critical analog traces (V , R , R , VR+,
V
V
DDD
IN
T
B
DDA
VR-) as short as possible and as far as possible from all
digital signals. The TMC1175A should be located near
the board edge, close to the analog input connectors.
VR+
R
T
TMC1175A
0.1µF
LM385
2. The power plane for the TMC1175A should be sepa-
rate from that which supplies the rest of the digital cir-
cuitry. A single power plane should be used for all of
R
B
1kΩ
D
7-0
VR-
10µF
RF
Input
OE
V
IN
the V
DD
pins. If the power supply for the TMC1175A
CONV
is the same as that of the system's digital circuitry,
power to the TMC1175A should be decoupled with
ferrite beads and 0.1µF capacitors to reduce noise.
56Ω
1kΩ
A
D
GND
GND
24457A
Figure 14. Typical Interface Circuit – Stabilized Reference
3. The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very
short leads.
REV. 1.3.3 2/28/02
13
TMC1175A
PRODUCT SPECIFICATION
4. Decoupling capacitors should be applied liberally to
6. CONV should be handled carefully. Jitter and noise on
this clock may degrade performance. Terminate the
clock line at the CONV input, if required, to eliminate
overshoot and ringing.
V
DD
pins. Remember that not all power supply pins are
created equal. They supply different circuits on the inte-
grated circuit, each of which generate varying amounts
and types of noise. For best results, use 0.1µF ceramic
capacitors. Lead lengths should be minimized. Ceramic
chip capacitors are the best choice.
Evaluation Board
An evaluation board is available that implements good inter-
face practices and provide a convenient testbed for develop-
ing system applications and circuit variations. An on-board
D/A converter is provided to reconstruct the digitized signal
and to evaluate converter performance.
5. If the digital power supply has a dedicated power plane
layer, it should not be placed under the TMC1175A, the
voltage reference, or the analog inputs. Capacitive cou-
pling of digital power supply noise from this layer to the
TMC1175A and its related analog circuitry can have an
adverse effect on performance.
Contact your sales representative for information.
14
REV. 1.3.3 2/28/02
PRODUCT SPECIFICATION
TMC1175A
Mechanical Dimensions
24 Lead SOIC (5.4 mm) Package
Inches
Millimeters
Min. Max.
Symbol
Notes
Min.
Max.
.067
.004
1.70
0.10
A
.075
.012
1.90
0.31
A1
B
.014
.006
.587
.205
.295
.020
.012
.610
.220
.319
0.36
0.15
0.51
0.30
C
14.90
5.20
15.50
5.60
D
E
7.50
8.10
E1
e
.050 BSC
1.27 BSC
0.25
0.41
0.50
1.27
.010
.016
.020
.050
h
L
24
24
N
8
α°
ccc
8
0
-
0
-
0.10
.004
24
13
E1
E
12
1
D
h x 45°
C
A1
SEATING PLANE -C-
A
α
L
e
B
LEAD COPLANARITY
ccc C
REV. 1.3.3 2/28/02
15
TMC1175A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
28 Lead PLCC Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Min.
Max.
Min.
Max.
2. Corner and edge chamfer (J) = 45°
A
.165
.090
.020
.013
.026
.485
.450
.180
.120
—
4.19
2.29
.51
4.57
3.05
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
A1
A2
B
.021
.032
.495
.456
.33
.53
B1
.66
.81
D/E
D1/E1
D3/E3
e
12.32
11.43
12.57
11.58
3
2
.300 BSC
.050 BSC
.042 .048
7.62 BSC
1.27 BSC
1.07 1.22
J
ND/NE
N
7
7
28
28
ccc
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
J
e
A
A1
– C – LEAD COPLANARITY
B
A2
ccc C
16
REV. 1.3.3 2/28/02
TMC1175A
PRODUCT SPECIFICATION
Ordering Information
Conversion
Package
Product Number
TMC1175AM7C20
TMC1175AM7C30
TMC1175AM7C40
TMC1175AR3C20
TMC1175AR3C30
TMC1175AR3C40
Rate
Temperature Range
T = -20°C to 75°C
Screening
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Package
Marking
20 Msps
30 Msps
40 Msps
20 Msps
30 Msps
40 Msps
24-Lead SOIC
24-Lead SOIC
24-Lead SOIC
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
1175AM7C20
1175AM7C30
1175AM7C40
1175AR3C20
1175AR3C30
1175AR3C40
A
T = -20°C to 75°C
A
T = -20°C to 75°C
A
T = -20°C to 75°C
A
T = -20°C to 75°C
A
T = -20°C to 75°C
A
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
2/28/02 0.0m 002
Stock#DS7001175A
2002 Fairchild Semiconductor Corporation
Product Folder - Fairchild P/N TMC1175x20 - 20MSPS 8-Bit Video A/D Converter
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Datasheet
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datasheet
Contents
How to order products
General description | Features | Applications |
Product status/pricing/packaging
Product Change Notices
(PCNs)
PDF
Support
General description
e-mail this datasheet
[E-
Distributor and field sales
representatives
The TMC1175A analog-to-digital (A/D)
converter employs a two-step flash architecture
to convert analog signals into 8-bit digital
words at sample rates of up to 40 Msps
(Megasamples per second). An integral
Track/Hold circuit delivers excellent
performance on signals with full-scale
frequency components up to 12 MHz.
Innovative architecture and submicron CMOS
technology limit typical power dissipation to
100 mW.
Quality and reliability
This page
Print version
Design tools
technical information
buy products
technical support
my Fairchild
Power may be derived from either single or
dual +5V supplies. Internal voltage reference
resistors allow self-bias operation. Input
capacitance is very low, simplifying or
eliminating input driving amplifiers. All digital
three-state outputs are TTL- and CMOS-
compatible.
company
The TMC1175A is available in 24-pin plastic
SOIC, and 28-lead J-lead PLCC packages.
Performance specifications are guaranteed
from -20°C to 75°C.
back to top
Features
Product Folder - Fairchild P/N TMC1175x20 - 20MSPS 8-Bit Video A/D Converter
●
●
●
●
●
8-Bit resolution
40 Msps conversion rate
Low power: 100mW at 20 Msps
Integral track/hold
Integral and differential linearity error
0.5 LSB
●
●
●
●
Single or dual +5 Volt supplies
Differential phase 0.5 degree
Differential gain 1.5%
Three-state TTL/CMOS-compatible
outputs
●
Low cost
back to top
Applications
●
●
●
●
●
●
●
Video digitizing
VGA and CCD digitizing
LCD projection panels
Image scanners
Personal computer video boards
Multimedia systems
Low cost, high speed data conversion
back to top
Product status/pricing/packaging
Product
Product status
Pricing* Package type Leads Packing method
TMC1175AN2B20
TMC1175AM7C20
TMC1175AN2C20
Lifetime Buy
Full Production
Lifetime Buy
N/A
DIP
24
24
24
RAIL
RAIL
RAIL
$2.84 SOIC-Wide
$11.41
N/A
DIP
CDIP
PLCC
N/A
Not recommended for new
designs
TMC1175AB2F20
TMC1175AR3C20
TMC1175AC3F20
24
28
RAIL
RAIL
Full Production
$9.69
N/A
Not recommended for new
designs
N/A
BLISTER PK
* 1,000 piece Budgetary Pricing
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© Copyright 2002 Fairchild Semiconductor
Product Folder - Fairchild P/N TMC1175x20 - 20MSPS 8-Bit Video A/D Converter
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