TMC2242CR2C1 [FAIRCHILD]
Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz; 数字半带插值/抽取滤波器的12位输入/ 16位输出， 60 MHz的
| 型号： | TMC2242CR2C1 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| 文件： | 总16页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
TMC2242C
Digital Half-Band Interpolating/Decimating Filter
12-bit In/16-bit Out, 60 MHz
Description
Features
The TMC2242C, a linear-phase low-pass half-band digital
filter with fixed coefficients, can be used to halve or double
the sampling rate of a digital signal. When used as a decimat-
ing post-filter with a double-speed oversampling A/D con-
verter, it greatly reduces the cost and complexity of the
required analog antialiasing pre-filters. When used as an
interpolating pre-filter with a double-speed oversampling
D/A converter, it greatly reduces the complexity and cost of
the necessary analog post-filter, particularly when its x/sin(x)
correction filter is engaged.
• Pin-compatible upgrade of TMC2242B
• User-selectable interpolate d.c. gain, 0 dB or -6 dB
• True unity d.c. gain in all “0 db” modes
• 40 MSPS performance in equal-rate filter modes
• 40 and 60 MSPS speed grades in all other modes
• User-selectable 2:1 decimation, 1:2 interpolation, and
equal-rate filter modes, plus unfiltered bypass/delay mode
• Defeatable πx/sin(πx) compensation filter
• Passband ripple <0.014 dB
• Stopband rejection >56 dB
• Dedicated 12-bit two’s complement or unsigned input bus
• 16-bit two’s complement or unsigned output bus with
user-selectable rounding to 8 to 16 effective bits
• Programmable limiter prevents overflow or clips to
CCIR601 levels
The TMC2242C user selects the mode of operation (deci-
mate, interpolate, equal-rate, bypass, x/sin(x))and rounding.
The part can accept 12-bit two’s complement or unsigned
data at up to 60 MHz and can output saturated two’s comple-
ment or offset binary data rounded to from 8 to 16 bits.
Within the speed grade I/O limit, the output sample rate may
be 1/2, 1, or 2 times the input sample rate. Two-channel
modes permit it to interpolate or to decimate two multi-
• New double-latency modes match Y channel data flow to
slower-sampled C and C data flows
B
R
• New dual-channel interpolation and decimation for
YUV422
plexed data streams (such as video C and C ) jointly.
B
R
Applications
The filter response is flat to within ±0.014 dB up to 0.21f
s
• Digital-to-Analog Converter Prefiltering with optional
x/sinx correction
(e.g. 5.75MHz at a 27MHz clock rate), with stopband attenu-
ation greater than 56dB above 0.29f . Symmetric-coefficient
s
• 1:2 interpolation
• Analog-to-Digital Converter Postfiltering
• 2:1 decimation
filters such as the TMC2242C always have linear phase
response. Half-band response is -6 dB.
• Low-ripple low-pass (0 to 0.2 f ) filter
s
Fabricated on an advanced submicron CMOS process, the
TMC2242C is available in a 44-lead PLCC package. Perfor-
mance is guaranteed from 0 to 70°C and over a power supply
range of 4.75 to 5.25V.
Block Diagram
X/SIN(X)
FILTER
ROUND
LIMIT
ZERO
INSERT
FIR
FILT
SI
11-0
SO
15-0
DECIMATE
SO
3-0
CONTROL
65-2242C-01
DEC INT SYNC TCO RND OE
Rev. 1.0.0
PRODUCT SPECIFICATION
TMC2242C
and other special modes. Unless more than 12 output bits are
enabled, the TMC2242C offers x/sin(x) correction filtering,
with or without the main low-pass filter, and without impact-
Functional Description
The TMC2242C implements a fixed-coefficient linear-phase
Finite Impulse Response (FIR) filter, with special rate-
matching input and output structures for decimation and
interpolation. For parts of each speed grade, the faster of
either the input or the output bus will operate at the respec-
tive guaranteed maximum clock rate. The total internal
pipeline latency from the input of an impulse to the corre-
sponding output peak (digital group delay) is 34 clock
cycles; the 39-value output response begins after 15 clock
cycles and ends after 53 cycles. (The double-latency interpo-
lation and decimation modes feature group delays of 68
clock cycles.)
ing the 34-cycle group delay. Bidirectional pins SO
3-2
enable these modes, per Table 1. If 14 or more output bits are
used, the low pass filter remains enabled, the x/sin(x),
disabled.
Table 1. Operating Modes
INT DEC RND SO
Function
Interpolate (0 dB)
Interpolate1 (-6 dB)
Decimate
2
3-2
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
Output
Output
Output
Output
00
To interpolate, the chip accepts incoming data on alternate
clock cycles, inserting zeroes on the remaining clock cycles.
In decimation mode, the chip’s output register is strobed at
half the clock rate. In bypass and equal-rate filter modes,
these input zero insertion and output register hold functions
are disabled.
Equal Rate Lowpass
Interpolate (0 dB)
Interpolate1 (-6 dB)
Decimate
00
00
00
Equal Rate Lowpass
01
Interpolate (0 dB)
* x/sinx
When interpolating, the user should normally bring SYNC
HIGH for at least one clock cycle, returning it LOW with the
first desired input data value. The chip will then continue to
accept data on alternate rising edges of CLK. The user may
leave SYNC LOW or change its value once per clock cycle,
with equivalent results. The chip can be powered up and
operated with SYNC grounded, but the input-to-output
latency may vary by 1/2 input sample period and the host
system won’t know which (even- or odd-numbered) CLK
rising edges strobe the input register. The setup and hold tim-
ing requirements for SYNC, with respect to the rising edges
of CLK, are the same as those for all other data and control
inputs except OE, which is asynchronous. In two-channel
mode, it must remain low after the first incoming data value.
0
1
1
01
Interpolate1 (-6 dB)
* x/sinx
1
1
0
0
1
0
1
1
1
01
01
10
Decimate * x/sinx
Equal Rate LPF * x/sinx
Delay + Interpolate2
(0 dB)
0
1
1
10
Delay + Interpolate2
(0 dB) * x/sinx
1
1
0
0
1
0
1
1
1
10
10
11
Delay + Decimate2
Bypass (Delay Only)
2-Channel Interpolate3
(0 db)
When decimating, the user should likewise bring SYNC
HIGH for at least one clock cycle, returning it LOW when a
fresh output is desired. The chip will continue to update the
output register on alternate rising edges of CLK. The user
may leave SYNC LOW or change its value once per clock
cycle, with equivalent results. The chip can be powered up
and operated with SYNC grounded, but the host system
won’t know whether the data outputs are updated on even- or
odd-numbered system clock cycles. In any half-band deci-
mating filter, a given single-cycle impulse’s arrival time (on
an odd versus an even clock cycle) determines whether it
generates a half-amplitude two-cycle impulse or a half-
speed, 40-clock, filtered output shaped by the nonzero, non-
center coefficients. The SYNC control permits the host sys-
tem to obtain consistent results. In two-channel mode, it
must remain low after the first incoming data value.
0
1
1
11
2-Channel Interpolate3
* x/sinx
1
1
0
1
1
1
11
11
2-Channel Decimate3
Delay * x/sinx
Note:
1. These modes limit to 15 bits (SO
) instead of 16
14-0
) and are provided for backward compatibility to
(SO
15-0
earlier parts.
2. These modes, which double the chip’s overall group delay
from 34 to 68 CLK cycles, can be used to equalize inter-
component delays where Y is sampled at twice the rate of
C
B
or C (e.g. 4:2:2 and 8:4:4 formats).
R
3. These modes accommodate multiplexed two-channel da-
ta, e.g. C C .
B/
R
When the result is rounded to fewer than 16 bits, the
unneeded lowest positions of the output bus are tristated
and become supplementary control bits, which enable the
x/sin(x) filter, bypass/delay, double-latency, dual-channel,
2
TMC2242C
PRODUCT SPECIFICATION
The output data format is two’s complement if TCO is HIGH,
inverted or offset binary if LOW. Unless all 16 output bits are
used, the user can also select either signed or unsigned input
data, via pin SO (see pin description note 2, below). As
0
shown in pin description note 1, the output is half-LSB
Table 2. Package Interconnections
Signal
Type
PLCC MQFP
Pin
Name
Function
Pin
Timing
CLK
Clock
42
36
rounded to the resolution selected by the value of RND
The asynchronous three-state output enable control simplifies
connection to a data bus with other drivers.
.
2-0
SYNC Synchronization
Data In SI Input Data Port
43
37
40,
34,
11-0
37-30, 31-24,
27-25 21-19
Data Out SO
15-4
Output Data Port 4-11, 42-44,
14-17
1-5,
8-11
Dual-
SO
Output
18-21 12-15
3-0
Function
Controls
Data; Controls
INT
DEC
RND
Interpolate
Decimate
44
1
38
39
Rounding
Position
22-24 16-18
2-0
TCO
OE
Output Format
Output Enable
2
3
40
41
Pin Assignments
SO
SO
SO
7
39
GND
12
11
10
SO
SO
SO
1
33
32
31
30
29
28
27
26
25
24
23
GND
12
11
10
8
38
37
36
35
34
33
32
31
30
29
V
DD
2
V
DD
9
SI
SI
SI
SI
SI
SI
SI
SI
10
9
3
SI
SI
SI
SI
SI
SI
SI
SI
10
9
SO
10
11
12
13
14
15
16
17
9
8
SO
4
9
8
SO
8
TMC2242C
SO
5
8
GND
7
TMC2242C
GND
6
7
V
DD
6
V
7
DD
6
SO
SO
SO
SO
7
6
5
4
5
SO
SO
SO
SO
8
7
6
5
4
5
4
9
4
3
10
11
3
V
DD
V
DD
65-2242C-02A
65-2242C-02B
44 Lead PLCC
44 Lead MQFP
3
PRODUCT SPECIFICATION
TMC2242C
Pin Descriptions
Pin Number
PLCC MQFP
Dedicated Timing Controls
Pin Name
Pin Function Description
CLK
42
36
Clock. The chip operates from a single-phase master clock, to whose rising
edges all timing parameters are referenced. All internal registers are strobed on
every rising edge of CLK, although the output register is strobed on alternate
rising edges during decimation. In all modes, the frequency applied to CLK is the
higher of the input and output data sampling rates. During interpolation, the chip
reads its input bus on alternate rising edges of CLK.
SYNC
43
37
Synchronization. During interpolation, the chip accepts input data on alternate
rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is
HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will
accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either
held LOW or fed a square wave of half the CLK frequency, the part will continue
to accept data on odd-numbered CLK edges and to stuff zeroes on even-
numbered edges. Similarly, during decimation, the output data change only on
alternate clock cycles. If the user operates SYNC as above, each even-
numbered rising edge of CLK will trigger a change in the output. In all other
modes, the state of SYNC doesn’t affect operation of the chip.
Dedicated Data Input Port
SI 40, 34,
Input Data. A 12-bit two’s complement or unsigned input word is registered by
11-0
37-30, 31-24, the rising edges of CLK. SI is the LSB.
0
27-25 21-19
Dedicated Data Output Port
SO 4-11, 42-44, Output Data MSBs. When OE is LOW, the 12 most significant bits of the filter’s
15-0
14-21 1-5,
8-15
output emerge here, following each rising edge of CLK. The format may be two’s
complement, unsigned, or inverted offset binary. Bits SO correspond to
15-4
input bits SI
, respectively. An on-chip limiter prevents overflows and
11-0
underflows in the output data.
Dual Function Data Output/Control Input Pins
SO
SO
SO
Output Data. These pins serve as data outputs when RND is LOW. When
2
3-2
RND is HIGH, they become additional filter mode controls (Table 1).
2
Output Data 2nd LSB. This pin is a data output when RND
are LOW. When
either RND or RND is HIGH, it becomes an additional rounding control.1
1
2-1
2
1
Output Data LSB. This pin is a data output if and only if all RND bits are LOW.
0
Otherwise, it augments the data I/O format controls.2
Dedicated Static Controls (Set state before first desired data input.)
INT, DEC
44, 1
38, 39 Interpolate and Decimate. Jointly with SO , these bits select the chip’s
3-2
overall operating mode, as discussed earlier in Table 1
TCO
2
40
Output format control. When TCO is HIGH, the output data are in two’s
complement format. When TCO is LOW, they are inverted offset binary, unless
SO is HIGH and RND is nonzero, in which case they are unsigned.
0
RND
2-0
22-24 16-18 Round and output tristate. Selects output rounding position and active bus
width 8-16 bits. All outputs at and below the rounding bit position are tristated,
allowing the 4 LSBs to become control inputs.
Active, Asynchronous Control
OE 41 Output enable. LOW activates output bus from SO down to the effective LSB,
3
15
as chosen by RND . All drivers at and below the rounding point are disabled,
2-0
as are all drivers when OE is HIGH.
4
PRODUCT SPECIFICATION
TMC2242C
Notes:
2. I/O Format Operation Detail
1. Rounding Operation Detail
RND
SO
TCO
In Format Out Format
0
RND
2-0
SO
Output Rounding
1
0
Output
0
2’s Comp Inverted
Offset
A
A
000
001
010
011
100
100
101
110
111
Output
SO
SO
SO
(16 bits)
(15 bits)
(14 bits)
15-0
15-1
15-2
0
Output
0
1
0
2’s Comp 2’s Comp
Output
>0
2’s Comp Inverted
Offset
X
X
0
1
0
1
X
SO
(13)
(12)
(8)
15-3
15-4
>0
>0
>0
0
1
1
1
0
1
2’s Comp 2’s Comp
Unsigned Unsigned
Unsigned 2’s Comp
SO
SO
15-8
15-5
15-6
SO
SO
(11)
(10)
(9)
SO
15-7
A. If RND
= 00X, do not drive SO , externally.
1
2-0
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Conditions
Min
Max
Units
V
Supply Voltage
-0.5
-0.5
-0.5
-3.0
7.0
Input Voltage
V
V
+ 0.5
V
DD
DD
Output Applied Voltage2
Externally Forced Current3,4
+ 0.5
V
+6.0
mA
sec
°C
°C
°C
°C
Short Circuit Duration
Operating Temperature (Case)
Junction Temperature
Lead Soldering Temperature
Storage Temperature
Notes:
Single output in HIGH state to ground
10 seconds
1
-20
-65
110
140
300
150
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating
Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5
PRODUCT SPECIFICATION
TMC2242C
Operating Conditions
Conditions
Min
Nom
Max
5.25
40
Units
V
V
Power Supply Voltage
Clock frequency
4.75
5.0
DD
f
TMC2242C
MHz
MHz
ns
CLK
TMC2242C-1
60
t
t
t
t
CLK pulse width, HIGH
CLK pulse width, LOW
6
6
PWH
PWL
S
ns
Input Data Set-up Time
Input Data Hold Time
6
ns
0
ns
H
V
V
Input Voltage, Logic HIGH
Input Voltage, Logic LOW
Output Current, Logic HIGH
Output Current, Logic LOW
Ambient Temperature, Still Air
2.0
V
IH
IL
0.8
-2.0
4.0
70
V
I
I
mA
mA
°C
OH
OL
T
0
A
Electrical Characteristics
P arameter
Conditions
= Max, C
Min
Typ
Max
Units
I
I
I
Total Power Supply
Current
V
=25pF, f =Max
LOAD CLK
DD
DD
TMC2242C
150
220
mA
mA
TMC2242C-1
Power Supply Current,
Unloaded
V
= Max, OE = HIGH, f =Max
CLK
DDU
DDQ
DD
TMC2242C
135
200
5
mA
mA
mA
TMC2242C-1
Power Supply Current,
Quiescent
V
= Max, CLK = LOW
DD
C
I/O Pin Capacitance
Input Current, HIGH
5
pF
µA
µA
PIN
I
I
V
V
= Max, V = V
IN
±10
IH
DD
DD
Input Current, HIGH
(Pulldown SO0–SO3)
= Max, V = V
IN
-10
+150
IH
DD
DD
(PD)
I
I
I
Input Current, LOW
V
= Max, V = 0 V
IN
±10
±10
µA
µA
µA
IL
DD
Leakage Current, HIGH
OE = HIGH, V
OE = HIGH, V
= V
= V
OZH
OZH
OUT
OUT
DD
Leakage Current, HIGH
(Pulldown SO0–SO3)
-10
+150
DD
(PD)
I
I
Leakage Current, LOW
Short-Circuit Current
OE = HIGH, V
= 0 V
±10
µA
OZL
OS
OUT
V
= Max, Output = HIGH, one pin to
-90
2.4
-150
mA
DD
ground, one second duration max.
V
V
Output Voltage, HIGH
Output Voltage, LOW
SO15-0, I
= Max
V
V
OH
OH
SO15-0, I = Max
0.4
OL
OL
Switching Characteristics
Parameter
Conditions
Min
Typ
Max
Units
ns
t
t
t
t
Output Delay Time
Output Hold Time
Output Enable Time
Output Disable Time
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 25 pF
= 25 pF
= 0 pF
= 0 pF
15
DO
2.5
ns
HO
15
30
ns
ENA
DIS
ns
6
PRODUCT SPECIFICATION
TMC2242C
Table 3a. Input Data Formats and Bit Weighting
Format
Two’s Comp.
Unsigned
SI
11
SI
S
. . .
. . .
. . .
SI
S
0
10
2-1
2-1
9
1
-20
20
2-2
2-2
2-10
2-10
2-11
2-11
Table 3b. Output Data Formats and Bit Weighting
Format
Two’s Comp.
Unsigned1
-6 dB t.c.2
SO
15
-20
20
-20
0
SO
SO
. . .
. . .
. . .
. . .
. . .
SO
SO
4
14
2-1
13
2-2
5
2-10
2-10
2-9
2-11
2-11
2-10
2-10
2-1
-20
20
2-2
2-1
2-1
-6 dB Unsgn3
2-9
Notes:
1. Inverted offset binary is the same as unsigned, except that all bits are complemented.
2. In -6 dB interpolation modes, the two’s complement sign bit is replicated in SI and SI
.
15 14
3. In -6 dB interpolation mode, the unsigned MSB is preceded by a 0 in SO
4. A leading minus sign denotes the two’s complement sign bit.
.
15
5. In all operating modes except “interpolate -6 dB,” dc gain is exactly unity.
Table 4. Rounded LSBs as a function of RND
2-0
RND
2-0
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
…
…
…
…
…
…
…
…
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
z
000
001
010
011
1002
101
110
111
15
15
15
15
15
15
15
15
14
14
14
14
14
14
14
14
13
13
13
13
13
13
13
13
8
8
8
8
8
8
8
8
7
7
6
6
5
5
4
4
4
4
3
3
2
2
1
0r
SO
SO
SO
SO
SO
z
1r
SO
z
z
7
6
5
3
2r
SO
z
z
z
7
6
5
3r
z
z
z
7
6
5
4r
SO
z
z
z
z
z
z
z
z
7
6
5r
SO
z
z
z
z
z
7
6r
SO
z
z
z
z
z
7r
Note:
1. The “r” indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. All output drivers at and
below the rounding bit are disabled, allowing the lower output bits to be used as control inputs.
2. If SO = 1, format is 8 bits, viz: SO …SO8r z…z.
15
1
Table 5. Steady-State Output Values and Limit Triggers
Input Interpolate -6 dB All Other Modes
Unsigned Unsigned 2’s Comp.
7FF81 3FF81
Interpretation
2’s Comp.
7FF
Unsigned
2’s Comp.
7FF01
4000
Unsigned
2’s Comp.
full-scale +
1/2 scale +
1 LSB +
FFF
C00
801
800
7FF
400
000
FFF01
C000
8010
8000
7FF0
4000
00001
full-scale
3/4-scale
400
6000
4008
4000
3FF8
2000
00001
2000
0008
0000
FFF8
E000
C0001
001
0010
000
0000
1/2-scale
Zero
FFF
FFF0
1 LSB –
C00
C000
80001
1/4-scale
zero
1/2-scale –
full-scale –
800
Notes:
1. Full-scale values are minima and maxima permitted by on-chip limiter. Transient overshoots arising from large input signal
transitions will be clipped to these limits.
7
TMC2242C
PRODUCT SPECIFICATION
Performance Curves
0
-10
-20
-30
-40
-50
-60
-70
-80
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Normalized Frequency
Figure 1. Frequency Response
0.030
0.025
0.020
0.015
0.010
0.006
0.000
-0.008
-0.010
0.00
0.05
0.10
Normalized Frequency
Figure 2. Passband Ripple Response
0.15
0.20
0.35
110
100
90
80
70
60
50
40
30
20
10
0
-10
0
10
20
30
40
50
60
Sample
Figure 3. Step Response
8
PRODUCT SPECIFICATION
TMC2242C
Equivalent Circuits
V
V
DD
DD
p
p
Digital
Input
Digital
Output
n
n
65-2242C-10
65-2242C-09
GND
GND
Figure 4. Equivalent Digital Input Circuit
Figure 5. Equivalent Digital Output Circuit
Timing Diagrams
t
t
PWL
1/f
PWH
C
CLK
t
t
H
S
SI
34
35
36
37
38
11-0
SYNC
t
t
DO
HO
1
2
3
4
SO
15-0
65-2242C-06
OE is LOW.
Note: Values at SO
are impulse response centers (peaks) corresponding to same-numbered inputs.
15-0
Figure 6. Equal Rate Mode
t
t
PWL
1/f
PWH
37
C
34
35
36
38
CLK
t
t
H
S
SI
34
35
36
37
38
11-0
SYNC
t
HO
1
3
SO
15-0
65-2242C-07
OE is LOW.
Figure 7. Decimate Mode
9
TMC2242C
PRODUCT SPECIFICATION
t
t
1/f
PWH
37
PWL
C
34
35
36
38
CLK
t
t
H
S
SI
35
37
71
71
11-0
SYNC
t
t
DO
HO
1
2
3
4
SO
15-0
65-2242C-08
OE is LOW.
Figure 8. Interpolate Mode
t
t
1/f
C
PWH
71
PWL
68
69
70
72
CLK
t
t
H
S
SI
68
69
70
72
11-0
SYNC
t
HO
1
3
SO
15-0
65-2242C-14
OE is LOW.
Figure 9. Decimate Mode – Double Latency
t
t
1/f
C
PWH
71
PWL
68
69
70
72
CLK
t
t
H
S
SI
69
11-0
SYNC
t
t
DO
HO
1
2
3
4
SO
15-0
65-2242C-15
OE is LOW.
Figure 10. Interpolate Mode – Double Latency
10
PRODUCT SPECIFICATION
TMC2242C
t
t
PWL
1/f
PWH
37
C
34
35
36
38
CLK
t
t
H
S
SI
Y
67
68
Y
69
70
Y
71
11-0
C
C
SYNC*
t
HO
1
Y
2
C
5
Y
SO
15-0
65-2242C-16
OE is LOW.
*In two-channel modes, sync must be left low after the first data input.
Figure 11. Decimate Mode – Two-Channel
t
t
PWL
1/f
C
PWH
37
34
35
36
38
CLK
t
t
H
S
SI
69
Y
71
C
11-0
SYNC*
t
t
DO
HO
1
Y
C
Y
3
C
SO
15-0
65-2242C-17
OE is LOW.
*In two-channel modes, sync must be left low after the first data input.
Figure 12. Interpolate Mode – Two-Channel
t
ENA
t
OE
0.5V
DIS
Three-State
Outputs
2.0V
0.8V
0.5V
High Impedance
65-2242C-11
Figure 13. Threshold Levels for Three State Measurements
11
PRODUCT SPECIFICATION
TMC2242C
In Figure 15, the TMC2242C drives a fast D/A converter to
reconstruct analog composite video. The TMC3003 10-bit
digital-to-analog converter inputs, D are connected to the
9-0
Applications Discussion
The TMC2242C is well-suited to filtering digitized compos-
ite or component NTSC or PAL video. In Figure 14, the
TMC2242C outputs SO , respectively. The TMC2242C
15-6
TMC1175A 8-bit video A/D converter outputs, D , are
7-0
RND controls are set to 110 for rounded 10-bit interpola-
2-0
tion operation.
connected to the TMC2242C inputs, SI
, respectively. To
11-4
minimize noise and any chance of electrostatic damage,
inputs SI should be grounded. Controls RND are set to
3-0 2-0
100 and SO is forced high to effect 8-bit rounding. SO
,
1
3-2
TCO, and DEC are forced low, whereas INT and SO are
0
forced high. (Setting SO high and TCO low selects
0
unsigned binary format at the input and output data ports,
eliminating the need for external MSB inverters.)
TTL Clock
27.000 MHz (D1)
28.636 MHz (NTSC D2)
2 uH
2 uH
TMC1175A
8-bit A/D
TMC2242C
VIN
Composite
Video
SI
300 pF
510 pF
11-4
8
75 Ohm
D
7-0
75 Ohm
300 pF
8
SO
15-8
AGND
27.000 MHz (D1)
28.636 MHz (NTSC D2)
13.500 MHz (D1)
14.318 MHz (NTSC D2)
65-2242C-12
Figure 12. Decimating Oversampled Video With a Low Cost 8-bit A/D
TCO = 0 RND = 100 SO(3:0) = 0011 DEC = 0 INT = 1
TTL Clock
27.000 MHz (D1)
28.636 MHz (NTSC D2)
TMC3003
TMC2242C
2 uH
2 uH
10-bit D/A
I
OUT
10
D
9-0
SO
15-6
Composite
Video
75 Ohm
SI
12
11-0
300 pF
510 pF
300 pF
75 Ohm
AGND
13.500 MHz (D1)
14.318 MHz (NTSC D2)
27.000 MHz (D1)
28.636 MHz (NTSC D2)
65-2242C-13
Note: Data buses are unsigned binary.
Figure 13. Interpolating Digital Video Signals before Reconstruction
TCO = 0 RND = 110 SO(3:0) = 0011 DEC = 0 INT = 0
12
TMC2242C
PRODUCT SPECIFICATION
Notes:
13
PRODUCT SPECIFICATION
TMC2242C
Mechanical Dimensions – 44-Pin PLCC Package
Notes:
Inches
Millimeters
mbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982
Min.
Max.
Min.
Max.
2. Corner and edge chamfer (J) = 45°
.165
.090
.020
.013
.026
.685
.650
.180
.120
—
4.19
2.29
.51
4.57
3.05
—
3. Dimension D1 and E1 do not include mold protrusion. Allowable
protrusion is .101" (.25mm)
.021
.032
.695
.656
.33
.53
.66
.81
17.40
16.51
17.65
16.66
E1
E3
3
2
.500 BSC
.050 BSC
.042 .056
12.7 BSC
1.27 BSC
1.07 1.42
/NE
11
44
11
44
—
.004
—
0.10
E
E1
J
D
D1
D3/E3
B1
J
e
A1
– C – LEAD COPLANARITY
ccc C
B
A2
14
TMC2242C
PRODUCT SPECIFICATION
Mechanical Dimensions – 44-Lead MQFP Package
Notes:
Inches
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
2. Dimensions "D1" and "E1" do not include mold protrusion.
3. Pin 1 identifier is optional.
Min.
Max.
Min.
Max.
A
.077
.000
.077
.012
.005
.510
.390
.093
.010
.083
.018
.009
.530
.398
1.95
.00
2.35
.25
A1
A2
B
4. Dimension N: number of terminals.
1.95
.30
2.11
.46
5. Dimension ND: Number of terminals per package edge.
6. "L" is the length of terminal for soldering to a substrate.
7. "B" includes lead finish thickness.
7
2
C
.13
.23
D/E
D1/E1
e
12.95
9.90
13.45
10.10
.032 BSC
.81 BSC
6
4
5
L
.026
.037
.66
.94
N
44
11
44
11
ND
α
0°
7°
0°
7°
ccc
—
.004
—
0.10
D
D1
e
PIN 1
IDENTIFIER
E
E1
C
α
L
0.063" Ref (1.60mm)
See Lead Detail
Base Plane
A2
A
B
-C-
LEAD COPLANARITY
ccc
Seating Plane
A1
C
15
TMC2242C
PRODUCT SPECIFICATION
Ordering Information
Product Number
Temperature
Speed
Grade
Screening
Package
Package Marking
Range
TMC2242CR2C
TMC2242CR2C1
TMC2242CKTC
TMC2242CKTC1
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
40 MHz
60 MHz
40 MHz
60 MHz
Commercial
Commercial
Commercial
Commercial
44-Lead PLCC
44-Lead PLCC
44-Lead MQFP
44-Lead MQFP
2242CR2C
2242CR2C1
2242CKTC
2242CKTC1
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
6/1/99 0.0m 004
Stock#DS7002242C
1998 Fairchild Semiconductor Corporation
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