UC3843DX [FAIRCHILD]
Switching Controller, Current-mode, 1A, 500kHz Switching Freq-Max, BIPolar, PDSO14, SOP-14;
| 型号： | UC3843DX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Switching Controller, Current-mode, 1A, 500kHz Switching Freq-Max, BIPolar, PDSO14, SOP-14 开关 光电二极管 |
| 文件： | 总10页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
UC3842/UC3843/UC3844/UC3845
SMPS Controller
Features
Description
• Low Start Up Current
The UC3842/UC3843/UC3844/UC3845 are fixed
• Maximum Duty Clamp
frequency current-mode PWM controller. They are
• UVLO With Hysteresis
• Operating Frequency Up To 500KHz
specially designed for Off - Line and DC-to-DC converter
applications with minimum external components. These
integrated circuits feature a trimmed oscillator for precise
duty cycle control, a temperature compensated reference,
high gain error amplifier. current sensing comparator, and a
high current totempole output Ideally suited for driving a
power MOSFET. Protection circuity Includes built in
under-voltage lockout and current limiting. TheUC3842 and
UC3844 have UVLO thresholds of 16V (on) and 10V (off)
The UC3843 and UC3845 are 8.5V (on) and 7.9V (off) The
UC3842 and UC3843 can operate within 100% duty cycle.
The UC3844and UC3845 can operate with 50% duty cycle.
8-DIP
1
14-SOP
1
Internal Block Diagram
Rev. 1.0.0
©2001 Fairchild Semiconductor Corporation
UC3842/UC3843/UC3844/UC3845
Absolute Maximum Ratings
Parameter
Supply Voltage
Symbol
Value
Unit
V
V
30
CC
Output Current
I
O
±1
A
Analog Inputs (Pin 2.3)
Error Amp Output Sink Current
V
-0.3 to 6.3
V
(ANA)
I
10
1
mA
W
SINK (E.A)
Power Dissipation (T = 25°C)
P
D
A
2
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics
(V =15V, R =10KΩ, C =3.3nF, T = 0°C to +70°C, unless otherwise specified)
CC
T
T
A
Parameter
Symbol
Conditions
Min.
Typ. Max. Unit
REFERENCE SECTION
Reference Output Voltage
Line Regulation
V
T = 25°C, I
= 1mA
4.90
5.00
6
5.10
20
V
REF
J
REF
∆V
∆V
12V ≤ V
≤ 25V
-
-
-
mV
mV
mA
REF
REF
SC
CC
Load Regulation
1mA ≤ I
≤ 20mA
6
25
REF
Short Circuit Output Current
OSCILLATOR SECTION
Oscillation Frequency
I
T = 25°C
A
-100
-180
f
T = 25°C
J
47
-
52
0.05
1.6
57
1
KHz
%
Frequency Change with
Voltage
∆f/∆V
CC
12V ≤ V
≤ 25V
CC
Oscillator Amplitude
ERROR AMPLIFIER SECTION
Input Bias Current
V
-
-
-
V
P-P
OSC
I
-
-
2.42
65
60
2
-0.1
2.50
90
-2
µA
V
BIAS
Input Voltage
V
V
= 2.5V
2.58
I(E>A)
pin1
Open Loop Voltage Gain
Power Supply Rejection Ratio
Output Sink Current
Output Source Current
High Output Voltage
Low Output Voltage
CURRENT SENSE SECTION
Gain
G
2V ≤ V ≤ 4V
-
dB
dB
mA
mA
V
VO
O
PSRR
12V ≤ V
CC
≤ 25V
70
-
I
V
V
V
V
= 2.7V, V
= 2.3V, V
= 1.1V
= 5V
7
-
-
SINK
pin2
pin2
pin2
pin2
pin1
pin1
I
-0.6
5
-1.0
6
SOURCE
V
= 2.3V, R = 15KΩ to GND
-
OH
L
V
= 2.7V, R = 15KΩ to Pin 8
-
0.8
1.1
V
OL
L
G
(Note 1 & 2)
= 5V(Note 1)
2.85
3
1
3.15
1.1
-
V/V
V
V
Maximum Input Signal
Power Supply Rejection Ratio
Input Bias Current
V
V
0.9
I(MAX)
pin1
PSRR
12V ≤ V
≤ 25V (Note 1)
-
-
70
-3
dB
µA
CC
I
-
-10
BIAS
OUTPUT SECTION
I
I
I
I
= 20mA
-
-
0.08
1.4
0.4
2.2
-
V
V
SINK
SINK
V
OL
Low Output Voltage
High Output Voltage
= 200mA
= 20mA
13
12
-
13.5
13.0
45
V
SOURCE
SOURCE
V
OH
= 200mA
-
V
Rise Time
Fall Time
t
T = 25°C, C = 1nF (Note 3)
150
150
ns
ns
R
J
L
t
T = 25°C, C = 1nF (Note 3)
-
35
F
J
L
UNDER-VOLTAGE LOCKOUT SECTION
UC3842/UC3844
UC3843/UC3845
UC3842/UC3844
UC3843/UC3844
14.5
7.8
16.0
8.4
17.5
9.0
V
V
V
V
Start Threshold
V
TH(ST)
8.5
7.0
10.0
7.6
11.5
8.2
Min. Operating Voltage
(After Turn On)
V
OPR(MIN)
3
UC3842/UC3843/UC3844/UC3845
Electrical Characteristics (Continued)
(V =15V, R =10KΩ, C =3.3nF, T = 0°C to +70°C, unless otherwise specified)
CC
T
T
A
Parameter
Symbol
Conditions
Min.
Typ. Max. Unit
PWM SECTION
D
UC3842/UC3843
95
47
-
97
48
-
100
50
0
%
%
%
(max)
D
Max. Duty Cycle
UC3844/UC3845
Min. Duty Cycle
D
-
(MIN)
TOTAL STANDBY CURRENT
Start-Up Current
I
-
-
-
0.45
14
1
17
-
mA
mA
V
ST
Operating Supply Current
Zener Voltage
I
V
=V
=ON
= 25mA
CC
CC(OPR)
pin3 pin2
V
I
30
38
Z
Adjust V above the start threshould before setting at 15V
CC
Note:
1. Parameter measured at trip point of latch
2. Gain defined as:
∆Vpin1
A = -----------------
,0 ≤ Vpin3 ≤ 0.8V
∆Vpin3
3.These parameters, although guaranteed, are not 100 tested in production.
UC3842
Figure 1. Open Loop Test Circuit
High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors
should be connected close to pin 5 in a single point ground. The transistor and 5KΩ potentiometer are used to sample the
oscillator waveform and apply an adjustable ramp to pin 3.
4
UC3842/UC3843/UC3844/UC3845
UC3842/44
UC3843/45
Figure 2. Under Voltage Lockout
During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with
a bleeder resistor to prevent activating the power switch with output leakage current.
Figure 3. Error Amp Configuration
Figure 4. Current Sense Circuit
Peak current (I ) is determined by the formula:
S
1.0V
IS(MAX)= ------------
RS
A small RC filter may be required to suppress switch transients.
5
UC3842/UC3843/UC3844/UC3845
Figure 5. Oscillator Waveforms and Maximum Duty Cycle
Oscillator timing capacitor, C , is charged by V
through R , and discharged by an internal current source. During the
T
T
REF
discharge time, the internal clock signal blanks the output to the low state. Selection of R and C therefore determines both
T
T
oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas:
t = 0.55 R C
c
T
T
0.0063RT – 2.7
---------------------------------------
tD= RTCTIn
0.0063RT – 4
Frequency, then, is: f=(t + t )-1
c
d
1.8
ForRT > 5KΩ,f= --------------
RTCT
Figure 6. Oscillator Dead Time & Frequency
(Deadtime vs C RT > 5kΩ)
Figure 7. Timing Resistance vs Frequency
T
Figure 8. Shutdown Techniques
6
UC3842/UC3843/UC3844/UC3845
Shutdown of the UC3842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two
diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The
PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pins
1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SOR which will be
reset by cycling Voc below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.
UC3842/UC3843
Figure 9. Slope Compensation
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for
converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch
spikes.
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. TEMPERATURE DRIFT (Vref)
Figure 11. TEMPERATURE DRIFT (Ist)
TEMPERATURE (°C)
Figure 12. TEMPERATURE DRIFT (Icc)
7
UC3842/UC3843/UC3844/UC3845
Mechanical Dimensions
Package
8-DIP
6.40 ±0.20
0.252 ±0.008
#1
#4
#8
#5
3.30 ±0.30
0.130 ±0.012
5.08
MAX
0.200
7.62
3.40 ±0.20
0.134 ±0.008
0.300
0.33
0.013
MIN
+0.10
–0.05
0.25
+0.004
–0.002
0.010
8
UC3842/UC3843/UC3844/UC3845
Mechanical Dimensions (Continued)
Package
14-SOP
0.05
0.002
MIN
1.55 ±0.10
0.061 ±0.004
#14
#1
#8
#7
6.00 ±0.30
0.236 ±0.012
1.80
MAX
0.071
3.95 ±0.20
0.156 ±0.008
5.72
0.225
0.60 ±0.20
0.024 ±0.008
9
UC3842/UC3843/UC3844/UC3845
Ordering Information
Product Number
UC3842N
UC3843N
UC3844N
UC3845N
UC3842D
UC3843D
UC3844D
UC3845D
Package
Operating Temperature
8-DIP
0 ~ + 70°C
14-SOP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9/25/01 0.0m 001
Stock#DSxxxxxxxx
2001 Fairchild Semiconductor Corporation
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1A SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, CDIP8, MINI, CERAMIC, DIP-8
STMICROELECTR
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