USB1T11ABQX [FAIRCHILD]
Universal Serial Bus Transceiver; 通用串行总线收发器
| 型号： | USB1T11ABQX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Universal Serial Bus Transceiver |
| 文件： | 总11页 (文件大小：560K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1999
Revised March 2005
USB1T11A
Universal Serial Bus Transceiver
General Description
Features
The USB1T11A is a one chip generic USB transceiver. It is
designed to allow 5.0V or 3.3V programmable and stan-
dard logic to interface with the physical layer of the Univer-
sal Serial Bus. It is capable of transmitting and receiving
serial data at both full speed (12Mbit/s) and low speed
(1.5Mbit/s) data rates.
■ Complies with Universal Serial Bus specification 1.1
■ Utilizes digital inputs and outputs to transmit and receive
USB cable data
■ Supports 12Mbit/s “Full Speed” and 1.5Mbit/s
“Low Speed” serial data transmission
■ Compatible with the VHDL “Serial Interface Engine”
from USB Implementers' Forum
The input and output signals of the USB1T11A conform
with the “Serial Interface Engine”. Implementation of the
Serial Interface Engine along with the USB1T11A allows
the designer to make USB compatible devices with off-the-
shelf logic and easily modify and update the application.
■ Supports single-ended data interface
■ Single 3.3V supply
■ ESD Performance: Human Body Model
9.5 kV on D , D pins only
4 kV on all other pins
■ 16-lead Pb-Free MLP package saves space
Ordering Code:
Package
Order Number
Package Description
Number
USB1T11AM
(Note 1)
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
USB1T11AM_NL
(Note 2)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
USB1T11ABQX
MLP16C Pb-Free 16-Terminal Molded Leadless Package (MLP), JEDEC MO-220, 3mm square
USB1T11AMTC
(Note 1)
MTC14
MTC14
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
USB1T11AMTC_NL
(Note 2)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
USB1T11AMTCX_NL
(Note 2)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Pb-Free package per JEDEC J-STD-020B.
Note 1: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Note 2: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Please use order number as indicated.
The USB-IF Logos are trademarks of Universal Serial Bus Implementers Forum, Inc.
© 2005 Fairchild Semiconductor Corporation
DS500234
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Connection Diagrams
Logic Diagram
Pin Assignments for SOIC and TSSOP
Pin Assignments for MLP
Pin Descriptions
Pin Name
I/O
Description
RCV
O
Receive data. CMOS level output for USB differential input
OE
I
I
I
Output Enable. Active LOW, enables the transceiver to transmit data on the bus. When not
active the transceiver is in receive mode.
MODE
Mode. When left unconnected, a weak pull-up transistor pulls it to VCC and in this GND, the
VMO/FSEO pin takes the function of FSEO (Force SEO).
VPO, VMO/FSEO
Inputs to differential driver. (Outputs from SIE).
MODE
0
VPO
VMO/FSEO
RESULT
Logic “0”
SE0
0
0
1
1
0
1
0
1
Logic “1”
SEO
1
0
0
1
1
0
1
0
1
SE0
Logic “0”
Logic “1”
Illegal code
VP, VM
O
Gated version of D and D . Outputs are logic “0” and logic “1”. Used to detect single ended
zero (SE0), error conditions, and interconnect speed. (Input to SIE).
VP
VM
RESULT
0
0
1
1
0
1
0
1
SE0
Low Speed
Full Speed
Error
D , D
AI/O Data , Data . Differential data bus conforming to the Universal Serial Bus standard.
SUSPND
I
Suspend. Enables a low power state while the USB bus is inactive. While the suspend pin is
active it will drive the RCV pin to a logic “0” state. Both D and D are 3-STATE.
SPEED
I
Edge rate control. Logic “1” operates at edge rates for “full speed”.
Logic “0” operates edge rates for “low speed”.
VCC
3.0V to 3.6V power supply
Ground reference
GND
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2
Functional Truth Table
Input
I/O
Outputs
VP
VM
Mode
VPO
VMO/FSEO
OE
SUSPND
D
D
RCV
Result
0
0
0
0
0
0
1
0
0
1
Logic 0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
U
1
0
1
0
0
SEO
Logic 1
0
1
1
0
0
0
0
U
0
0
SEO
1
1
1
1
X
X
0
0
1
1
X
X
0
1
0
1
X
X
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
Z
Z
0
1
0
1
Z
Z
U
0
0
0
0
1
SEO
Logic 0
1
1
0
Logic 1
U
U
U
U
U
U
U
U
U
Illegal Code
D /D Hi-Z
D /D Hi-Z
X
Z
U
Don’t Care
3-STATE
Undefined State
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
DC Supply Voltage (VCC
DC Input Diode Current (IIK
VI
)
0.5V to 7.0V
)
Supply Voltage VCC
Input Voltage (VI)
3.0V to 3.6V
0V to 5.5V
0V to VCC
0V to VCC
0
50 mA
Input Voltage (VI)
(Note 4)
Input Range for AI/O (VAI/O
Output Voltage (VO)
)
0.5V to 5.5V
Input Voltage (VI/O
)
0.5V to VCC 0.5V
Operating Ambient Temperature
in free air (Tamb
Output Diode Current (IOK
)
)
40 C to 85 C
VO VCC or VO
Output Voltage (VO)
(Note 4)
0
50 mA
0.5V to VCC 0.5V
Output Source or Sink Current (IO)
VP.VM, RCV pins
VO 0 to VCC
15 mA
Output Source or Sink Current (IO)
D /D pins
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristic tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
VO 0 to VCC
50 mA
100 mA
V
CC or GND Current (ICC, IGND
)
Storage Temperature (TSTO
)
60 C to 150 C
Note 4: The input and output voltage ratings may be exceeded if the input
and output clamp current ratings are observed.
DC Electrical Characteristics (Digital Pins)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CC
3.0V to 3.6V
Limits
Symbol
Parameter
Test Conditions
Temp
Min
40 C to 85 C
Unit
Typ
Max
INPUT LEVELS:
V
V
LOW Level Input Voltage
HIGH Level Input Voltage
OUTPUT LEVELS:
0.8
V
V
IL
2.0
IH
V
LOW Level Output Voltage
I
I
I
I
4 mA
0.4
0.1
OL
OL
OL
OH
OH
V
V
20
A
V
HIGH Level Output Voltage
4 mA
2.4
OH
20
A
V
– 0.1
CC
LEAKAGE CURRENT:
Input Leakage Current
Supply Current (Full Speed)
Supply Current (Low Speed)
Quiescent Current
I
I
I
I
V
V
V
V
V
V
3.0 to 3.6
5
5
A
mA
mA
L
CC
CC
CC
CC
IN
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
CCFS
CCLS
CCQ
5
5
mA
A
V
or GND
CC
I
Supply Current in Suspend
3.0 to 3.6; Mode
V
CC
10
CCS
CC
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4
DC Electrical Characteristics (D /D Pins)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
3.0V to 3.6V
Limits
CC
Symbol
Parameter
Test Conditions
Temp
Min
40 C to 85 C
Units
Typ
Max
INPUT LEVELS:
V
V
V
Differential Input Sensitivity
Differential Common Mode Range
Single Ended Receiver Threshold
OUTPUT LEVELS:
|(D ) – (D )|
Includes V Range
0.2
0.8
0.8
V
V
V
DI
2.5
2.0
CM
SE
DI
V
V
V
Static Output LOW Voltage
Static Output HIGH Voltage
Differential Crossover
R
R
of 1.5 k to 3.6V
of 15 k to GND
0.3
3.6
2.0
V
V
V
OL
OH
CR
L
2.8
1.3
L
LEAKAGE CURRENT:
I
High Z State Data Line Leakage Current 0V
CAPACITANCE:
V
3.3V
5
A
OZ
IN
C
(Note 6)
Transceiver Capacitance
Capacitance Match
Pin to GND
10
10
pF
%
IN
OUTPUT RESISTANCE:
Z
(Note 5) Driver Output Resistance
Resistance Match
Steady State Drive
4
20
10
DRV
%
Note 5: Excludes external resistor. In order to comply with USB Specification 1.1, external series resistors of 24
1% each on D and D are recom-
mended. This specification is guaranteed by design and statistical process distribution.
Note 6: This specification is guaranteed by design and statistical process distribution.
AC Electrical Characteristics (D /D Pins, Full Speed)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CL 50 pF; RL 1.5 k on D to VCC
3.0V to 3.6V
CC
Limits
40 C to 85 C
Typ Max
Symbol
Parameter
Test Condition
Temp
Min
Units
DRIVER CHARACTERISTICS:
10% and 90%
ns
t
t
t
Rise Time
Figure 1
Figure 1
4
4
20
20
R
Fall Time
F
Rise/Fall Time Matching
Output Signal Crossover Voltage
DRIVER TIMINGS:
Driver Propagation Delay
(t /t )
90
1.3
110
2.0
%
V
RFM
r f
V
CRS
t
t
t
Figure 2
Figure 2
Figure 4
18
18
13
ns
ns
ns
PLH
PLH
PHZ
(VPO, VMO/FSEO to D /D
Driver Disable Delay
)
t
t
(OE to D /D
Driver Enable Delay
(OE to D /D
)
Figure 4
Figure 4
13
17
ns
ns
PLZ
PZH
t
)
Figure 4
17
ns
PZL
RECEIVER TIMINGS:
Receiver Propagation Delay
(D , D to RCV)
t
t
t
t
Figure 3
Figure 3
Figure 3
Figure 3
16
19
8
ns
ns
ns
ns
PLH
PHL
PLH
PHL
Single-ended Receiver Delay
(D , D to VP, VM)
8
5
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AC Electrical Characteristics (D /D Pins, Low Speed)
Over recommended range of supply voltage and operating free air temperature (unless otherwise noted). V
CL 200 pF to 600 pF; RL 1.5k on D to VCC
3.0V to 3.6V
CC
Limits
T
40 C to 85 C
Symbol
Parameter
Test Conditions
Unit
amb
Min
Typ
Max
DRIVER CHARACTERISTICS:
10% and 90%
t
t
t
Rise Time
Figure 1
Figure 1
75
75
80
1.3
300
300
120
2.0
ns
LR
Fall Time
LF
Rise/Fall Time Matching
Output Signal Crossover Voltage
DRIVER TIMINGS:
Driver Propagation Delay
(t /t )
%
V
RFM
r f
V
CRS
t
t
t
Figure 2
Figure 2
Figure 4
300
300
13
ns
ns
ns
PLH
PHL
PHZ
(VPO, VMO/FSEO to D /D
Driver Disable Delay
)
t
t
(OE to D /D
Driver Enable Delay
(OE to D /D
)
Figure 4
Figure 4
13
ns
ns
PLZ
205
PZH
t
)
Figure 4
205
ns
PZL
RECEIVER TIMINGS:
Receiver Propagation Delay
(D , D to RCV)
t
t
t
t
Figure 3
Figure 3
Figure 3
Figure 3
18
18
28
28
ns
ns
ns
ns
PLH
PHL
PLH
PHL
Single-ended Receiver Delay
(D , D to VP, VM)
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6
AC Waveforms
VOL and VOH are the typical output voltage drops that occur with the output load. (VCC never goes below 3.0V)
FIGURE 1. Rise and Fall Times
FIGURE 2. VPI, VMO/FSEO to D /D
FIGURE 3. D /D to RCV, VP/VM
FIGURE 4. OE to D /D
Test Circuits and Waveforms
Load for VM/VP and RCV
Load for Enable and Disable Times
Note:
V
V
0 for t
, t
PZH PHZ
V
for t
, t
PZL PLZ
CC
Load for D /D
Test
S1
CL 50 pF, Full Speed
D /LS Close
D /LS Open
D /FS Open
CL 200 pF, Low Speed (Min Timing)
CL 600 pF, Low Speed (Max Timing)
1.5 k on D (Low Speed) or D (Full Speed) only D /FS Close
7
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Tape and Reel Specification
Tape Format for MLP
Package
Tape
Number
Cavities
125 (typ)
2500
Cavity
Status
Empty
Filled
Cover Tape
Status
Designator
Section
Leader (Start End)
Sealed
BQX
Carrier
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
A
N
W1
W2
Tape Size
(mm)
(Typical)
(mm)
(mm)
(Max)
(mm)
12 mm
330
178
12.4
18.4
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8
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 16-Terminal Molded Leadless Package (MLP), JEDEC MO-220, 3mm square
Package Number MLP16C
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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相关型号：
USB1T11ABQX_NL
Bus Transceiver, USB Series, 1-Func, 1-Bit, True Output, 3 X 3 MM, LEAD FREE, MO-220, MLP-16
FAIRCHILD
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