FM8P756_技术文档

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OTP-Based 8-Bit Microcontroller with LCD Driver

FM8P756

Devices Included in this Data Sheet:

 FM8P756A : 24-pin OTP device

 FM8P756B : 20-pin OTP device

 FM8P756C : 16-pin OTP device

 FM8P756D : 28-pin OTP device with VR pin

 FM8P756E : 24-pin OTP device with VR pin

 FM8P756F : 18-pin OTP device with VR pin

 FM8P756G : 20-pin OTP device with VR pin

FEATURES

 Total 8 channel 10bit AD converter with ±2LSB resolution

 All instructions are single cycle except for program branches which are two-cycles

 All OTP area GOTO instruction

 All OTP area subroutine CALL instruction

 8-bit wide data path

 8-level deep hardware stack

 2K x 16 bits on chip OTP

 36x8 bits on chip special purpose registers and 96 x 8 bits on chip general purpose registers (SRAM)

 Operating speed: DC-20 MHz clock input, or DC-100 ns instruction cycle

 Direct, indirect addressing modes for data accessing

 Three real time down-count Timer/Counter with 3-bit programmable prescaler

- TMR1: 8-bit, PWM1 & Timer

- TMR2: 8-bit, PWM2 & Timer

- TMR3: 8-bit, Timer

 Software controlled 4-COM lines LCD driver with 1/2bias

 Built-in 3 levels Low Voltage Detector (LVDT) (2.2V/2.6V/3.7V) for Brown-out Reset (BOR)

 Power-up Reset Timer (PWRT)

 On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog

enable/disable control

 Three I/O ports Port A, Port B and Port C with independent direction control

- 21 Bi-direction I/O port (Programmable Pull-up enable in Input mode)

- One Input only port (IOA7/RSTB)

 Four kinds of interrupt source: 3 Timers/Counters, 8 external interrupt sources: IOA0~IOA7, Internal watchdog

timer (i_WDT) wakeup, and A/D end of conversion

 Wake-up from SLEEP:

- Port A (IOA0~IOA7) pin change wakeup

- WDT overflow

- i_WDT overflow

 Power saving SLEEP mode

 Programmable Code Protection

 Selectable oscillator options:

- ERC: External Resistor/ Voltage Controlled Oscillator

- XT: Crystal/Resonator Oscillator

- LF: Low Frequency Crystal Oscillator

- HIRC: Internal Resistor/Capacitor High speed Oscillator

- LIRC: Internal Resistor/Capacitor Low speed Oscillator

 Operating voltage range:

- ≤4MHz: 2.2V to 5.5V

- ≤8MHz: 2.4V to 5.5V, see 6.1 for more information.

This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.

No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.

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GENERAL DESCRIPTION

The FM8P756 is a low-cost, high speed, high noise immunity, OTP-based 8-bit CMOS microcontrollers. It

employs a RISC architecture with 54 instructions. All instructions are single cycle except for program branches

which take two cycles. The easy to use and easy to remember instruction set reduces development time

significantly.

The FM8P756 consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),

Watchdog Timer, OTP, SRAM, tri-state I/O port, I/O pull-high control, Power saving SLEEP mode, 3 real time

programmable clock/counter, Interrupt, Wake-up from SLEEP mode, and Code Protection for OTP products.

There are eight oscillator configurations to be chosen from, including the power-saving LF (Low Frequency)

oscillator and cost saving internal RC oscillator.

The FM8P756 address 2K×16 of program memory.

The FM8P756 can directly or indirectly address its register files and data memory. All special function registers

including the program counter are mapped in the data memory.

The FM8P756 provides total 8 channel 10bit AD converter with ±2LSB resolution.

The FM8P756 provides total 4 COM LCD pins, drive waveform is controlled by Software.

BLOCK DIAGRAM

Oscillator

Circuit

8-level

STACK

SRAM

FSR

Watchdog

Timer

Program

Counter

PORTA

PORTB

PORTC

Instruction

Decoder

ALU

OTP ROM

Interrupt

Control

8-bit TMR1~3

Accumulator

DATA BUS

Control

A/D

Converter

PWM

Controller

LCD ½ Bias

Converter

Interrupt

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PIN CONNECTION

PDIP24, SOP24

IOA3/ADC3/INT3

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

1

2

3

4

5

6

7

8

9

24 IOA4/ADC4/INT4/PWM1

23 IOA5/INT5/OSCO/CLO

22 IOA6/INT6/OSCI

21 IOA7/INT7/RSTB

20 VDD

IOC6

19 IOC5

FM8P756A

IOC7/ADC7

IOC0

18 IOC4

17 IOC3

IOC1

16 IOC2

IOB0/COM0 10

IOB1/COM1 11

IOB2/COM2 12

15 IOB5/ADC6

14 IOB4/ADC5/PWM2

13 IOB3/COM3

PDIP20, SOP20

IOA3/ADC3/INT3

1

2

3

4

5

6

7

8

9

20 IOA4/ADC4/INT4/PWM1

19 IOA5/INT5/OSCO/CLO

18 IOA6/INT6/OSCI

17 IOA7/INT7/RSTB

16 VDD

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

FM8P756B

IOC0

15 IOC3

IOC1

14 IOC2

IOB0/COM0

IOB1/COM1

13 IOB5/ADC6

12 IOB4/ADC5/PWM2

11 IOB3/COM3

IOB2/COM2 10

PDIP16, SOP16

IOA3/ADC3/INT3

1

2

3

4

5

6

7

8

16 IOA4/ADC4/INT4/PWM1

15 IOA5/INT5/OSCO/CLO

14 IOA6/INT6/OSCI

13 IOA7/INT7/RSTB

12 VDD

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

FM8P756C

IOB0/COM0

11 IOB5/ADC6

IOB1/COM1

10 IOB4/ADC5/PWM2

IOB2/COM2

9

IOB3/COM3

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FM8P756

PDIP28, SOP28 (With VR PIN)

IOA3/ADC3/INT3

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

1

2

3

4

5

6

7

8

9

28 IOA4/ADC4/INT4/PWM1

27 IOA5/INT5/OSCO/CLO

26 IOA6/INT6/OSCI

25 IOA7/INT7/RSTB

24 VR

IOC6

23 VDD

IOC7/ADC7

IOC0

22 IOC5

FM8P756D

21 IOC4

IOC1

20 IOC3

IOB0/COM0 10

IOB1/COM1 11

IOB2/COM2 12

NC 13

19 IOC2

18 IOB5/ADC6

17 IOB4/ADC5/PWM2

16 IOB3/COM3

15 NC

NC 14

PDIP24, SOP24 (With VR PIN)

IOA3/ADC3/INT3

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

1

2

3

4

5

6

7

8

9

24 IOA4/ADC4/INT4/PWM1

23 IOA5/INT5/OSCO/CLO

22 IOA6/INT6/OSCI

21 IOA7/INT7/RSTB

20 VR

IOC6

19 VDD

FM8P756E

IOC7/ADC7

IOC0

18 IOC4

17 IOC3

IOC1

16 IOC2

IOB0/COM0 10

IOB1/COM1 11

IOB2/COM2 12

15 IOB5/ADC6

14 IOB4/ADC5/PWM2

13 IOB3/COM3

PDIP20, SOP20 (With VR PIN)

IOA3/ADC3/INT3

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

1

2

3

4

5

6

7

8

9

20 IOA4/ADC4/INT4/PWM1

19 IOA5/INT5/OSCO/CLO

18 IOA6/INT6/OSCI

17 IOA7/INT7/RSTB

16 VR

FM8P756G

IOC0

15 VDD

IOC1

14 IOC2

IOB0/COM0

13 IOB5/ADC6

IOB1/COM1

12 IOB4/ADC5/PWM2

11 IOB3/COM3

IOB2/COM2 10

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FM8P756

PDIP18, SOP18 (With VR PIN)

IOA3/ADC3/INT3

IOA2/ADC2/INT2/TMCKI

IOA1/ADC1/INT1

IOA0/ADC0/INT0

VSS

1

2

3

4

5

6

7

8

9

18 IOA4/ADC4/INT4/PWM1

17 IOA5/INT5/OSCO/CLO

16 IOA6/INT6/OSCI

15 IOA7/INT7/RSTB

14 VR

FM8P756F

IOC1

13 VDD

IOB0/COM0

12 IOB5/ADC6

IOB1/COM1

11 IOB4/ADC5/PWM2

10 IOB3/COM3

IOB2/COM2

PIN DESCRIPTIONS

Name

I/O

Description

 Bi-direction I/O port (programmable Pull-high in Input mode)

 Wake-up on pin change

IOA0/AD0/INT0

|

I/O  External interrupt input

IOA4/AD4/INT4

 A/D converter input

 IOA4 is PWM1 output

 Bi-direction I/O port (programmable Pull-high in Input mode)

 Wake-up on pin change

I/O  External interrupt input

IOA5/INT5

/OSCO

 Clock output shared with IOA5

 Oscillator output (XT, LF, ERC mode)

 Bi-direction I/O port (programmable Pull-high in Input mode)

IOA6/INT6

/OSCI

 Wake-up on pin change

 External interrupt input

I/O

 Oscillator input (XT, LF, ERC mode)

 Input port

 Wake-up on pin change

 External interrupt input

 System clear (RESET) input. This pin is an active low RESET to the device.

The voltage on this pin must not exceed VDD.

IOA7/INT7

/RSTB

I

IOB0/COM0

 Bi-direction I/O port (programmable Pull-high in Input mode)

 Software controlled 1/2bias LCD COM0 ~ COM3 output

|

IOB3/COM3

IOB4/AD5

|

IOB5/AD6

IOC0

I/O

 Bi-direction I/O port (programmable Pull-high in Input mode)

I/O  IOB4 is PWM2 output

 A/D converter input

 Bi-direction I/O port (programmable Pull-high in Input mode)

 LCD segment output

|

I/O

IOC6

 Bi-direction I/O port (programmable Pull-high in Input mode)

I/O  LCD segment output

IOC7/ADC7

 A/D converter input

VR

-

ADC module reference input. The voltage on this pin must not exceed VDD.

VDD

VSS

Positive supply

Ground

Legend: I=input, O=output, I/O=input/output

Note: Please refer to 2.2 for detail IO type description

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1.0 MEMORY ORGANIZATION

FM8P756 memory is organized into program memory and data memory.

1.1 Program Memory Organization

The FM8P756 has a 11-bit Program Counter capable of addressing a 2K×16 program memory space.

The RESET vector for the FM8P756 is at 000h.

The H/W interrupt vector is at 004h.

FM8P756 supports all OTP area CALL/GOTO instructions without page.

Figure 1.1: Program Memory Map and STACK

PC<10:0>

Stack 1

Stack 2

Stack 3

Stack 4

Stack 5

Stack 6

Stack 7

Stack 8

7FFh

:

004h H/W Interrupt Vector

000h

Reset Vector

FM8P756

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1.2 Data Memory Organization

Data memory is composed of 36 bytes Special Function Registers and 96 bytes General Purpose Registers.

The data memory can be accessed either directly or indirectly through the FSR register.

Table 1.1: Registers File Map for FM8P756

Address

Description

00h

:

Special Purpose

Register

2Ch

40h

:

General Purpose

Register

9Fh

Table 1.2: Special Purpose Registers Map

Address

System

Name

B7

B6

B5

B4

B3

B2

B1

B0

00h (r/w)

01h (r/w)

02h (r/w)

03h (r/w)

04h (r/w)

INDF

PCL

Uses contents of FSR to address data memory (not a physical register)

Low order 8 bits of PC

PCHBUF

STATUS

FSR

-

High order 3 bits of PC

DC C

̅̅̅̅

PD

TO

Z

Indirect data memory address pointer

IO PAD & CONTROL

05h (r/w)

06h (r/w)

07h (r/w)

08h (r/w)

09h (r/w)

0Ah (r/w)

IOSTA

PORTA

IOSTB

PORTB

IOSTC

PORTC

-

IOSTA6 IOSTA5 IOSTA4 IOSTA3 IOSTA2 IOSTA1 IOSTA0

IOA7

IOA6

IOA5

IOSTB5 IOSTB4 IOSTB3 IOSTB2 IOSTB1 IOSTB0

IOB5 IOB4 IOB3 IOB2 IOB1 IOB0

IOA4

IOA3

IOA2

IOA1

IOA0

-

IOSTC7 IOSTC6 IOSTC5 IOSTC4 IOSTC3 IOSTC2 IOSTC1 IOSTC0

IOC7

IOC6

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

Timer1: 8-bit Timer & PWM1 Duty

10h (r/w) T1CON T1EN

-

T1SO1

T1SO0

-

T1EDG

PIR13

T1PS2

PIR12

T1PS1

PIR11

T1PS0

PIR10

11h (r/w) PWM1CON T1MOD PWM1S EPWM1

12h (r/w)

2Bh (r)

T1LA

8-bit real-time timer/counter latch

8-bit real time timer/counter Count

T1CNT

Timer2: 8-bit Timer & PWM2 Duty

13h (r/w) T2CON T2EN

14h (r/w) PWM2CON T2MOD PWM2S EPWM2

-

T2SO1

T2SO0

-

T2EDG

PIR23

T2PS2

PIR22

T2PS1

PIR21

T2PS0

PIR20

15h (r/w)

2Ch (r)

T2LA

8-bit real-time timer/counter latch

8-bit real time timer/counter Count

T2CNT

Timer3: 8-bit Timer

16h (r/w)

17h (r/w)

18h (r)

T3CON

T3EN

T3LOAD T3SO1

T3SO0

T3EDG

T3PS2

T3PS1

T3PS0

T3LA

8-bit real-time timer/counter latch

8-bit real-time timer/counter Count

T3CNT

IRQ

19h (r/w)

1Ah (r/w)

INTEN

GIE

-

ADCIE

ADCIF

PAIE

PAIF

COMIE

COMIF

-

T3IE

T3IF

T2P2IE T1P1IE

T2P2IF T1P1IF

INTFLAG

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Address

ADC Control

1Bh (r/w)

1Ch (r/w)

1Dh (r/w)

1Eh (r)

Name

B7

B6

B5

B4

B3

B2

B1

B0

ADCON1

ADCON2

ADCON3

ADDATL

ADDATH

ADCEN

-

CHSL2

-

CHSL1

CHSL0

-

CLKSL1 CLKSL0

-

ANISL3 ANISL2 ANISL1 ANISL0

D1

D9

D0

D8

-

1Fh (r)

D7

D6

D5

D4

D3

D2

Software LCD

20h (r/w) COMCON1

-

COM3E COM2E COM1E COM0E

21h (r/w) COMCON2 COMEN

Others

22h (r/w)

COMIS1 COMIS0 COMCK2 COMCK1 COMCK0

SYSCLK

CLOCON

APHCON

BPHCON

CPHCON

INTPA

CLKS

-

IRCPD ECLKPD

23h (r/w)

25h (r/w)

26h (r/w)

27h (r/w)

28h (r/w)

29h (r/w)

2Ah (r/w)

CLOEN

-

EXCLK

PHA5

PHB5

PHC5

DINV

PHA4

PHB4

PHC4

DUTY CLOPS2 CLOPS1 CLOPS0

-

PHA6

-

PHA3

PHB3

PHC3

PHA2

PHB2

PHC2

PHA1

PHB1

PHC1

PHA0

PHB0

PHC0

PHC7

PHC6

PA7IEN PA6IEN PA5IEN PA4IEN PA3IEN PA2IEN PA1IEN PA0IEN

WDTCON WDTEN I_WDT I_TWDT

TAB_BNK

-

WDTPS2 WDTPS1 WDTPS0

BNK2 BNK1 BNK0

-

Legend: - = unimplemented, read as ‘0’.

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2.0 FUNCTIONAL DESCRIPTIONS

2.1 Operational Registers

2.1.1

INDF (Indirect Addressing Register)

Address

00h (r/w)

Name

INDF

B7

B6

B5

B4

B3

B2

B1

B0

Uses contents of FSR to address data memory (not a physical register)

The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the

register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to

the INDF register indirectly results in a no-operation (although status bits may be affected).

Example 2.1: INDIRECT ADDRESSING

Register file 48 contains the value 10h

Register file 49 contains the value 0Ah

Load the value 48 into the FSR Register

A read of the INDF Register will return the value of 10h

Increment the value of the FSR Register by one (@FSR=49h)

A read of the INDF register now will return the value of 0Ah.

Figure 2.1: Direct/Indirect Addressing for FM8P756

Direct Addressing

From opcode

Indirect Addressing

From FSR register

7

0

7

0

00h

location select

addressing INDF register

location select

9Fh

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2.1.2

PCL / PCHBUF (Low / High Bytes of Program Counter) & Stack

Address

Name

PCL

B7

B6

-

B5

-

B4

B3

B2

B1

B0

01h (r/w)

02h (r/w)

Low order 8 bits of PC

PCHBUF

-

High order 3 bits of PC

Legend: - = unimplemented, read as ‘0’.

FM8P756 devices have an 11-bits wide Program Counter (PC) and eight-level deep 11-bit hardware push/pop

stack. This 11-bits Program Counter can be accessed and controlled by two registers, PCHBUF and PCL. The

low byte of PC control register is called the PCL. This register is readable and writable. The high byte of PC

control register is called the PCHBUF. This register contains the PC<10:8> bits also readable or writable.

The PCL and PCHBUF registers normally indicate the value of Program Counter. But when interrupt occurrence

and execution of RETF and RETFIE, the PCHBUF data would not be update.

Any address within the program memory can be written into PCL and PCHBUF registers. If the PCHBUF

register been changed and different from Program Counter., the value of PCHBUF register updated only when

execute GOTO, CALL, RETURN, or PCL value changed or increases from 0xff to 0x00. Once the value of PCL

register changed, the program and Program Counter will jump to the location indicated by PCL and PCHBUF

register.

Figure 2.2: Loading of PC in Different Situations

Situation 1: GOTO Instruction

PCH

9

PCL

10

-

8

-

7

-

0

PC

Opcode <10:0>

Opcode <10:8>

PCHBUF

-

Situation 2: CALL Instruction

STACK<10:0>

PCH

PCL

10

-

9

8

-

7

-

0

PC

Opcode <10:0>

Opcode <10:8>

PCHBUF

-

Situation 3: RETURN, RETF, RETIA or RETFIE Instruction

STACK<10:0>

PCH

9

PCL

10

-

8

-

7

-

0

PC

PCHBUF

-

STACK <10:8>

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FM8P756

Situation 4: Instruction with PCL as destination

PCH

9

PCL

10

8

7

0

PC

ALU result <7:0>

Or Opcode <7:0>

ALU result Carry

PCHBUF

-

2.1.3

STATUS (Status Register)

Address

03h (r/w)

Name

B7

-

B6

-

B5

-

B4

B3

̅̅̅̅

PD

B2

Z

B1

B0

C

̅̅̅̅

STATUS

TO

DC

Legend: - = unimplemented, read as ‘0’.

This register contains the arithmetic status of the ALU, the RESET status.

If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these

̅̅̅̅

three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and

̅̅̅̅

PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be

different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves

the STATUS Register as 000u u1uu (where u = unchanged).

C : Carry/borrow bit.

ADDAR

= 1, Carry occurred.

= 0, No Carry occurred.

SUBAR

= 1, No borrow occurred.

= 0, Borrow occurred.

Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR,

RLR) instructions, this bit is loaded with either the high or low order bit of the source register.

DC : Half carry/half borrow bit

ADDAR

= 1, Carry from the 4th low order bit of the result occurred.

= 0, No Carry from the 4th low order bit of the result occurred.

SUBAR

= 1, No Borrow from the 4th low order bit of the result occurred.

= 0, Borrow from the 4th low order bit of the result occurred.

Z : Zero bit.

= 1, The result of a logic operation is zero.

= 0, The result of a logic operation is not zero.

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FM8P756

̅̅̅̅

PD : Power down flag bit.

= 1, after power-up or by the CLRWDT instruction.

= 0, by the SLEEP instruction.

̅̅̅̅

TO : Watch-dog timer overflow flag bit.

= 1, after power-up or by the CLRWDT or SLEEP instruction

= 0, a watch-dog time overflow occurred

2.1.4

FSR (Indirect Data Memory Address Pointer)

Address

04h (r/w)

Name

FSR

B7

B6

B5

B4

B3

B2

B1

B0

Indirect data memory address pointer

Bit7:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.

2.1.5

PORTA, PORTB, PORTC, IOSTA, IOSTB and IOSTC (Port Data Registers and Port Direction

Control Registers)

Address

Name

IOSTA

PORTA

IOSTB

PORTB

IOSTC

PORTC

B7

B6

B5

B4

B3

B2

B1

B0

05h (r/w)

06h (r/w)

07h (r/w)

08h (r/w)

09h (r/w)

0Ah (r/w)

-

IOSTA6 IOSTA5 IOSTA4 IOSTA3 IOSTA2 IOSTA1 IOSTA0

IOA7*

IOA6

IOA5

IOSTB5 IOSTB4 IOSTB3 IOSTB2 IOSTB1 IOSTB0

IOB5 IOB4 IOB3 IOB2 IOB1 IOB0

IOA4

IOA3

IOA2

IOA1

IOA0

-

IOSTC7 IOSTC6 IOSTC5 IOSTC4 IOSTC3 IOSTC2 IOSTC1 IOSTC0

IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0

Legend: - = unimplemented, read as ‘0’.

The registers (IOSTA, IOSTB and IOSTC) are used to define the input or output of each port.

= 1, Input.

= 0, Output.

Reading the port (PORTA, PORTB and PORTC register) reads the status of the pins independent of the pin’s

input/output modes. Writing to these ports will write to the port data latch. Please refer to 2.2 for detail I/O Port

description.

Note: IOA7 is read only.

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2.1.6

TMR1: 8-bit Timer & PWM1 Duty

The Timer1 is an 8-bit down count timer/counter which includes counter register (T1CNT), and latch register

(T1LA). Please refer to 2.3 for detail Timer description.

The Timer1 can also be PWM1 and controlled by the register PWM1CON. Please refer to 2.4 for detail PWM

description.

2.1.6.1 T1CON (Timer1 Control Register)

Address

10h (r/w)

Name

B7

B6

-

B5

B4

B3

B2

B1

B0

T1CON

T1EN

T1SO1

T1SO0

T1EDG

T1PS2

T1PS1

T1PS0

Legend: - = unimplemented, read as ‘0’.

T1EN : TMR1 Enable/Disable

= 1, TMR1 (PWM1) Enable.

= 0, TMR1 (PWM1) Disable.

T1SO1:T1SO0 : TMR1 clock source selection

T1SO1

T1SO0

TMR1 clock source

0

1

0

1

0

1

TMCKI(IOA2)

Crystal mode OSCI or LIRC

Internal 8MHz RC or ERC

8 MHz IRCx2

Note: Please refer 2.3 for detail description.

T1EDG : TMR1 clock edge selection. This bit works only when external clock source TMCKI (IOA2) selected.

= 1, TMR1 decreased while external clock H→L (Falling edge).

= 0, TMR1 decreased while external clock L→H (Rising edge).

T1PS2:T1PS0 : TMR1 Prescaler selection

T1PS2 : T1PS0

TMR1 Prescal rate

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

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2.1.6.2 PWM1CON (PWM1 Control Register)

Address

Name

B7

B6

B5

B4

-

B3

B2

B1

B0

11h (r/w) PWM1CON T1MOD PWM1S EPWM1

PIR13

PIR12

PIR11

PIR10

Legend: - = unimplemented, read as ‘0’.

T1MOD : TMR1 operation mode select bit.

= 1, The TMR1 in PWM mode operation.

= 0, The TMR1 in Timer mode operation.

PWM1S : Initial State of PWM1 output duty.

= 1, Set the initial state to L, change to H when TMR1 duty underflow.

= 0, Set the initial state to H, change to L when TMR1 duty underflow.

EPWM1 : Extension PWM mode selection

= 1, PWM1 is Extension PWM mode.

= 0, PWM1 is normal PWM mode.

Note: Please refer to 2.4 for detail PWM description.

PIR13:PIR10 : Interrupt Event Rate of PWM1.

“1:N” means interrupt occurred after “N” PWM1 pulses.

PIR13 : PIR10

PWM1 Interrupt rate

0

1

0

1

0

1

1:1

1:2

1:3

1:4

|

1

0

1

0

1

1:14

1:15

1:16

2.1.6.3 T1LA (Timer1 Latch Register)

Address

12h (r/w)

Name

T1LA

B7

B6

B5

B4

B3

B2

B1

B0

8-bit real-time timer/counter latch

T1LA is a Timer1 pre-set latch buffer, see 2.3 for detail description.

2.1.6.4 T1CNT (Timer1 Counter Register)

Address

2Bh (r)

Name

B7

B6

B5

B4

B3

B2

T1CNT

8-bit real-time timer/counter Count

T1CNT is a Timer1 real-time counter, this register is only read, see 2.3 for detail description.

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2.1.7

TMR2: 8-bit Timer & PWM2 Duty

The Timer2 is an 8-bit down count timer/counter which includes counter register (T2CNT), and latch register

(T2LA). Please refer to 2.3 for detail Timer description.

The Timer2 can also be PWM2 and controlled by the register PWM2CON. Please refer to 2.4 for detail PWM

description.

2.1.7.1 T2CON (Timer2 Control Register)

Address

13h (r/w)

Name

B7

B6

-

B5

B4

B3

B2

B1

B0

T2CON

T2EN

T2SO1

T2SO0

T2EDG

T2PS2

T2PS1

T2PS0

Legend: - = unimplemented, read as ‘0’.

T2EN : TMR2 Enable/Disable

= 1, TMR2 (PWM2) Enable.

= 0, TMR2 (PWM2) Disable.

T2SO1:T2SO0 : TMR2 clock source selection

T2SO1

T2SO0

TMR2 clock source

0

1

0

1

0

1

TMCKI(IOA2)

Crystal mode OSCI or LIRC

Internal 8MHz RC or ERC

8MHz IRCx2

Note: Please refer 2.3 for detail description.

T2EDG : TMR2 clock edge selection. This bit works only when external clock source TMCKI (IOA2) selected.

= 1, TMR2 decreased while external clock H→L (Falling edge).

= 0, TMR2 decreased while external clock L→H (Rising edge).

T2PS2:T2PS0 : TMR2 Prescaler selection

T2PS2 : T2PS0

TMR2 Prescal rate

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

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2.1.7.2 PWM2CON (PWM2 Control Register)

Address

Name

B7

B6

B5

B4

-

B3

B2

B1

B0

14h (r/w) PWM2CON T2MOD PWM2S EPWM2

PIR23

PIR22

PIR21

PIR20

Legend: - = unimplemented, read as ‘0’.

T2MOD : TMR2 operation mode select bit.

= 1, The TMR2 in PWM mode operation.

= 0, The TMR2 in Timer mode operation.

PWM2S : Initial State of PWM2 output duty.

= 1, Set the initial state to L, change to H when TMR2 duty underflow.

= 0, Set the initial state to H, change to L when TMR2 duty underflow.

EPWM2 : Extension PWM mode selection

= 1, PWM2 is Extension PWM mode.

= 0, PWM2 is normal PWM mode.

Note: Please refer to 2.4 for detail PWM description.

PIR23:PIR20 : Interrupt Event Rate of PWM2.

“1:N” means interrupt occurred after “N” PWM2 pulses.

PIR23 : PIR20

PWM2 Interrupt rate

0

1

0

1

0

1

1:1

1:2

1:3

1:4

|

1

0

1

0

1

1:14

1:15

1:16

2.1.7.3 T2LA (Timer2 Latch Register)

Address

15h (r/w)

Name

T2LA

B7

B6

B5

B4

B3

B2

B1

B0

8-bit real-time timer/counter latch

T2LA is a Timer2 pre-set latch buffer, see 2.3 for detail description.

2.1.7.4 T2CNT (Timer2 Counter Register)

Address

2Ch (r)

Name

B7

B6

B5

B4

B3

B2

T2CNT

8-bit real-time timer/counter Count

T2CNT is a Timer2 real-time counter, this register is only read, see 2.3 for detail description.

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2.1.8

TMR3: 8-bit Timer

The Timer3 is an 8-bit down count timer/counter which includes counter register (T3CNT), and latch register

(T3LA). Please refer to 2.3 for detail Timer description.

2.1.8.1 T3CON (Timer3 Control Register)

Address

16h (r/w)

Name

B7

B6

B5

B4

B3

B2

B1

B0

T3CON

T3EN

T3LOAD T3SO1

T3SO0

T3EDG

T3PS2

T3PS1

T3PS0

T3EN : TMR3 Enable/Disable

= 1, TMR3 Enable.

= 0, TMR3 Disable.

T3LOAD : Enable/Disable Latch Buffer automatically load to counter register while writing to latch register

= 1, Enable TMR3 latch buffer automatically load to counter register while writing to latch register.

= 0, Disable TMR3 latch buffer automatically load to counter register while writing to latch register.

Note: This bit is only affected after latch register written. When the timer underflows, the latch

register data will automatically load into counter register.

T3SO1:T3SO0 : TMR3 clock source selection

T3SO1

T3SO0

TMR3 clock source

0

1

0

1

0

1

TMCKI(IOA2)

Crystal mode OSCI or LIRC

Internal 8MHz RC or ERC

Not function, don’t use.

Note: Please refer 2.3 for detail description.

T3EDG : TMR3 clock edge selection. This bit works only when external clock source TMCKI (IOA2) selected.

= 1, TMR3 decreased while external clock H→L (Falling edge).

= 0, TMR3 decreased while external clock L→H (Rising edge).

2.1.8.2 T3LA (Timer3 Latch Register)

Address

17h (r/w)

Name

T3LA

B7

B6

B5

B4

B3

B2

B1

B0

8-bit real-time timer/counter latch

T3LA is a Timer3 pre-set latch buffer, see 2.3 for detail description.

2.1.8.3 T3CNT (Timer3 Counter Register)

Address

18h (r)

Name

B7

B6

B5

B4

B3

B2

T3CNT

8-bit real-time timer/counter Count

T3CNT is a Timer3 real-time counter, this register is only read, see 2.3 for detail description.

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T3PS2:T3PS0 : TMR3 Prescaler selection

T3PS2 : T3PS0

TMR3 Prescal rate

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

2.1.9

INTEN (Interrupt Mask Register)

Address

19h (r/w)

Name

B7

B6

ADCIE

B5

PAIE

B4

B3

-

B2

B1

B0

INTEN

GIE

COMIE

T3IE

T2P2IE T1P1IE

Legend: - = unimplemented, read as ‘0’.

GIE : Global interrupt enable bit.

= 1, Enable all un-masked interrupts.

= 0, Disable all interrupts.

Note : When an interrupt event occurred with the GIE bit and its corresponding interrupt enable bits are set,

the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will

exit the interrupt routine and set the GIE bit to re-enable interrupt.

ADCIE : ADC conversion completed interrupt enable bit.

= 1, Enable interrupt.

= 0, Disable interrupt.

PAIE : PORTA interrupt enable

= 1, Enable interrupt.

= 0, Disable interrupt.

COMIE : LCD COM interrupt enable bit.

= 1, Enable interrupt.

= 0, Disable interrupt.

T3IE : Timer3 underflow interrupt enable bit.

= 1, Enable interrupt.

= 0, Disable interrupt.

T2P2IE : Timer2 / PWM2 underflow interrupt enable bit.

= 1, Enable interrupt.

= 0, Disable interrupt.

T1P1IE : Timer1 / PWM1 underflow interrupt enable bit.

= 1, Enable interrupt.

= 0, Disable interrupt.

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2.1.10 INTFLAG (Interrupt Status Register)

Address

Name

B7

-

B6

B5

B4

B3

-

B2

B1

B0

1Ah (r/w)

INTFLAG

ADCIF

PAIF

COMIF

T3IF

T2P2IF

T1P1IF

Legend: - = unimplemented, read as ‘0’.

ADCIF : ADC Interrupt flag. Set when ADC conversion is completed, reset by software.

PAIF : Port A <7:0> Interrupt flag. Set when pin changed on selected I/O by register INTPA, reset by software.

COMIF : LCD COM interrupt flag. Set when LCD clock overflows, and reset by software.

T3IF : TMR3 interrupt flag. Set when TMR3 underflows, and reset by software.

T2P2IF : TMR2 or PWM2 interrupt flag. Set when TMR2 underflows or PWM2 pulse counts to selected

interrupt rate, and reset by software.

T1P1IF : TMR1 or PWM1 interrupt flag. Set when TMR1 underflows or PWM1 pulse counts to selected

interrupt rate, and reset by software.

Note : BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).

2.1.11 ADCON1 (AD converter Control Register1)

Address

Name

B7

B6

-

B5

-

B4

-

B3

-

B2

B1

B0

1Bh (r/w)

ADCON1

ADCEN

CHSL2

CHSL1

CHSL0

Legend: - = unimplemented, read as ‘0’.

ADCEN : ADC enable/disable setting

= 1, Enable.

= 0, Disable.

Note : This bit should be set by software and would be reset by hardware after the ADC end of

conversion.

CHSL2:CHSL0 : ADC input channel select

CHSL2 CHSL1 CHSL0

Input channel

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Channel 0, IOA0 pin

Channel 1, IOA1 pin

Channel 2, IOA2 pin

Channel 3, IOA3 pin

Channel 4, IOA4 pin

Channel 5, IOB4 pin

Channel 6, IOB5 pin

Channel 7, IOC7 pin

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2.1.12 ADCON2 (AD converter Control Register2)

Address

Name

B7

-

B6

-

B5

-

B4

-

B3

-

B2

-

B1

B0

1Ch (r/w)

ADCON2

CLKSL1 CLKSL0

Legend: - = unimplemented, read as ‘0’.

CLKSL1:CLKSL0 : ADC Conversion clock source select bits.

CKSL1

CKSL0

Conversion clock

0

1

0

1

0

1

System clock / 2 (fastest result, lowest quality)

System clock / 8

System clock / 32

System clock / 128 (slowest result, best quality)

Note : This clock is used to control the conversion precision and speed. The precision will be dropped off if

faster conversion rate been used. The lowest conversion rate would be recommended in order to acquire

most accurate data.

2.1.13 ADCON3 (AD converter Control Register3)

Address

Name

B7

-

B6

-

B5

-

B4

-

B3

B2

B1

B0

1Dh (r/w)

ADCON3

ANISL3 ANISL2 ANISL1 ANISL0

Legend: - = unimplemented, read as ‘0’.

ANISL3:ANISL0 : Analog input select bits.

ANISL3 ANISL2 ANISL1 ANISL0

Analog input selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

All the ports are digital input

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Other

No function, don’t use.

Note : To minimize power consumption, all the I/O pins should be carefully managed before entering sleep mode.

2.1.14 ADDATL, ADDATH (AD conversion data high-byte and low-byte Register)

Address

1Eh (r)

1Fh (r)

Name

B7

D1

D9

B6

D0

D8

B5

-

B4

-

B3

-

B2

-

B1

-

B0

-

ADDATL

ADDATH

D7

D6

D5

D4

D3

D2

Legend: - = unimplemented, read as ‘0’.

The ADDATL and ADDATH registers is ADC conversion result. When ADC conversion is completed, the result is

loaded into ADDATL and ADDATH, the ADCEN bit will be cleared, and the ADCIF bit will be set (if ADCIE are set).

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2.1.15 Software Controlled LCD Module

Address

Name

B7

-

B6

B5

B4

-

B3

B2

B1

B0

20h (r/w) COMCON1

-

COM3E COM2E COM1E COM0E

21h (r/w) COMCON2 COMEN

COMIS1 COMIS0 COMCK2 COMCK1 COMCK0

Legend: - = unimplemented, read as ‘0’.

The pins IOB0~IOB3 on port B can be used as COM lines to drive an external LCD panels. To implement this

function, the COMCON1 and COMCON2 registers used to setup the correct bias voltage on these pins.

2.1.15.1 COMCON1 (Software LCD COM Control Register1)

COM0E : IOB0 / COM0 Selection bit.

= 1, IOB0 is normal I/O.

= 0, IOB0 is COM0, 1/2 VDD output (in LCD mode).

COM1E : IOB1 / COM1 Selection bit.

= 1, IOB1 is normal I/O.

= 0, IOB1 is COM1, 1/2 VDD output (in LCD mode).

COM2E : IOB2 / COM2 Selection bit.

= 1, IOB2 is normal I/O.

= 0, IOB2 is COM2, 1/2 VDD output (in LCD mode).

COM3E : IOB3 / COM3 Selection bit.

= 1, IOB3 is normal I/O.

= 0, IOB3 is COM3, 1/2 VDD output (in LCD mode).

2.1.15.2 COMCON2 (Software LCD COM Control Register2)

Address

Name

B7

B6

-

B5

-

B4

B3

B2

B1

B0

21h (r/w) COMCON2 COMEN

COMIS1 COMIS0 COMCK2 COMCK1 COMCK0

Legend: - = unimplemented, read as ‘0’.

COMEN : COM module enable/disable bit.

= 1, Enable COM module.

= 0, Disable COM module.

COMIS1:COMIS0 : COMn operating current selection (VDD = 5V).

COMIS1

COMIS0

COMn operating current

0

1

0

1

0

1

25uA

50uA

100uA

200uA

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FM8P756

COMCK2:COMCK0 : COMn turn-on time selection (interrupt).

COMCK2 : COMCK0

COMn Clock prescaler

0

1

0

1

0

System clock / 1024

System clock / 2048

System clock / 4096

System clock / 8192

System clock / 4

0

1

0

1

0

1

0

1

System clock / 8

System clock / 16

System clock / 32

2.1.16 SYSCLK (System Clock Control Register)

Address

22h (r/w)

Name

B7

B6

-

B5

-

B4

-

B3

-

B2

-

B1

B0

SYSCLK

CLKS

IRCPD ECLKPD

Legend: - = unimplemented, read as ‘0’.

The FM8P756 could be operated either dual or single clock system selected by configuration words. Please

refer to 2.14 for detail configuration selection description. This register is used to control the switch between

different system clocks and power-down function of those clocks.

CLKS : System Clock Selection (only valid in dual clock mode)

= 1, System Clock is External OSC/LIRC.

= 0, System Clock is Internal 8MHz or 4MHz RC.

IRCPD : Internal RC Power down Control (only valid in dual clock mode)

= 1, Internal 8MHz or 4MHz RC Power Down.

= 0, Internal 8MHz or 4MHz RC Power ON.

Note: Make sure the system clock been switch to external OSC/RC before power down internal 8MHz

or 4MHz RC.

ECLKPD : External clock (OSC/LIRC) Power down Control (only valid in dual clock mode)

= 1, External OSC/LIRC Power Down.

= 0, External OSC/LIRC Power ON.

Note: Make sure the system clock been switch to internal 8MHz or 4MHz RC before power down

external OSC/LIRC.

2.1.17 CLOCON (Clock output Control Register)

Address

23h (r/w)

Name

B7

B6

-

B5

B4

B3

B2

B1

B0

CLOCON

CLOEN

EXCLK

DINV

DUTY CLOPS2 CLOPS1 CLOPS0

Legend: - = unimplemented, read as ‘0’.

The FM8P756 provides one system clock output with prescaler function.

CLOEN : System Clock output function selection

= 1, IOA5 is Clock Output.

= 0, IOA5 is normal I/O.

EXCLK : External clock (IOA2/TMCKI) function selection

= 1, IOA2 is external clock input of timer.

= 0, IOA2 is normal I/O.

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FM8P756

DINV : System Clock output Duty invert selection bit.

If DUTY bit = 1:

= 1, 1/4 duty output

= 0, keep 3/4 duty output

else:

Ignore.

DUTY : System Clock output duty selection bit.

= 1, 3/4 duty output.

= 0, 1/2 duty output.

CLOPS2:CLOPS0 : Clock Output prescaler setting

Clock Output prescaler ratio

DUTY = 0 DUTY = 1

CLOPS2 : CLOPS0

0

1

0

1

0

1

0

1

1:1

1:2

1:4

0

1

1:4

1:8

1

0

1:8

1:16

1:32

1:64

1:16

1:32

0

Other

No function, don’t use.

2.1.18 APHCON, BPHCON, CPHCON (Port A, Port B, Port C Pull-high Control Register)

Address

25h (r/w)

26h (r/w)

27h (r/w)

Name

B7

B6

PHA6

-

B5

B4

B3

B2

B1

B0

APHCON

BPHCON

CPHCON

-

PHA5

PHB5

PHC5

PHA4

PHB4

PHC4

PHA3

PHB3

PHC3

PHA2

PHB2

PHC2

PHA1

PHB1

PHC1

PHA0

PHB0

PHC0

PHC7

PHC6

Legend: - = unimplemented, read as ‘0’.

Those registers are used to setup pull-high resistor enable/disable of each IO pins.

= 1, Pull-high resistor enable.

= 0, Pull-high resistor disable.

2.1.19 INTPA (Port A Interrupt / Wakeup control Register)

Address

28h (r/w)

Name

INTPA

B7

B6

B5

B4

B3

B2

B1

B0

PA7IEN PA6IEN PA5IEN PA4IEN PA3IEN PA2IEN PA1IEN PA0IEN

This register is used to enable/disable the interrupt/wakeup function of Port A. Please refer to 2.8.1 for detail

description of External Interrupt and Wake up function.

= 1, Selected IO interrupt/wakeup enable.

= 0, Selected IO interrupt/wakeup disable.

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2.1.20 WDTCON (Watchdog Timer Control Register)

Address

29h (r/w)

Name

B7

B6

B5

B4

-

B3

-

B2

B1

B0

WDTCON WDTEN I_WDT I_TWDT

WDTPS2 WDTPS1 WDTPS0

Legend: - = unimplemented, read as ‘0’.

The FM8P756 builds in a watchdog timer with two different modes, normal watchdog reset and internal watchdog

wakeup. The watchdog timer is controlled by this register (WDTCON). Please refer to 2.6 for detail Watchdog

Timer description.

WDTEN : Watchdog Timer Enable/ Disable.

= 1, WDT Enable.

= 0, WDT disable.

I_WDT : Internal Watchdog Wakeup mode selection.

= 1, Internal Watchdog Wakeup Enable.

= 0, Internal Watchdog Wakeup Disable.

I_TWDT : Watchdog Timer Stable time required when operating in I_WDT mode (I_WDT bit = 1).

= 1, 1.25ms.

= 0, 5ms (default).

WDTPS2:WDTPS0 : Watchdog timer prescaler setting

WDTPS2 : WDTPS0

WDT prescaler rate

1:1 (20mS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:2 (40mS)

1:4 (80mS)

1:8 (160mS)

1:16 (320mS)

1:32 (640mS)

1:64 (1.28S)

1:128 (2.56S)

2.1.21 TAB_BNK (Table Look-up function Bank select Register)

Address

Name

B7

-

B6

-

B5

-

B4

-

B3

-

B2

B1

B0

2Ah (r/w)

TB_BNK

BNK2

BNK1

BNK0

Legend: - = unimplemented, read as ‘0’.

The FM8P756 provides a table look-up function and the bank selection of ROM data is controlled by this register.

Please refer to 2.10 for detail operation of look-up table function.

BNK2:BNK0 : Page selection of Look-up table

BNK2 : BNK0

BANK select

0

1

|

0

1

0

000 XXXX XXXX Table location

001 XXXX XXXX Table location

010 XXXX XXXX Table location

|

1

111 XXXX XXXX Table location

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2.1.22 ACC (Accumulator)

Address

N/A (r/w)

Name

ACC

B7

B6

B5

B4

B3

B2

B1

B0

Accumulator

Accumulator is an internal data transfer, or instruction operand holding. It cannot be addressed.

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2.2 I/O Ports

There are totally 21 bi-directional tri-state I/O ports and one (IOA7) input only. All I/O pins (IOA<6:0>, IOB<5:0>

and IOC<7:0>) have specified data direction control registers (IOSTA, IOSTB and IOSTC) which can configure

these pins as output or input.

All the IO pins can also enable or disable a weak internal pull-high by setting APHCON, BPHCON and CPHCON.

This weak pull-high will be automatically turned off when the pin is configured as an output pin.

VR pin is reference voltage input pin of the ADC module, this pin does not have I/O function.

The Configuration Words can set IOA7 to Reset functions. When acting as Reset functions the pins will read as

“0” during port read.

Please note, IOB2 and VR voltage on these pins must not exceed VDD, otherwise it will cause the pin

breakdown.

Figure 2.3: Block Diagram of I/O Pins

IOB5, IOC7 ~ IOC0:

DATA BUS

D

Q

IOST

Latch

WR IOSTx

EN

Q

I/O PIN

D

DATA

Latch

WR PORT

RD PORT

EN

Q

Pull-high / ADC / LCD are not shown in this figure

DATA BUS

IOA6 ~ IOA0:

D

Q

IOST

Latch

WR IOSTAx

EN

Q

I/O PIN

D

DATA

Latch

WR PORT

RD PORT

EN

Q

D

Q

Set PAIF

PAxIEN

Latch

EN

Pull-high/ADC/OSC are not shown in this figure

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FM8P756

IOA7:

DATA BUS

RD PORT

I/O PIN

Q

D

Set PAIF

PA7IEN

Latch

EN

Voltage on this pin must not exceed VDD.

VR:

To ADC module

VR PIN

Voltage on this pin must not exceed VDD.

IOB0 ~ IOB3:

½ VDD

COMnE

COMEN

DATA BUS

D

Q

IOST

Latch

WR IOSTBx

EN

Q

I/O PIN

DATA

Latch

WR PORT

RD PORT

EN

Q

Pull-high is not shown in this figure

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2.3 Timer/Event Counter (TMR1, TMR2, TMR3)

The FM8P756 contains three 8-bit down-counts Timers/Counters. All these timers have auto reload function,

TMR1 and TMR2 can be to perform PWM function.

Figure 2.4: Simple Block Diagram of the Timer 1 ~ 3

TMR(x)

TxSO<1:0>

Latch

T(x)PS<2:0>

EXCLK

Auto-reload

WR T(x)LA

Controller

TMCKI (IOA2)

00

01

10

Prescaler

00

01

10

11

8Bit-

Counter

Set T(x)P(x)IF flag

on overflow

Note: (x) is 1 or 2

Frequency

multiplier

x2

TMR3

Latch

Auto-reload

Controller

WR T3LA

T3LOAD

T3PS<2:0>

Prescaler

8MHz

HIRC

00

01

10

8Bit-

Counter

Set T3IF flag

on overflow

T3SO<1:0>

SYS_CK*

ERC

Oscillator

F_OSC

*

System clock

CPU_S*

/4, /2

CLKS

Crystal

Oscillator

/2, /1

0

1

Instruction clock

12KHz

LIRC

*: Controlled by configuration word

F_OSC

*

2.3.1

Clock Source

Timer1 and Timer2 has four clock sources can be selected, Timer3 has three clock sources can be selected.

2.3.1.1 TMCKI (IOA2)

The event counter mode would be activated when the source of TMCKI (IOA2) used. At this mode, the rising/

falling edge of the event could also be selected separately.

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2.3.1.2 Crystal or External RC Oscillator

In this mode, the timer clock source from Crystal / ERC oscillator module. Oscillator module operating modes are

defined by the Fosc bit in the configuration word.

Please note that, in this case, the clock input to the timer in two paths, and therefore will have the following

composition:

Table 2.1: Selection of Timer 1 ~ 3 Clock source

F_OSCmode of Configuration word

HIRC

Timer 1 ~ 3 Clock

Only HIRC 8 MHz

HIRC & LIRC

HIRC 8 MHz or LIRC 12 KHz

HIRC 8 MHz or Crystal oscillator source

Only External RC oscillator source

Only LIRC 12 KHz

HIRC & XT or HIRC & LF

ERC

LIRC

XT or LF

Only Crystal oscillator source

Since the oscillator module is controlled by the F_OSCbit, if need a combination of multiple clock sources, the need

to carefully choose the configuration word F_OSCoperating mode.

2.3.1.3 Internal 8MHz RC Oscillator

In this mode, timer clock source from internal 8MHz RC oscillator. Please note that this clock source can only be

used in the following modes:

Table 2.2: Selection of 8 MHz HIRC clock source

F_OSCmode of Configuration word

HIRC

Timer 1 ~ 3 Clock

HIRC 8 MHz can be selected

HIRC 8 MHz are shutdown

HIRC & LIRC

HIRC & XT or HIRC & LF

ERC or LIRC or XT or LF

2.3.1.4 Internal 8MHz RC Oscillator *2

In this mode, the IRC frequency is multiplied by 2, as the timer clock source, this clock source using the same

Opportunity and Table 2.2.

Note : This mode only for Timer1 and Timer2.

2.3.2

Prescaler

Each timer contains a 3-bits prescaler which can scale the timer or counter from 1:1 to 1:128.

TxPS2 : TxPS0

TMRx Prescal rate

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

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2.4 Pulse Width Modulation (PWM)

FM8P756 provides two PWM output shared with TMR1 and TMR2. When PWM1 or PWM2 selected,

TMR1/TMR2 will be the duty of PWM1/PWM2.

PWM1 and PWM2 period is fixed resolution of 8-bits; duty time output a maximum resolution of 8-bits (normal

mode) or 6-bits (extended mode).

The PWM outputs are on the IOA4/ADC4/INT4/PWM1, and IOB4/ADC5/PWM2 pins.

The user needs to set the T1MOD bit (PWM1CON<7>) to enable the PWM1 output. When T1MOD bit is set, the

IOA4/ADC4/INT4/PWM1 pin is configured as PWM1 output and forced as an output, irrespective of the data direct

bit (IOSTA<6>). When the T1MOD is clear, the pin behaves as a I/O pin.

Similarly, the T2MOD bit (PWM2CON<7>) controls the configuration of the IOB4/ADC5/PWM2 pin.

The FM8P756 PWM has two modes of operation; PWM1 and PWM2 have normal mode, and the extension

mode, detailed description as follows:

2.4.1

Normal PWM mode

In the Normal PWM mode, it is a general purpose PWM mode; this mode can be used in the PWM1 and PWM2.

The PWM1 period time is fixed; period time can be calculated as follows:

1

Period time of PWM1 = 256 * TMR1 Prescal rate *

Clock source frequency

The duty cycle of PWM1 is determined by the 8-bit value T1LA, PWM1 duty time is as follows:

1

Duty time of PWM1 = (T1LA+1) * TMR1 Prescal rate *

Clock source frequency

or

Duty time * Clock source frequency

T1LA =

TMR1 Prescal rate

PWM1 and PWM2 structure is the same. Therefore, these formulas can be used directly in PWM2.

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Example 2.2: PWM1 Setting (Normal mode)

Address

NA

Code

#include <8P756.ASH>

…

//Set PWM1 Duty

n

MOVIA

0x32

n+1

MOVAR

T1CON

;CLK source is Crystal, Prescaler 1:4

;Period time = 256*4*(1/16MHz) = 64uS

n+2

n+3

n+4

n+5

MOVIA

MOVAR

MOVIA

MOVAR

0x80

PWM1CON

0xC8

;Set to Normal PWM, interrupt rate 1:1

T1LA

;Set Duty (0xC8 down count to 0x00)

;Duty time = (0xC8+1)*4*(1/16MHz) = 50.25uS

;Start PWM1

n+6

BSR

T1CON,T1EN_B

//Interrupt setting, not required

n+7

n+8

MOVIA

MOVAR

MOVIA

MOVAR

0x81

INTEN

0x76

INTFLAG

;Enable global & PWM1 interrupt

;Clear interrupt flag

;Clear T1P1IF(PWM1) flag

n+9

n+10

Note: 1. The PWM duty (F_OSC/255 max) must be smaller than PWM period (F_OSC/256). In this example, the

frequency of external OSC is approximately 16MHz.

2. The PWM duty has built-in controller circuit, user can directly change, and the new value will be

automatically loaded to the next cycle.

Figure 2.5: Normal PWM Output Waveform

FF FE

01 00 FF FE

01 00

Internal Period Counter:

PWM1 Output:

PWM Period

PWM Duty

C8 C7

01 00

C8 C7

01 00

TMR1 counter:

T1P1IF (PIR1<3:0>=1:1)

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2.4.2

Extension PWM mode

In the extension PWM mode, PWM module will increase the delay to Duty cycle. This mode has three modes, can

be select by T1LA <1:0> (PWM1) or T2LA <1:0> (PWM2). Therefore, in the extension mode, duty cycle

maximum resolution is 6-bits.

The PWM1 or PWM2 duty cycle is set by T1LA <7:2> or T2LA <7:2>.

This mode can be used in the PWM1 and PWM2.

Figure 2.6: T1 or T2 LA bits allocation in the Extension PWM mode

T1 or T2 LA

7

0

D5 D4 D3 D2 D1 D0 M1 M0

Duty cycle value

M1 : M0

Stretched cycle number

None (Same as Normal mode)

Only 2nd

0

1

0

1

0

1

1st and 3rd

1st, 2nd and 3rd

Figure 2.7: Extension PWM Output Waveform

...

1st

2nd

3rd

4th

1st

2nd

3rd

4th

PWMx Normal mode:

M1:M0=00:

M1:M0=01:

M1:M0=10:

M1:M0=11:

Extension delay

Extension mode duty time can be calculated as follows:

1

Duty time of PWM1 = (T1LA+1) * TMR1 Prescal rate *

Clock source frequency

or

Duty time * Clock source frequency

T1LA =

TMR1 Prescal rate

Extension delay time is as follows:

1

Clock source frequency

Extension delay time = TMR1 Prescal rate *

PWM1 and PWM2 structure is the same. Therefore, these formulas can be used directly in PWM2.

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Example 2.3: PWM1 Setting (Extension mode)

Address

NA

Code

#include <8P756.ASH>

…

//Set PWM1 Duty

n

MOVIA

0x32

n+1

MOVAR

T1CON

;CLK source is Crystal, Prescaler 1:4

;Period time = 256*4*(1/16MHz) = 64uS

n+2

n+3

n+4

n+5

MOVIA

MOVAR

MOVIA

MOVAR

0xA0

PWM1CON

0xC9

;Set to Extension PWM, interrupt rate 1:1

T1LA

;Set Duty (0x32 down count to 0x00)

;Duty time = (0x32+1)*4*(1/16MHz) = 12.75uS

;Start PWM1

n+6

BSR

T1CON,T1EN_B

//Interrupt setting, not required

n+7

n+8

MOVIA

MOVAR

MOVIA

MOVAR

0x81

INTEN

0x76

INTFLAG

;Enable global & PWM1 interrupt

;Clear interrupt flag

;Clear T1P1IF(PWM1) flag

n+9

n+10

Note: 1. The PWM duty (F_OSC/255 max) must be smaller than PWM period (F_OSC/256). In this example, the

frequency of external OSC is approximately 16MHz.

2. The PWM duty has built-in controller circuit, user can directly change, and the new value will be

automatically loaded to the next cycle.

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2.5 Software controlled LCD

The FM8P756 have the software controlled LCD driving external LCD panels. The common pins for LCD driving,

COM0~COM3, are pin shared with certain pin on IOB0~IOB3 port. The LCD signals (COM and SEG) are

generated using the application program.

The LCD driver function is controlled using the COMCON1 and COMCON2 to controlling the overall on/off

function, Also controls the bias voltage setup function. This enables the LCD COM driver to generate the

necessary VDD/2 voltage levels for LCD 1/2 bias operations.

2.5.1

1/2 VDD Bias

The chip provides 1/2 VDD bias in IOB0 ~ IOB3. User needs to set the COMIS<1:0> bits set I_COMcurrent. To

make the I/O Output 1/2 VDD bias, must be setting COMEN bit to “1”.

When COMEN bit is "1", COM0E direct control IOB0 pin, users only need to control IOB0 and COM0E two bits,

IOSTB0 does not affect the status of IOB0.

Similarly, COM3E ~ COM1E bits control the corresponding IOB3 ~ IOB1 pin.

Figure 2.8: Simplified Block Diagram of COM pins

½ VDD simplified block

IOB0

COMIS<1:0>

:

IOB3

COMEN

COM3E

IOB0~IOB2 some circuit are not shown in this figure

Table 2.3: COM 3~0 Pin Function

COMEN

COMnE

Pin Function

I/O

IOB3 ~ 0

0 or 1

0

1

X

0

1

COMn

I/O

1/2 VDD

0 or 1

Note: In the case of unused, the user must turn-off 1/2 VDD bias (setting COMEN bit to “0”), reducing current

consumption.

2.5.2

COMCK

The chip provides one set of dividers can be set, the user can use this divider to generate an interrupt triggers

signal to generate LCD waveform by software program. If this interrupt source used in another application,

COMEN bit must be set to "1".

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2.6 Watch Dog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external

components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in

SLEEP mode.

The WDT can be disabled by clearing the control bit WDTEN (WDTCON <7>) to “0”.

The WDT has a typical time-out period of 20 mS (without prescaler). This period of this timer may be variant

slightly because of temperature, voltage, and process variation. If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the WDTCON register

<2:0>. Thus, the longest time-out period is approximately 2.56 seconds.

The CLRWDT instruction clears the WDT and prevents it from timing out and generating a device reset.

The SLEEP instruction also resets the WDT. This gives the maximum SLEEP time before a WDT Wake-up

Reset.

There are two type of watchdog timer mode could be selected by I_WDT (WDTCON <6>). When I_WDT bit

disable, normal watchdog timer reset is selected. During normal operation or in SLEEP mode, a WDT time-out

̅̅̅̅

will cause the device reset and the TO bit (STATUS<4>) will be cleared.

If I_WDT bit enabled, the internal watchdog timer wakeup will be used. The system wakeups from sleep, then

jumps into interrupt vector with external interrupt request PAIF (INTFLAG<5>) and continues from next instruction

instead of triggering a reset event. There is a stabilization time required for internal watchdog wakeup could be

selected by I_ TWDT (WDTCON<5>). The default value of this stabilization timer is 5ms.

Example 2.4: Internal Watchdog Wakeup

Address

NA

Code

#include <8P756.ASH>

0x003

0x004

…

1. WDT Wakeup

;User WDT Wakeup ISR code

… (Backup status code)

…

MOVIA

MOVAR

0x57

INTFLAG

;Clear PAIF flag^(Note1)

… (Restore status code)

RETFIE

2. Return from ISR

n

MOVIA

MOVAR

CLRWDT

MOVIA

MOVAR

…

0xA0

INTEN

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

;Enable global & Port A interrupt

;Sleep: 2.56S + Wakeup: 5mS

0xE7

WDTCON

…

SLEEP

NOP

…

Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).

2. Interrupt backup / restore status code are not shown in this example.

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Example 2.5: Typical Watchdog Reset

Address

NA

Code

#include <8P756.ASH>

0x000

…

WDT Reset

n

CLRWDT

MOVIA

MOVAR

…

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

0x87

WDTCON

;Sleep: 2.56S + Wakeup:20mS

…

SLEEP

NOP

…

2.7 Reset

FM8P756 device may be RESET in one of the following ways:

1. Power-on Reset (POR)

2. Brown-out Reset (BOR)

3. RSTB Pin Reset

4. WDT time-out Reset

Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and

unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or

WDT Reset.

A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely

ties the RSTB pin to Vdd.

On-chip Low Voltage Detector (LVDT) places the device into reset when Vdd is below a fixed voltage. This

ensures that the device does not continue program execution outside the valid operation Vdd range. Brown-out

RESET is typically used in AC line or heavy loads switched applications.

A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before

SLEEP.

̅̅̅̅

The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.

2.7.1

Power-up Reset Timer(PWRT)

The Power-up Reset Timer provides a nominal 20ms delay after Power-on Reset (POR), Brown-out Reset (BOR),

RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.

The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.

Figure 2.9: Reset Timing

Case1: LVDT ON, RSTB Disable

VDD

PWRT time-out

Internal Reset

V_LVDT

T_PWRT

Note: T_PWRT= 20mS

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FM8P756

Case2: LVDT OFF, RSTB Enable

VDD

V_IH

RSTB

V_IL

PWRT time-out

Internal Reset

T_PWRT

Note: T_PWRT= 20mS

Case3: LVDT OFF, RSTB Disable

VDD

VDD_min

PWRT time-out

Internal Reset

T_PWRT

Note: T_PWRT= 20mS

Figure 2.10: Simplified Block Diagram of on-chip Reset Circuit

WDT

WDT Time-out

Module

(WarmStart)

Synchronize

With

System Clock

I WDT

Enable

RSTB

Cold Start

Low Voltage

VDD

Detector

(LVD)

RESET

On-Chip

RC OSC

Power-up

Reset Timer

(PWRT)

CHIP RESET

Power-on

Reset

(POR)

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Table 2.4: Reset Conditions for Operational Registers

Power-on Reset

Brown-out Reset

WDT Reset

RSTB Reset

Register

Address

ACC

INDF

N/A

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

10h

11h

xxxx xxxx

0000 0000

---- -000

---1 1xxx

xxxx xxxx

-111 1111

xxxx xxxx

--11 1111

--xx xxxx

1111 1111

xxxx xxxx

0-00 0000

000- 0000

1111 1111

0-00 0000

000- 0000

1111 1111

0-00 0000

1111 1111

0000 -000

-000 -000

0--- -000

---- --00

---- 0000

00-- ----

0000 0000

---- 0000

0--0 0000

0--- --00

0-00 0000

-000 0000

--00 0000

0000 0000

100- -111

---- -000

1111 1111

xxxx xxxx

uuuu uuuu

0000 0000

---- -000

---# #xxx

uuuu uuuu

-111 1111

uuuu uuuu

--11 1111

--uu uuuu

1111 1111

uuuu uuuu

0-00 0000

000- 0000

1111 1111

0-00 0000

000- 0000

1111 1111

0-00 0000

1111 1111

0000 -000

-000 -000

0--- -000

---- --00

---- 0000

00-- ----

0000 0000

---- 0000

0--0 0000

0--- --00

0-00 0000

-000 0000

--00 0000

0000 0000

100- -111

---- -000

1111 1111

uuuu uuuu

PCL

PCHBUF

STATUS

FSR

IOSTA

PORTA

IOSTB

PORTB

IOSTC

PORTC

T1CON

PWM1CON

T1LA

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

40h ~ 9Fh

T2CON

PWM2CON

T2LA

T3CON

T3LA

T3CNT

INTEN

INTFLAG

ADCON1

ADCON2

ADCON3

ADDATL

ADDATH

COMCON1

COMCON2

SYSCLK

CLOCON

APHCON

BPHCON

CPHCON

INTPA

WDTCON

TAB_BNK

T1CNT

T2CNT

General Purpose Registers

Legend: u = unchanged, x = unknown, - = unimplemented, # = refer to the following table for possible values.

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̅̅̅̅

Table 2.5: TO and PD Status after Reset

̅̅̅̅

TO

PD

RESET was caused by

WDT timer overflow from sleep mode

WDT timer overflow from normal mode

Set ‘low” at RESETB from sleep mode

Power on reset

0

1

u

0

1

0

1

u

Set “low” at RESETB from normal mode

Legend: u = unchanged.

̅̅̅̅

Table 2.6: TO and PD Status after Reset

̅̅̅̅

Event

TO

PD

1

Power-on

1

0

1

WDT Time-out

u

SLEEP instruction

CLRWDT instruction

Legend: u = unchanged.

0

1

2.8 Interrupt

The FM8P756 has four kinds of interrupt sources:

1. 8 External IOA<0:7> pin changed interrupt

2. 3 Timers underflow interrupt (or PWM interrupt)

3. ADC conversion completion interrupt

4. LCD COM interrupt

INTFLAG is the interrupt flag register that recodes the interrupt requests to the relative flags.

A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all

interrupts. Individual interrupts can be enabled/ disabled through their corresponding enable bits in INTEN

register regardless of the status of the GIE bit.

When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit

will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address

004h. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.

The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.

The flag bit in INTFLAG register is set by interrupt event regardless of the status of its mask bit.

2.8.1

PORTA<0:7> External Interrupt and Wakeup Function

The external interrupt on PORTA<0:7> are selected by INTPA<0:7> and PAIE (INTEN<5>). When the device is

in normal mode and the specified IO status changed, the interrupt event will be triggered and the program will

jump to 004h.

When the device is in sleep mode, those interrupts can also be used as an external wakeup signal. The device

will restart system clock and the program will jump to 004h after startup timer timeout.

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Example 2.6: External IOA0 pin change interrupt

Address

NA

Code

#include <8P756.ASH>

0x003

0x004

…

1. IOA0 pin change

… (Backup status code)

…

MOVIA

MOVAR

;User Port A pin change ISR code

;Clear PAIF flag^(Note1)

0x57

INTFLAG

… (Restore status code)

RETFIE

2. Return from ISR

n

MOVIA

MOVAR

MOVIA

MOVAR

MOVIA

MOVAR

MOVR

MOVIA

MOVAR

…

0xFF

IOSTA

0xA0

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

;Set Port A as input

INTEN

0x57

;Enable global & Port A interrupt

INTFALG

PORTA,A

0x01

;Clear PAIF flag^(Note1)

;Update Port A pin status

INTPA

;Set IOA0 pin change

…

Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).

2. Interrupt backup / restore status code is not shown in this example.

Example 2.7: External IOA0 pin change wakeup interrupt

Address

NA

Code

#include <8P756.ASH>

0x003

0x004

…

1. IOA0 pin change

; User Port A pin change wakeup ISR code

… (Backup status code)

…

MOVIA

MOVAR

0x57

INTFLAG

;Clear PAIF flag^(Note1)

… (Restore status code)

RETFIE

2. Return from ISR

n

MOVIA

MOVAR

MOVIA

MOVAR

MOVIA

MOVAR

MOVR

MOVIA

MOVAR

SLEEP

NOP

0xFF

IOSTA

0xA0

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

n+10

;Set Port A as input

INTEN

0x57

;Enable global & Port A interrupt

INTFALG

PORTA,A

0x01

;Clear PAIF flag^(Note1)

;Update Port A pin status

INTPA

;Set IOA0 pin change wakeup

…

Note : 1. BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).

2. Interrupt backup / restore status code is not shown in this example.

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2.8.2

Timer1~3 Interrupt’s

2.8.2.1 Timer 1 interrupt

At Timer mode, an underflow (00h  FFh) in the TMR1 counter will set the flag bit T1P1IF (INTFLAG<0>).

At PWM mode, the end of each PWM period cycle to generate an interrupt. The interrupt rate can be adjusted by

PWM1CON <3:0>. See Figure 2.11 for detail description.

The T1P1IF bit can be cleared by software. This interrupt can be disabled by clearing T1P1IE bit (INTEN<0>).

2.8.2.2 Timer 2 interrupt

At Timer mode, an underflow (00h  FFh) in the TMR2 counter will set the flag bit T2P2IF (INTFLAG<1>).

At PWM mode, the end of each PWM period cycle to generate an interrupt. The interrupt rate can be adjusted by

PWM2CON <3:0>. See Figure 2.11 for detail description.

The T2P2IF bit can be cleared by software. This interrupt can be disabled by clearing T2P2IE bit (INTEN<1>).

Figure 2.11: PWM Interrupt Waveform

PWMx Output

TxPxIF (PIRx<3:0>=1:4)

TxPxIF (PIRx<3:0>=1:5)

2.8.2.3 Timer 3 interrupt

An underflow (00h  FFh) in the TMR3 counter will set the flag bit T3IF (INTFLAG<2>). And the T3IF bit can be

cleared by software. This interrupt can be disabled by clearing T3IE bit (INTEN<2>).

2.8.3

ADC conversion completion interrupt

When the A/D conversion is completed, the flag bit ADCIF (INTFLAG <6>) will be set. And the ADCIF bit can be

cleared by software. This interrupt can be disabled by clearing ADCIE bit (INTEN<6>).

2.8.4

LCD COM interrupt

When the divider overflow occurs, the flag bit COMIF (INTFLAG <4>) will be set. And the COMIF bit can be

cleared by software. This interrupt can be disabled by clearing COMIE bit (INTEN<4>).

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2.9 Analog to Digital Converter (ADC)

This analog to digital converter has 8 channels 10bits (8+2) resolution. The ADC is controlled by three control

register, ADCON1, ADCON2, and ADCON3.

Example 2.8: Analog to Digital Conversion (Channel0 AD conversion)

Address

Code

NA

#include <8P756.ASH>

…

n

BTRSC

GOTO

ADCON1,ADCEN_B

n+1

$-1

; Make Sure no ADC is processing

; Clear ADCIF flag^(Note)

n+2

MOVIA

MOVAR

MOVIA

MOVAR

MOVIA

MOVAR

MOVIA

MOVAR

BSR

0x37

n+3

INTFLAG

0x00

ADCON1

0x03

n+4

n+5

; Select ADC Channel 0 (IOA0) conversion

; Set AD conversion rate: System clock / 128

n+6

n+7

n+8

ADCON2

0x01

n+9

ADCON3

ADCON1,ADCEN_B

INTFLAG,ADCIF_B

$-1

; Set AN0 analog input

; ADC conversion start

n+10

n+11

n+12

n+13

n+14

n+15

n+16

BTRSS

GOTO

; Wait AD end of conversion

MOVR

MOVAR

MOVR

ADDATH,A

…

; Read ADC high byte data

; Transfer ADC value to other register.

; Read ADC low byte data

ADDATL,A

…

MOVAR

…

; Transfer ADC value to other register.

Note : BCR instruction is not recommended for Clear interrupt flag (INTFLAG register).

2.10 Look-Up Table Function

The Look-up Table function is built-in to access the data table within entire ROM area. The TAB_BNK register is

used to address the high byte of the location of required ROM. The instructions TABL and TABH are used to

read low byte and high byte of the addressed ROM. The result of instructions will be stored at ACC register.

Please refer to the following example for detail.

Example 2.9: Look-up Table

Address

Code

NA

#include <8P756.ASH>

…

n

MOVIA

MOVAR

MOVIA

MOVAR

TABL

0x03

n+1

n+2

n+3

n+4

0x5B

;Save offset value 03H to register 0x5B (low bit address)

0x07

TAB_BNK

0x5B

; Save offset value 07H to TAB_BNK (high bit address)

; Read Low byte 0x703 ROM Data, and saved

; it to ACC. (ACC=0xAA)

n+5

n+6

MOVAR

TABH

….

; Transfer value to other register.

0x5B

; Read High byte 0x703 ROM Data, and saved

; it to ACC. (ACC=0x55)

n+7

n+8

MOVAR

…

; Transfer value to other register.

Required sequence

0x700

0x701

0x702

0x703

…

DW

…

0x1122

0x3344

0x5566

0x55AA

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2.11 Hexadecimal Convert to Decimal (HCD)

Decimal format is another number format for FM8P756. When the content of the data memory has been assigned

as decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions.

When the decimal converting operation is processing, all of the operand data (including the contents of the data

memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the

results of conversion will be incorrect.

Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and

restored to ACC.

The conversion operation is illustrated in Example 2.10.

Example 2.10: DAA CONVERSION

Address Code

NA

n

#include <8P756.ASH>

…

n+1

n+2

n+3

n+4

MOVIA 0x90

MOVAR 0x40

MOVIA 0x10

;Set immediate data = decimal format number “90” (ACC  90h)

;Load immediate data “90” to data memory address 40H

;Set immediate data = decimal format number “10” (ACC  10h)

ADDAR 0x40,A ;Contents of the data memory address 40H and ACC are binary-added

;the result loads to the ACC (ACC  A0h, C  0)

n+5

n+6

DAA

0x40,A ;Convert the content of ACC to decimal format, and restored to ACC

;The result in the ACC is “00” and the carry bit C is “1”. This represents

;the decimal number “100”

…

Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation

and restored to ACC.

The conversion operation is illustrated in Example 2.11.

Example 2.11: DAS CONVERSION

Address Code

NA

n

#include <8P756.ASH>

…

n+1

n+2

n+3

n+4

MOVIA 0x10

MOVAR 0x40

MOVIA 0x20

;Set immediate data = decimal format number “10” (ACC  10h)

;Load immediate data “90” to data memory address 40H

;Set immediate data = decimal format number “20” (ACC  20h)

SUBAR 0x40,A ;Contents of the data memory address 40H and ACC are binary-subtracted

;the result loads to the ACC (ACC  F0h, C  0)

n+5

n+6

DAS

0x40,A ;Convert the content of ACC to decimal format, and restored to ACC

;The result in the ACC is “90” and the carry bit C is “0”. This represents

;the decimal number “ -10”

…

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2.12 Dual Clock Function

The chip can be operated in three different dual clock function, users need to use it, and the configuration word

must be set to one of following:

 HIRC & LIRC

 HIRC & XT

 HIRC & LF

If not in these states, will not be able to use dual clock function. By default, the system is the use of internal HIRC

frequency as the clock source, and the two oscillator circuit is in the enable state. If not used, turn off unused

oscillator power (via SYSCLK), can be reduce unnecessary current consumption.

When you want to switch clock source, recommend follow these steps:

1. Turn-on another oscillator power.

2. Wait oscillator to stable (XT and LF mode requires this step).

3. Set WDT prescaler to 1:128 and Clear Watch-dog (avoid watchdog overflow).

4. Set or Clear CLKS bit (SYSCLK <7>) to switch to another clock source.

5. Wait two NOP instruction (Required sequence).

6. Clear Watch-dog and set back to original settings.

7. If original oscillator not used, turn-off it.

Since the oscillator from the off state to the normal output clock oscillator needs some time to wait for a stable, at

each oscillation mode, we recommend waiting time should be greater than the following table:

Table 2.7: Recommend typical wait time

Situation

Crystal  HIRC

Typical waiting time

10uS

HIRC  Crystal (4 to 20 MHz)

HIRC  Crystal (32 KHz)

HIRC  LIRC

1.5mS

5 ~ 370mS

1.5mS

Note: 1. This table is for reference only.

2. Quartz crystal characteristics vary according to type, package and manufacturer, the users must be

carefully tested and verified.

3. RC oscillator mode will change depending on the operating voltage, the user must carefully tested and

verified.

Example 2.12: Switching from HIRC to External clock (or LIRC)

Address

NA

Code

#include <8P756.ASH>

…

n

BCR

SYSCLK,ECLKPD_B

Delay

;Turn-on External oscillator

n+1

CALL

MOVIA

MOVAR

CLRWDT

BSR

;Wait Crystal oscillator to stable

0x87

WDTCON

;If Watch-dog enable, recommend set to 1:128

;If Watch-dog enable, clean it!

n+2

n+3

n+4

n+5

n+6

n+7

n+8

n+9

SYSCLK,CLKS_B

;Switching from HIRC to External clock

Required sequence

NOP

CLRWDT

BSR

;If Watch-dog enable, clean it!

SYSCLK,IRCPD_B

0xnn

;Turn-off HIRC oscillator (if unused)

MOVIA

MOVAR

…

WDTCON

;Set back original settings (if Watch-dog used)

Similarly, switching from External clock (or LIRC) to HIRC also this procedure.

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2.13 Oscillator Configurations

FM8P756 can be operated in five different combinations of oscillator modes. Users can program Configuration

Words (F_OSC) to select the appropriate modes. The five different system clock modes are combination of the

following oscillators:

 LF: Low Frequency Crystal Oscillator

 XT: Crystal/Resonator Oscillator

 ERC: External Resistor/ Voltage Controlled Oscillator

 HIRC: High speed Internal Resistor/Capacitor Oscillator

 LIRC: Low speed Internal Resistor/Capacitor Oscillator

In LF, or XT modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish

oscillation. When in LF, or XT modes, the devices can have an external clock source drive the OSCI pin.

The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator

frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext), the operating temperature,

and the process parameter.

The IRC option offers largest cost savings for timing insensitive applications.

Figure 2.12: XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)

FM8P756

C1

OSCI

SLEEP

X`TAL

RS

R1

RF

OSCO

C2

Internal

Circuit

Figure 2.13: XT or LF Oscillator Modes (External Clock Input Operation)

FM8P756

OSCI

Clock from

External System

OSCO

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Figure 2.14: ERC Oscillator Mode (External RC Oscillator)

FM8P756

Rext

OSCI

Internal

Circuit

Cext

Dual-clock

Controller

/2, /4

CPU_S

OSCO

Instruction clock

The typical oscillator frequency vs. external resistor is as following table

When Cext = 0.01uf (103)

5V

3V

Frequency

Rext

4.3M

210K

108K

56K

Frequency

32 KHz

Rext

3.6M

238K

116K

59K

32 KHz

500 KHz

1.0 MHz

2.0 MHz

4.0 MHz

8.0 MHz

12.0 MHz

500 KHz

1.0 MHz

2.0 MHz

4.0 MHz

8.0 MHz

12.0 MHz

30K

16K

11K

Note: Values are provided for design reference only.

Figure 2.15: HIRC/LIRC Oscillator Mode (Internal R, Internal C Oscillator)

FM8P756

IOA6

Internal

Circuit

C

IOA5

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2.14 Configuration Words

Table 2.8: Configuration Words

Name

Description

Oscillator Selection Bit

 HIRC (8 MHz or 4 MHz) mode (default)

 HIRC (8 MHz or 4 MHz) & LIRC (12 KHz) mode

 HIRC (8 MHz or 4 MHz) & XT crystal mode

 HIRC (8 MHz or 4 MHz) & LF crystal mode

 ERC mode

Fosc

 LIRC (12 KHz) mode

 XT crystal mode

 LF crystal mode

Note: LIRC 12 KHz is an uncalibrated low frequency oscillator.

Watchdog Timer Enable Bit

 WDT enabled (default)

 WDT disabled

WDTEN

LVDT

Low Voltage Detector Selection Bit

 LVDT = 2.2V

 LVDT = 2.6V

 LVDT = 3.7V (default)

IOA7/RSTB Pin Selection Bit

 RSTB pin is selected (default)

 IOA7 pin is selected

RSTBIN

OSCD

Instruction Period Selection Bit

 four oscillator periods (4T) (default)

 two oscillator periods (2T)

System Clock Selection bit

SYS_CK

OSCOUT

PROTECT

 8 MHz

 4 MHz

IOA5/OSCO Pin Selection Bit for ERC mode

 OSCO pin is selected (default)

 IOA5 pin is selected

Code Protection Bit

 NO, OTP code protection off (default)

 YES, OTP code protection on

Table 2.9: Selection of IOA5/OSCI and IOA6/OSCO Pin

Mode of oscillation

HIRC/LIRC

ERC

IOA6/OSCI

Force to IOA6

Force to OSCI

IOA5/OSCO

Force to IOA5

IOA5/OSCO selected by OSCOUT bit

Force to OSCO

XT, LF

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3.0 INSTRUCTION SET

Mnemonic,

Operands

Status

Cycles

Description

Operation

0  R

Affected

BCR

R, bit Clear bit in R

R, bit Set bit in R

1

-

BSR

1  R

BTRSC

BTRSS

NOP

R, bit Test bit in R, Skip if Clear

R, bit Test bit in R, Skip if Set

No Operation

Skip if R = 0

Skip if R = 1

No operation

1/2⁽¹⁾

1

00h  WDT,

00h  WDT prescaler

00h  WDT,

00h  WDT prescaler

ACC=ROM{BANK index:

̅̅̅̅ ̅̅̅̅

CLRWDT

SLEEP

TABL

Clear Watchdog Timer

1

2

1

TO,PD

̅̅̅̅ ̅̅̅̅

Go into power-down mode

TO,PD

Read low byte ROM table to (acc)

R

-

ROM table address={TB_BNK,index of R} R}[7:0]

Read high byte ROM table to (acc)

ACC=ROM{BANK index :

TABH

R

ROM table address={TB_BNK,index of R} R}[15:8]

Adjust data format of register from HEX to

DAA

R, d

R(hex)  dest (dec)

C

DEC after any addition operation

Adjust data format of register from HEX to

DEC after any subtraction operation

DAS

R(hex)  dest (dec)

Top of Stack  PC

1

2

C

-

RETURN

RETFIE

Return from subroutine

Top of Stack  PC,

1  GIE

Return from interrupt, set GIE bit

-

RETF

Return from interrupt

Clear ACC

Top of Stack  PC,

00h  ACC

00h  R

2

1

-

Z

-

CLRA

CLRR

MOVAR

MOVR

MOV2

DECR

R

Clear R

Move ACC to R

ACC  R

R, d Move R

R  dest

Z

-

R, d Move R

R  dest

R, d Decrement R

R - 1  dest

Z

R - 1  dest,

Skip if result = 0

DECRSZ

INCR

R, d Decrement R, Skip if 0

R, d Increment R

1/2⁽¹⁾

1

-

Z

-

R + 1  dest

R + 1  dest,

Skip if result = 0

INCRSZ

R, d Increment R, Skip if 0

1/2⁽¹⁾

ADDAR

SUBAR

ADCAR

SBCAR

ANDAR

IORAR

XORAR

COMR

R, d Add ACC and R

R + ACC  dest

R - ACC  dest

1

C, DC, Z

R, d Subtract ACC from R

R, d Add ACC and R with Carry

R, d Subtract ACC from R with Carry

R, d AND ACC with R

C, DC, Z

R + ACC + C  dest

C, DC, Z

̅̅̅̅̅̅̅

R + ACC + C  dest

C, DC, Z

ACC and R  dest

ACC or R  dest

R xor ACC  dest

Z

R, d Inclusive OR ACC with R

R, d Exclusive OR ACC with R

R, d Complement R

ꢀ

R dest

R<6:0>  dest<7:1>,

R<7> dest<0>

R<7>  C,

R<6:0>  dest<7:1>,

C  dest<0>

RL

R, d Rotate left R

1

-

C

-

RLR

RL0

R, d Rotate left R through Carry

R, d Rotate left R through 0

R<6:0>  dest<7:1>,

0  dest<0>

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Mnemonic,

Operands

Status

Cycles

Description

Operation

Affected

R<6:0>  dest<7:1>,

1  dest<0>

RL1

RR

R, d Rotate left R through 1

1

-

R<7:1>  dest<6:0>,

R<0>  dest<7>

C  dest<7>,

R, d Rotate right R

RRR

R, d Rotate right R through Carry

R<7:1>  dest<6:0>,

R<0>  C

1

C

0  dest<7>,

R<7:1>  dest<6:0>,

1  dest<7>,

R<7:1>  dest<6:0>,

R<3:0>  dest<7:4>,

R<7:4>  dest<3:0>

RR0

R, d Rotate right R with 0

R, d Rotate right R with 1

R, d Swap R

1

-

RR1

SWAPR

MOVIA

ADDIA

SUBIA

ANDIA

IORIA

I

Move Immediate to ACC

I  ACC

1

-

Add ACC and Immediate

Subtract ACC from Immediate

AND Immediate with ACC

OR Immediate with ACC

I + ACC  ACC

I - ACC  ACC

ACC and I  ACC

ACC or I  ACC

ACC xor I  ACC

C, DC, Z

Z

XORIA

Exclusive OR Immediate to ACC

I  ACC,

RETIA

CALL

GOTO

I

Return, place Immediate in ACC

2

-

Top of Stack  PC

PC + 1  Top of Stack,

I  PC<10:0>

I <10:8>  PCHBUF<2:0>

I  PC<10:0>

Call subroutine

Unconditional branch

I <10:8>  PCHBUF<2:0>

TMSZA

If (ACC) =0, skip next instruction

If (R) =0, skip next instruction

Skip if ACC = 0

Skip if R = 0

1/2⁽¹⁾

-

TMSZR

R

TMSNZR

TMCOMP

If (R) ≠ 0, skip next instruction

If (acc) =(R), skip next instruction

If (acc) ≠(R), skip next instruction

Skip if R ≠ 0

Skip if (acc) =(R)

Skip if (acc) ≠ (R)

TMCOMPB R

Note: 1. 2 cycles for skip, else 1 cycle.

2. bit : Bit address within an 8-bit register R

R : Register address (00h to BFh)

I : Immediate data

ACC :Accumulator

d : Destination select;

=0 (store result in ACC)

=1 (store result in file register R)

dest : Destination

PC : Program Counter

WDT :Watchdog Timer Counter

GIE : Global interrupt enable bit

̅̅̅̅

TO : Time-out bit

̅̅̅̅

PD : Power-down bit

C : Carry bit

DC : Digital carry bit

Z : Zero bit

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FM8P756

ADCAR

Syntax:

Add ACC and R with Carry

ADCAR R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

R + ACC + C  dest

Status Affected:

Description:

C, DC, Z

Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is

stored in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

Cycles:

1

ADDAR

Syntax:

Add ACC and R

ADDAR R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

ACC + R  dest

Status Affected:

Description:

C, DC, Z

Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the

ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

Cycles:

1

ADDIA

Add ACC and Immediate

Syntax:

ADDIA I



Operands:

Operation:

Status Affected:

Description:

0 I 0xFF

ACC + I  ACC

C, DC, Z

Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the

ACC register.

1

Cycles:

ANDAR

Syntax:

AND ACC and R

ANDAR R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

ACC and R  dest

Status Affected:

Description:

Z

The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored

in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.

Cycles:

1

ANDIA

AND Immediate with ACC

Syntax:

ANDIA I



Operands:

Operation:

Status Affected:

Description:

0 I 0xFF

ACC AND I  ACC

Z

The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is

placed in the ACC register.

1

Cycles:

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FM8P756

BCR

Clear Bit in R

Syntax:

Operands:

BCR R, b



0 R 0xBF



0 b 7

Operation:

Status Affected:

Description:

Cycles:

0  R

None

Clear bit ‘b’ in register ‘R’.

1

BSR

Set Bit in R

Syntax:

Operands:

BSR R, b



0 R 0xBF



0 b 7

Operation:

Status Affected:

Description:

Cycles:

1  R

None

Set bit ‘b’ in register ‘R’.

1

BTRSC

Test Bit in R, Skip if Clear

Syntax:

BTRSC R, b



Operands:

0 R 0xBF



0 b 7

Operation:

Skip if R = 0

Status Affected:

Description:

None

If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.

If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is

discarded, and a NOP is executed instead making this a 2-cycle instruction.

1/2

Cycles:

BTRSS

Test Bit in R, Skip if Set

Syntax:

BTRSS R, b



Operands:

0 R 0xBF



0 b 7

Operation:

Skip if R = 1

Status Affected:

Description:

None

If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is

discarded and a NOP is executed instead, making this a 2-cycle instruction.

1/2

Cycles:

CALL

Subroutine Call

Syntax:

CALL I



Operands:

Operation:

0 I 0x7FF

PC + 1  Top of Stack,

I  PC<10:0>

I <10:8>  PCHBUF<2:0>

Status Affected:

Description:

None

Subroutine call. First, return address (PC+1) is pushed onto the stack. The 11-bit

immediate address is loaded into PC bits <10:0>.

2

Cycles:

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FM8P756

CLRA

Clear ACC

Syntax:

CLRA

Operands:

Operation:

None

00h  ACC;

1  Z

Status Affected:

Description:

Cycles:

Z

The ACC register is cleared. Zero bit (Z) is set.

1

CLRR

Clear R

Syntax:

CLRR

R



Operands:

Operation:

0 R 0xBF

00h  R;

1  Z

Status Affected:

Description:

Cycles:

Z

The contents of register ‘R’ are cleared and the Z bit is set.

1

CLRWDT

Syntax:

Clear Watchdog Timer

CLRWDT

Operands:

Operation:

None

00h  WDT;

̅̅̅̅

1  TO;

̅̅̅̅

1  PD

̅̅̅̅ ̅̅̅̅

Status Affected:

Description:

Cycles:

TO, PD

̅̅̅̅

The CLRWDT instruction resets the WDT. The status bits TO and PD will be set.

1

COMR

Complement R

Syntax:

COMR R, d



Operands:

0 R 0xBF

d

[0,1]



ꢀ

Operation:

R dest

Status Affected:

Description:

Z

The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC

register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

DAA

Adjust ACC’s data format from HEX to DEC

Syntax:

Operands:

DAA R, d



0 R 0xBF

d

[0,1]



Operation:

R(hex)  dest(dec)

Status Affected:

Description:

C

Convert the register data from hexadecimal to decimal format after any addition operation.

If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored back in

register ‘R’.

Cycles:

1

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FM8P756

DAS

Adjust ACC’s data format from HEX to DEC

DAS R, d

Syntax:

Operands:



0 R 0xBF

d

[0,1]



Operation:

R(hex)  dest(dec)

Status Affected:

Description:

C

Convert the register data from hexadecimal to decimal format after any subtraction

operation. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is stored

back in register ‘R’.

Cycles:

1

DECR

Decrement R

Syntax:

Operands:

DECR R, d



0 R 0xBF

d

[0,1]



Operation:

R - 1  dest

Status Affected:

Description:

Z

Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the

result is stored back in register ‘R’.

Cycles:

1

DECRSZ

Syntax:

Decrement R, Skip if 0

DECRSZ R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

R - 1  dest; skip if result =0

Status Affected:

Description:

None

The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is stored back in register ’R’.

If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is

executed instead and making it a two-cycle instruction.

1/2

Cycles:

GOTO

Unconditional Branch

Syntax:

GOTO

I

 

Operands:

Operation:

0 I 0x7FF

I  PC<10:0>

I <10:8>  PCHBUF<2:0>

Status Affected:

Description:

None

GOTO is an unconditional branch. The 11-bit immediate value is loaded into PC bits

<10:0>.

2

Cycles:

INCR

Increment R

Syntax:

Operands:

INCR R, d



0 R 0xBF

d

[0,1]



Operation:

R + 1  dest

Status Affected:

Description:

Z

The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.

If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

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FM8P756

INCRSZ

Syntax:

Increment R, Skip if 0

INCRSZ R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

R + 1  dest, skip if result = 0

Status Affected:

Description:

None

The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.

If ‘d’ is the result is stored back in register ‘R’.

If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP

is executed instead and making it a two-cycle instruction.

1/2

Cycles:

IORAR

OR ACC with R

Syntax:

IORAR R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

ACC or R  dest

Status Affected:

Description:

Z

Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is placed back in register ‘R’.

Cycles:

1

IORIA

OR Immediate with ACC

Syntax:

IORIA I

 

Operands:

Operation:

Status Affected:

Description:

0 I 0xFF

ACC or I  ACC

Z

The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is

placed in the ACC register.

1

Cycles:

MOVAR

Move ACC to R

Syntax:

MOVAR

R



Operands:

Operation:

Status Affected:

Description:

Cycles:

0 R 0xBF

ACC  R

None

Move data from the ACC register to register ‘R’.

1

MOVIA

Move Immediate to ACC

Syntax:

MOVIA I

 

Operands:

Operation:

Status Affected:

Description:

0 I 0xFF

I  ACC

None

The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as

0s.

1

Cycles:

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FM8P756

MOVR

Move R

Syntax:

MOVR R, d



Operands:

0 R 0xBF

d

[0,1]



Operation:

R  dest

Status Affected:

Description:

Z

The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC

register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register

since status flag Z is affected.

1

Cycles:

MOV2

Move R

Syntax:

Operands:

MOV2 R, d



0 R 0xBF

d

[0,1]



Operation:

R  dest

Status Affected:

Description:

None

The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC

register. If ‘d’ is 1, the destination is file register ‘R’. The zero status flag <Z> is not

affected.

1

Cycles:

NOP

No Operation

NOP

Syntax:

Operands:

Operation:

Status Affected:

Description:

Cycles:

None

No operation

None

No operation.

1

RETF

Return from Interrupt

Syntax:

RETF

Operands:

Operation:

Status Affected:

Description:

None

Top of Stack  PC

None

The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit

would NOT be set to 1. This is a two-cycle instruction.

2

Cycles:

RETFIE

Return from Interrupt, Set ‘GIE’ Bit

Syntax:

RETFIE

Operands:

Operation:

None

Top of Stack  PC

1  GIE

Status Affected:

Description:

None

The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit

is set to 1. This is a two-cycle instruction.

2

Cycles:

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RETIA

Return with Immediate in ACC

Syntax:

RETIA I

 

Operands:

Operation:

0 I 0xFF

I  ACC;

Top of Stack  PC

None

Status Affected:

Description:

The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded

from the top of the stack (the return address). This is a two-cycle instruction.

2

Cycles:

RETURN

Return from Subroutine

Syntax:

RETURN

Operands:

Operation:

Status Affected:

Description:

None

Top of Stack  PC

None

The program counter is loaded from the top of the stack (the return address). This is a two-

cycle instruction.

2

Cycles:

RL

Rotate Left R

Syntax:

Operands:

RL R, d



0 R 0xBF

d

[0,1]



Operation:

R<6:0>  dest<7:1>,

R<7> dest<0>

Status Affected:

Description:

None

The contents of register ‘R’ are rotated left one bit. If ‘d’ is 0 the result is placed in the ACC

register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

RL0

Rotate Left R with 0

Syntax:

Operands:

RL0 R, d



0 R 0xBF

d

[0,1]



Operation:

R<6:0>  dest<7:1>,

0  dest<0>

Status Affected:

Description:

None

The contents of register ‘R’ are rotated left one bit to the left and bit0 fills with “0”. If ‘d’ is 0

the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

RL1

Rotate Left R with 1

Syntax:

Operands:

RL1 R, d



0 R 0xBF

d

[0,1]



Operation:

R<6:0>  dest<7:1>,

1  dest<0>

Status Affected:

Description:

None

The contents of register ‘R’ are rotated left one bit to the left and bit0 fills with “1”. If ‘d’ is 0

the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

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FM8P756

RLR

Rotate Left R through Carry

Syntax:

Operands:

RLR R, d



0 R 0xBF

d

[0,1]



Operation:

R<7>  C;

R<6:0>  dest<7:1>;

C  dest<0>

C

Status Affected:

Description:

The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is

0 the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

RR

Rotate Right R

Syntax:

Operands:

RR R, d



0 R 0xBF

d

[0,1]



Operation:

R<7:1>  dest<6:0>,

R<0>  dest<7>

Status Affected:

Description:

None

The contents of register ‘R’ are rotated right one bit. If ‘d’ is 0 the result is placed in the

ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.

Cycles:

1

RR0

Rotate Right R with 0

Syntax:

Operands:

RR0 R, d



0 R 0xBF

d

[0,1]



Operation:

0  dest<7>,

R<7:1>  dest<6:0>

Status Affected:

Description:

None

The contents of register ‘R’ are rotated right one bit and bit7 fills with “0”. If ‘d’ is 0 the

result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.

Cycles:

1

RR1

Rotate Right R with 1

Syntax:

Operands:

RR1 R, d



0 R 0xBF

d

[0,1]



Operation:

1  dest<7>,

R<7:1>  dest<6:0>

Status Affected:

Description:

None

The contents of register ‘R’ are rotated right one bit and bit7 fills with “1”. If ‘d’ is 0 the

result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.

Cycles:

1

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FM8P756

RRR

Rotate Right R through Carry

Syntax:

Operands:

RRR R, d



0 R 0xBF

d [0,1]



Operation:

C  dest<7>;

R<7:1>  dest<6:0>;

R<0>  C

Status Affected:

Description:

C

The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0

the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.

Cycles:

1

SLEEP

Enter SLEEP Mode

SLEEP

Syntax:

Operands:

Operation:

None

00h  WDT;

̅̅̅̅

1  TO;

̅̅̅̅

0  PD

̅̅̅̅ ̅̅̅̅

Status Affected:

Description:

TO, PD

̅̅̅̅

Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT is

cleared.

The processor is put into SLEEP mode.

1

Cycles:

SBCAR

Syntax:

Subtract ACC from R with Carry

SBCAR R, d



Operands:

0 R 0xBF

d [0,1]



̅̅̅̅̅̅̅

Operation:

R + ACC + C  dest

Status Affected:

Description:

C, DC, Z

Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the

result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

SUBAR

Syntax:

Subtract ACC from R

SUBAR R, d



Operands:

0 R 0xBF

d [0,1]



Operation:

R - ACC  dest

Status Affected:

Description:

C, DC, Z

Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is

stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

SUBIA

Subtract ACC from Immediate

Syntax:

SUBIA I

 

Operands:

Operation:

Status Affected:

Description:

0 I 0xFF

I - ACC  ACC

C, DC, Z

Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result

is placed in the ACC register.

1

Cycles:

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FM8P756

SWAPR

Syntax:

Swap nibbles in R

SWAPR R, d



Operands:

0 R 0xBF

d [0,1]



Operation:

R<3:0>  dest<7:4>;

R<7:4>  dest<3:0>

None

Status Affected:

Description:

The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in

ACC register. If ‘d’ is 1 the result in placed in register ‘R’.

Cycles:

1

TABL

Table Look-up Low Byte

Syntax:

TABL R



Operands:

Operation:

Status Affected:

Description:

0 R 0xBF

ACC=ROM{TB_BNK index : R}[7:0]

None

Read low byte ROM table to (ACC)

ROM table address={TB_BNK index : R}

2

Cycles:

TABH

Table Look-up High Byte

Syntax:

TABH R



Operands:

Operation:

Status Affected:

Description:

0 R 0xBF

ACC=ROM{TB_BNK index : R}[15:8]

None

Read High byte ROM table to (ACC)

ROM table address={TB_BNK index : R}

2

Cycles:

TMCOMP

Test ACC and R, Skip if equal

Syntax:

TMCOMP

R



Operands:

Operation:

Status Affected:

Description:

0 R 0xBF

Skip if ACC = R

None

If ACC is equal to R then the next instruction is skipped.

If ACC is equal to R then next instruction fetched during the current instruction execution is

discarded, a NOP is executed instead and making this a 2-cycle instruction.

1/2

Cycles:

TMCOMPB

Syntax:

Test ACC and R, Skip if not equal

TMCOMPB

R



Operands:

Operation:

Status Affected:

Description:

0 R 0xBF

Skip if ACC ≠ R

None

If ACC is not equal to R then the next instruction is skipped.

If ACC is not equal to R then next instruction fetched during the current instruction execution

is discarded, a NOP is executed instead and making this a 2-cycle instruction.

1/2

Cycles:

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TMSZA

Test ACC, Skip if equal to 0

Syntax:

TMSZA

Operands:

Operation:

Skip if ACC = 0

Status Affected:

Description:

None

If ACC is equal to 0 then the next instruction is skipped.

If ACC is equal to 0 then next instruction fetched during the current instruction execution is

discarded, a NOP is executed instead and making this a 2-cycle instruction.

1/2

Cycles:

TMSNZR

Test R, Skip if not equal to 0

Syntax:

TMSNZR

R



Operands:

Operation:

Status Affected:

Description:

0 R 0xBF

Skip if R ≠ 0

None

If R is not equal to 0 then the next instruction is skipped.

If R is not equal to 0 then next instruction fetched during the current instruction execution is

discarded, a NOP is executed instead and making this a 2-cycle instruction.

1/2

Cycles:

TMSZR

Test R, Skip if equal to 0

Syntax:

TMSZR

R



Operands:

Operation:

Status Affected:

Description:

0 R 0xBF

Skip if R = 0

None

If R is equal to 0 then the next instruction is skipped.

If R is equal to 0 then next instruction fetched during the current instruction execution is

discarded, a NOP is executed instead and making this a 2-cycle instruction.

1/2

Cycles:

XORAR

Syntax:

Exclusive OR ACC with R

XORAR R, d



Operands:

0 R 0xBF



d [0,1]

Operation:

ACC xor R  dest

Status Affected:

Description:

Z

Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is

stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.

Cycles:

1

XORIA

Exclusive OR Immediate with ACC

Syntax:

XORIA I

 

Operands:

Operation:

Status Affected:

Description:

0 I 0xFF

ACC xor I  ACC

Z

The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is

placed in the ACC register.

1

Cycles:

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.60/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

4.0 ABSOLUTE MAXIMUM RATINGS

Ambient Operating Temperature

Store Temperature

-40℃ to +85℃

-65℃ to +150℃

0V to +6.0V

DC Supply Voltage (Vdd)

Input Voltage with respect to Ground (Vss)

-0.3V to (Vdd + 0.3)V

5.0 OPERATING CONDITIONS

DC Supply Voltage

+2.2V to +5.5V

Operating Temperature

-40℃ to +85℃

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.61/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

6.0 ELECTRICAL CHARACTERISTICS

6.1 ELECTRICAL CHARACTERISTICS of FM8P756A/B/C/D/E/F/G

Ta=25℃

Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled

Sym

Description

Conditions

Min.

Typ.

2.2

2.4

2.6

2.8

3.4

4.0

Max.

5.5

2.6

20

Unit

V

0Hz ~ 4MHz

4MHz ~ 8MHz

8MHz ~ 10MHz

V_DD

Supply voltage

10MHz ~ 12MHz

12MHz ~ 16MHz

16MHz ~ 20MHz

T_PWRPower rising time

Vdd=0V to Vdd

0.8

ms/V

MHz

XT mode, Vdd=5V, Fcpu=Fosc/2

XT mode, Vdd=3V, Fcpu=Fosc/2

LF mode, Vdd=5V, Fcpu=Fosc/2

LF mode, Vdd=3V, Fcpu=Fosc/2

ERC mode, Vdd=5V, Fcpu=Fosc/2

ERC mode, Vdd=3V, Fcpu=Fosc/2

With schmitter

F_XT

F_LF

X’tal oscillation range

15

4000

1000

15

KHZ

MHz

F_ERCRC oscillation range

7

V_IH

Input high voltage

Input low voltage

I/O ports

0.7Vdd

0.8Vdd

Vdd

V

RSTB pin

With schmitter

V_IL

I/O ports

Vss

0.2Vdd

RSTB pin

0.2Vdd

Vin=5V, Vdd=5V

1

I_IL

Input Leakage Current

IO Drive Current

uA

Vin=0V, Vdd=5V

VOH=4.5V, Vdd=5V

VOH=4V, Vdd=5V

VOL=0.5V, Vdd=5V

8

I_OH

mA

15

14

I_OL

IO Sink Current

Pull-high resister

WDT current

mA

KΩ

uA

VOL=0.75V, Vdd=5V

Input pin at Vss, vdd=5V

Input pin at Vss, vdd=3V

Vdd=5V

21

145

290

8

65

195

375

R_PH

I_WDT

125

Vdd=3V

2

Vdd=3V

24

20

2

T_WDTWDT period

mS

Vdd=5V

LVDT=3.7V, vdd=5V

LVDT=2.6V, vdd=5V

LVDT=2.6V, vdd=3V

LVDT=2.2V, vdd=5V

LVDT=2.2V, vdd=3V

LVDT=3.7V

3

I_LVDT

LVDT current

0.5

3

uA

V

0.5

3.7

2.6

2.2

3.5

2.4

2.0

0

3.9

2.8

2.4

Vdd

10

V_LVDTLVDT voltage

LVDT=2.6V

LVDT=2.2V

V_AD

R_AD

A/D input Voltage

Resolution

V

Bits

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.62/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

Sym

DNL

Description

Conditions

Min.

Typ.

Max.

Unit

A/D Differential Non-

Linear

1

LSB

A/D Integral Non-

Linear

INL

2

LSB

uA

Vdd=5V, 4 clock instruction

Vdd=5V, 2 clock instruction

Vdd=3V, 4 clock instruction

Vdd=3V, 2 clock instruction

470

440

80

I_ADC

A/D Operation Current

A/D clock period

40

T_AD

8

us

T_ADCA/D Conversion Time

T_ADCSA/D Sampling Time

25

8

T_AD

Sleep mode, Vdd=5V, WDT disable,

LVDT off

1

I_SB

Power down current

uA

Sleep mode, Vdd=3V, WDT disable,

LVDT off

Vdd=5V, COMIS[1:0] = 0 0

Vdd=5V, COMIS[1:0] = 0 1

Vdd=5V, COMIS[1:0] = 1 0

Vdd=5V, COMIS[1:0] = 1 1

17.5

35

25

50

32.5

65

COM Operating

current

I_COM

uA

70

100

200

0.5

130

260

0.525

140

0.475

V_COM1/2 bias voltage range Vdd=5V, No load

IRC mode, vdd=5V, 4 clock instruction

VDD

SYS_CK=8 MHz

2.27

1.63

SYS_CK=4 MHz

IRC mode, vdd=5V, 2 clock instruction

SYS_CK=8 MHz

3.64

2.28

SYS_CK=4 MHz

I_DD

Operating current

mA

IRC mode, vdd=3V, 4 clock instruction

SYS_CK=8 MHz

1.15

0.80

SYS_CK=4 MHz

IRC mode, vdd=3V, 2 clock instruction

SYS_CK=8 MHz

1.62

1.13

SYS_CK=4 MHz

XT mode, vdd=5V, 4 clock instruction

20 MHz

4.92

3.99

3.18

1.40

16 MHz

12 MHz

4 MHz

I_DD

Operating current

mA

XT mode, vdd=5V, 2 clock instruction

20 MHz

16 MHz

12 MHz

4 MHz

6.88

5.95

5.03

2.08

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.63/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

Sym

Description

Conditions

Min.

Typ.

Max.

Unit

XT mode, vdd=3V, 4 clock instruction

20 MHZ

1.9

16 MHz

1.64

1.40

0.56

12 MHz

4 MHz

I_DD

Operating current

mA

XT mode, vdd=3V, 2 clock instruction

20 MHZ

-

16 MHz

-

12 MHz

1.96

0.88

4 MHz

LF mode, Vdd=5V, 4 clock instruction

32 KHz

35

40.8

8.8

11.4

13

I_DD

Operating current

uA

LF mode, Vdd=5V, 2 clock instruction

32 KHz

LF mode, Vdd=3V, 4 clock instruction

32 KHz

LF mode, Vdd=3V, 2 clock instruction

32 KHz

LIRC mode, Vdd=5V, 4 clock instruction

Near 12 KHz

LIRC mode, Vdd=5V, 2 clock instruction

Near 12 KHz

15

LIRC mode, Vdd=3V, 4 clock instruction

Near 12 KHz

3

LIRC mode, Vdd=3V, 2 clock instruction

Near 12 KHz

4

Note: LIRC 12 KHz is an uncalibrated low-frequency oscillator, current is for reference only.

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.64/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

6.2 ELECTRICAL CHARACTERISTICS Charts of FM8P756A/B/C/D/E/F/G

6.2.1

Operator Frequency vs. Operator voltage (Ta=25℃, 2 clock instruction)

20MHz

16MHz

8MHz

4MHz

1MHz

455KHz

32KHz

Near 0Hz

2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

6.2.2

Internal 8MHz RC vs. Temperature

8.00%

6.00%

4.00%

2.00%

0.00%

-2.00%

-4.00%

-6.00%

-8.00%

Avg-5V

Avg-3V

-40 -30 -20 -10

0

10 20 25 30 40 50 60 70 80 90 100 110 120 125

Temperature

Note: Curves are for design reference only.

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.65/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

6.2.3

Internal 8MHz RC vs. Supply Voltage (Ta=25℃)

3.00%

2.00%

1.00%

0.00%

8M HV

8M LV

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6 5.8

6

-1.00%

-2.00%

-3.00%

-4.00%

-5.00%

Voltage

Note: Curves are for design reference only.

Internal 12KHz RC vs. Temperature

6.2.4

60.00%

40.00%

20.00%

0.00%

Avg-5V

Avg-3V

-40 -30 -20 -10

0

10 20 25 30 40 50 60 70 80 90 100 110 120 125

-20.00%

-40.00%

-60.00%

Temperature

Note: 1. Curves are for design reference only.

2. 12 KHz is an uncalibrated low-frequency oscillator

6.2.5

Internal 12KHz RC vs. Supply Voltage (Ta=25℃)

40.00%

30.00%

20.00%

10.00%

0.00%

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6 5.8

12K HV

6

-10.00%

-20.00%

-30.00%

12K LV

Voltage

Note: 1. Curves are for design reference only.

2. 12 KHz is an uncalibrated low-frequency oscillator

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.66/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

6.2.6

Low Voltage Detect (LVDT=2.2V) vs. Temperature

3.00

Avg-2.2V

2.50

2.00

1.50

1.00

0.50

0.00

-40 -30 -20 -10

0

10 20 25 30 40 50 60 70 80 90 100 110 120 125

Temperature

Note: Curves are for design reference only.

6.2.7

Low Voltage Detect (LVDT=2.6V) vs. Temperature

3.00

2.50

2.00

1.50

1.00

0.50

0.00

Avg-2.6V

-40 -30 -20 -10

0

10 20 25 30 40 50 60 70 80 90 100 110 120 125

Temperature

Note: Curves are for design reference only.

6.2.8 Low Voltage Detect (LVDT=3.7V) vs. Temperature

5.00

4.00

3.00

2.00

1.00

0.00

Avg-3.7V

-40 -30 -20 -10

0

10 20 25 30 40 50 60 70 80 90 100 110 120 125

Temperature

Note: Curves are for design reference only.

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.67/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

6.2.9 WDT 20mS Reset time vs. Temperature

45.00

40.00

35.00

30.00

25.00

20.00

15.00

10.00

5.00

Avg-5V

Avg-3V

0.00

-40 -30 -20 -10

0

10 20 25 30 40 50 60 70 80 90 100 110 120 125

Temperature

Note: Curves are for design reference only.

6.2.10 WDT 20mS Reset time vs. Supply Voltage (Ta=25℃)

30.00

25.00

20.00

15.00

10.00

5.00

Avg-20mS

0.00

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6 5.8

6

Voltage

Note: Curves are for design reference only.

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.68/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.0 PACKAGE DIMENSION

7.1 16-PIN PDIP 300mil

Dimension In Inches

Symbols

Min

-

Nom

-

Max

0.210

-

A

A1

A2

D

0.015

0.125

0.735

-

0.130

0.755

0.300 BSC

0.250

0.130

0.355

7°

0.135

0.775

E

E1

L

0.245

0.115

0.335

0°

0.255

0.150

0.375

15°

eB

θ°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.69/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.2 16-PIN SOP 150mil

Dimension In Inches

Symbols

Min

Max

0.069

0.010

0.065

0.394

0.157

0.244

0.050

8°

A

A1

A2

D

0.053

0.004

0.049

0.386

0.150

0.228

0.016

0°

E

H

L

θ°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.70/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.3 18-PIN PDIP 300mil

D

C

TOP E-PIN INDENT £ 0.079

BOTTOM E-PIN INDENT £ 0.118

0.727

e

B

B1

D1

Dimension In Inches

Symbols

Min

Nom

-

Max

0.180

-

A

A1

A2

B

-

0.05

-

0.130

0.018

0.060

0.010

0.904

0.022

-

0.140

0.022

0.070

0.013

0.910

0.027

0.325

0.262

-

0.014

0.050

0.008

0.894

0.017

0.300

0.252

-

B1

C

D

D1

E

E1

e

0.256

0.100

-

L

0.125

-

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.71/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.4 18-PIN SOP 300mil

View “

A

D

View “

A

7^o(4x)

e

B

£

L

Dimension In Inches

Symbols

Min

0.093

0.04

-

Nom

0.098

-

Max

0.104

0.012

-

A

A1

A2

B

0.091

0.016

0.009

-

0.013

0.007

0.447

0.291

-

0.020

0.011

0.463

0.299

-

C

D

E

0.295

0.050

0.406

0.032

-

e

H

0.394

0.015

0^o

0.419

0.050

8^o

L

θ^o

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.72/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.5 20-PIN PDIP 300mil

Dimension In Inches

Symbols

Min

-

Nom

-

Max

0.210

-

A

A1

A2

D

0.015

0.125

0.98

-

0.130

1.030

0.300 BSC

0.250

0.130

0.355

7°

0.135

1.060

E

E1

L

0.245

0.115

0.335

0°

0.255

0.150

0.375

15°

eB

θ°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.73/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.6 20-PIN SOP 300mil

Dimension In Inches

Symbols

Min

Nom

Max

0.104

0.012

0.508

0.299

0.419

0.050

8°

A

A1

D

0.093

0.004

0.496

0.291

0.394

0.016

0°

-

E

H

L

θ°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.74/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.7 20-PIN SSOP 209 mil

Dimension In Millimeters

Symbols

Min

-

Nom

-

Max

2.00

-

A

A1

A2

b

0.05

1.65

0.22

0.09

6.90

7.40

5.00

-

1.75

-

1.85

0.38

0.21

7.50

8.20

5.60

-

c

-

D

7.20

7.80

5.30

0.65

0.75

1.25

4°

E

E1

e

L

0.55

-

0.95

-

L1

θ°

0°

8°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.75/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.8 24-PIN Skinny PDIP 300mil

Dimension In Inches

Symbols

Min

-

Nom

-

Max

0.210

-

A

A1

A2

D

0.015

0.125

1.230

-

0.130

1.250

0.300 BSC.

0.258

0.130

0.355

7°

0.135

1.280

E

E1

L

0.253

0.115

0.335

0°

0.263

0.150

0.375

15°

eB

θ°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.76/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.9 24-PIN SOP 300mil

Dimension In Inches

Symbols

Min

-

Nom

-

Max

0.104

-

A

A1

D

0.004

0.599

0.291

0.394

0.016

0°

-

0.600

0.295

0.406

0.035

4°

0.624

0.299

0.419

0.050

8°

E

H

L

θ°

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.77/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.10 28-PIN Skinny PDIP 300mil

D

C

1.000?

PIN 1 INDENT

e

B

B1

B2

Dimension In Inches

Symbols

Min

Nom

Max

0.180

-

A

A1

A2

B

-

0.015

-

0.130

0.140

0.065

0.023

0.044

0.013

1.395

0.330

0.296

-

0.0040

0.016

0.028

0.008

1.383

0.310

0.284

-

B1

B2

C

-

0.010

1.385

0.327

0.288

0.100

-

D

E

E1

e

L

0.125

0.340

-

eB

-

0.380

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.78/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

7.11 28-PIN SOP 300mil

View “

A

D

View “

A

7^o(4x)

e

D1

B

£

L

Dimension In Inches

Symbols

Min

-

Nom

0.098

-

Max

0.108

-

A

A1

A2

B

0.006

0.087

0.012

0.008

0.700

0.290

0.048

0.404

0.025

0^o

0.091

0.016

0.010

0.705

0.295

0.050

0.410

-

0.097

0.020

0.012

0.725

0.300

0.052

0.416

-

C

D

E

e

eB

L

θ

4^o

8^o

D1

0.014

0.020

-

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.79/FM8P756

FEELING

FM8P756

T

ECHNOLOGY

8.0 PACKAGE IR Re-flow Soldering Curve

250 5

10 1 sec

150 10

90 30 sec

2 ~ 5 / sec

Time

9.0 ORDERING INFORMATION

OTP Type MCU

FM8P756AM

FM8P756AD

FM8P756BP

FM8P756BD

FM8P756BR

FM8P756CP

FM8P756CD

FM8P756DM

FM8P756DD

FM8P756EM

FM8P756ED

FM8P756FP

FM8P756FD

FM8P756GP

FM8P756GD

Package Type

Pin Count

24

Package Size

SAMPLE Stock

No stock

Available

No stock

Available

No stock

Available

No stock

Available

No stock

Available

No stock

Available

SKINNY-DIP

SOP

300 mil

209 mil

300 mil

150 mil

300 mil

24

DIP

20

SOP

20

SSOP

DIP

20

16

SOP

16

SKINNY-DIP

SOP

28

SKINNY-DIP

SOP

24

DIP

18

SOP

18

DIP

20

SOP

20

Web site: http://www.feeling-tech.com.tw

Rev 1.01.020 Nov 12, 2014

P.80/FM8P756


型号：	FM8P756
厂家：	Feeling Technology
描述：	OTP-Based 8-Bit Microcontroller with LCD Driver CD 微控制器
文件：	总80页 (文件大小：3432K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FM8P756 [FEELING]

相关型号：

FM8P756A

FM8P756AD

FM8P756AM

FM8P756B

FM8P756BD

FM8P756BP

FM8P756BR

FM8P756C

FM8P756CD

FM8P756CP

FM8P756D

FM8P756DD