FM8PB56BAR [FEELING]
OTP-Based 8-Bit Microcontroller;型号: | FM8PB56BAR |
厂家: | Feeling Technology |
描述: | OTP-Based 8-Bit Microcontroller 微控制器 |
文件: | 总53页 (文件大小:2342K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EELING
FM8PB56B
OTP-Based 8-Bit Microconer
Devices Included in this Data Sheet:
FM8PB56B : OTP device
FEATURES
Only 42 single word instructions
All instructions are single cycle except for program branches which are two-cycle
13-bit wide instructions
All OTP area GOTO instruction
All OTP area subroutine CALL instruction
8-bit wide data path
5-level deep hardware stack
Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O #
OTP (Byte)
RAM (Byte)
FM8PB56B
18 16
1K
49
Direct, indirect addressing modes for data accessing
8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
Internal Power-on Reset (POR)
Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
Two I/O ports IOA and IOB with independent direction control
Soft-ware I/O pull-high/pull-down or open-drain control
One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
Wake-up from SLEEP by INT pin or Port B input change
Power saving SLEEP mode
Built-in 8 MHz, 4 MHz, 1 MHz, and 455 KHz internal RC oscillator
Programmable Code Protection
Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
Operating voltage range: 2.0V to 5.5V
- ≤4MHz: 2.0V to 5.5V
- ≤8MHz: 2.4V to 5.5V, see 6.1 for more information.
This datasheet contains on. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a rethis product. No rights under any patent accompany the sales of the product.
Web site: http://www.feeling-teom.tw
Rev1.0.004 Aug 21, 2014
P.1/FM8PB56B
EELING
FM8PB56B
GENERAL DESCRIPTION
The FM8PB56B is a low-cost, high speed, high noise immunity, OTP-based 8-bit CMOS microcontrollers. It
employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program
branches which take two cycles. The easy to use and easy to remember instruction set reduces development
time significantly.
The FM8PB56B consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Oscillator Start-up Timer(OST), Watchdog Timer, OTP, SRAM, tri-state I/O port, I/O pull-high/open-drain/pull-down
control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP
mode, and Code Protection for OTP products. There are three oscillator configurations to choose from, including
the power-saving LF (Low Frequency) oscillator and cost saving RC oscillator.
The FM8PB56B address 1K×13 of program memory.
The FM8PB56B can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
DATA BUS
Oscillator
Circuit
5-level
STACK
Control
Interrupt
Watchdog
Timer
Program
Counter
FSR
SRAM
PORTA
PORTB
Instruction
Decoder
ALU
OTP-ROM
Interrupt
Control
8-bit Timer0
Accumulator
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.2/FM8PB56B
EELING
FM8PB56B
PIN CONNECTION
PDIP, SOP
SSOP
IOA2
IOA3
1
2
3
4
5
6
7
8
9
20 IOA1
IOA2
IOA3
1
2
3
4
5
6
7
8
9
18 IOA1
19 IOA0
17 IOA0
IOA4/T0CKI
IOA5/RSTB
VSS
18 IOA7/OSCI
17 IOA6/OSCO
IOA4/T0CKI
IOA5/RSTB
VSS
16 IOA7/OSCI
15 IOA6/OSCO
14 VDD
16 VDD
FM8PB56B
FM8PB56B
VSS
15 VDD
14 IOB7
13 IOB6
12 IOB5
11 IOB4
IOB0/INT
IOB1
13 IOB7
IOB0/INT
IOB1
12 IOB6
IOB2
11 IOB5
IOB2
IOB3
10 IOB4
IOB3 10
PIN DESCRIPTIONS
Name
I/O
I/O
Description
Bi-direction I/O pins
Software controlled pull-down
Bi-direction I/O pin with system wake-up function /External interrupt input
IOA0 ~ IOA3
IOB0/INT
IOB1~IOB7
IOA4/T0CKI
I/O Software controlled pull-down
Software controlled pull-high/open-drain
Bi-direction I/O port with system wake-up function
I/O IOB1 ~ IOB3 software controlled pull-down
IOB1 ~ IOB7 software controlled pull-high/open-drain
Bi-direction I/O pin
I/O Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current
consumption
Input pin or open-drain output pin
System clear (RESET) input. Active low RESET to the device.
Voltage on this pin must not exceed VDD, See IOA5 diagram for detail
IOA5/RSTB
I/O
description.
Bi-direction I/O pin (RCOUT optional in IRC/ERIC, ERC mode)
I/O Oscillator crystal output (HF, XT, LF mode)
Outputs with the instruction cycle rate (RCOUT optional in IRC/ERIC, ERC mode)
Bi-direction I/O pin (IRC mode)
I/O Oscillator crystal input (HF, XT, LF mode)
External clock source input (ERIC, ERC mode)
IOA6/OSCO
IOA7/OSCI
Vdd
Vss
-
-
Positive supply
Ground
Legend: I=input, O=output, I/O=input/output
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.3/FM8PB56B
EELING
FM8PB56B
1.0 MEMORY ORGANIZATION
FM8PB56B memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PB56B have a 10-bit Program Counter capable of addressing a 1K×13 program memory space.
The RESET vector for the FM8PB56B is at 3FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
FM8PB56B supports all OTP area CALL/GOTO instructions without page.
Figure 1.1: Program Memory Map and STACK
PC<9:0>
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
3FFh
Reset Vector
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8PB56B
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.4/FM8PB56B
EELING
FM8PB56B
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
Table 1.1: Registers File Map for FM8PB56B
Address
00h
Description
INDF
TMR0
01h
02h
PCL
N/A
OPTION
03h
STATUS
04h
FSR
05h
PORTA
05h
06h
IOSTA
IOSTB
06h
PORTB
07h
General Purpose Register
PCON
08h
09h
WUCON
0Ah
PCHBUF
0Bh
PDCON
0Ch
0Dh
0Eh
ODCON
PHCON
INTEN
0Fh
INTFLAG
General Purpose Registers
10h ~ 3Fh
Table 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
N/A (w)
05h (w)
06h (w)
Name
OPTION
IOSTA
B7
-
B6
B5
B4
B3
B2
B1
B0
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Port A I/O Control Register
Port B I/O Control Register
IOSTB
Table 1.3: Operational Registers Map
Address
00h (r/w)
01h (r/w)
02h (r/w)
03h (r/w)
04h (r/w)
05h (r/w)
06h (r/w)
07h (r/w)
08h (r/w)
09h (r/w)
0Ah (r/w)
0Bh (r/w)
0Ch (r/w)
0Dh (r/w)
0Eh (r/w)
0Fh (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
C
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
TMR0
PCL
Low order 8 bits of PC
̅̅̅̅
̅̅̅̅
PD
STATUS
FSR
GP2
*
GP1
*
GP0
TO
Z
DC
Indirect data memory address pointer
PORTA
PORTB
SRAM
IOA7
IOB7
IOA6
IOB6
IOA5
IOB5
IOA4
IOB4
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
General Purpose Register
PCON
WDTE
WUB7
-
EIS
WUB6
-
LVDTE
WUB5
-
ROC
WUB4
-
-
-
-
-
WUCON
PCHBUF
PDCON
ODCON
PHCON
INTEN
INTFLAG
WUB3
WUB2
-
WUB1
WUB0
-
2 MSBs Buffer of PC
/PDB3
ODB7
/PHB7
GIE
/PDB2
ODB6
/PHB6
-
/PDB1
ODB5
/PHB5
-
/PDB0
ODB4
/PHB4
-
/PDA3
ODB3
/PHB3
-
/PDA2
ODB2
/PHB2
INTIE
INTIF
/PDA1
ODB1
/PHB1
PBIE
/PDA0
ODB0
/PHB0
T0IE
-
-
-
-
-
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’,
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.5/FM8PB56B
EELING
FM8PB56B
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1
INDF (Indirect Addressing Register)
Address
00h (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
Uses contents of FSR to address data memory (not a physical register)
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the
INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh).
Example 2.1: INDIRECT ADDRESSING
Register file 38 contains the value 10h
Register file 39 contains the value 0Ah
Load the value 38 into the FSR Register
A read of the INDF Register will return the value of 10h
Increment the value of the FSR Register by one (@FSR=39h)
A read of the INDF register now will return the value of 0Ah.
Figure 2.1: Direct/Indirect Addressing
Direct Addressing
From opcode
Indirect Addressing
From FSR register 0
5
0
5
00h
location select
addressing INDF register
location select
3Fh
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.6/FM8PB56B
EELING
FM8PB56B
2.1.2
TMR0 (Time Clock/Counter register)
Address
01h (r/w)
Name
TMR0
B7
B6
B5
B4
B3
B2
B1
B0
8-bit real-time clock/counter
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is
increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).
The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be
cleared when TMR0 register is written with a value.
2.1.3
PCL (Low Bytes of Program Counter) & Stack
Address
02h (r/w)
Name
PCL
B7
B6
B5
B4
B3
B2
B1
B0
Low order 8 bits of PC
FM8PB56B device has a 10-bit wide Program Counter (PC) and five-level deep 10-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called
the PCH register. This register contains the PC<9:8> bits and is not directly readable or writable. All updates to
the PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter
will contain the address of the next program instruction to be executed. The PC value is increased by one, every
instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PCL register is mapped to
PC<7:0>, and the PCHBUF register is not updated.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The next PC will be loaded
(PUSHed) onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not
updated.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU
result. However, the PC<9:8> will come from the PCHBUF<1:0> bits (PCHBUF PCH).
PCHBUF register is never updated with the contents of PCH.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.7/FM8PB56B
EELING
FM8PB56B
Figure 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
PCL
9
8
-
7
-
0
PC
Opcode <9:0>
-
-
-
-
PCHBUF
Situation 2: CALL Instruction
STACK<9:0>
Opcode <9:0>
PCH
PCL
9
8
7
-
0
PC
-
-
-
-
-
PCHBUF
Situation 3: RETIA, RETFIE, or RETURN Instruction
PCH PCL
STACK<9:0>
9
8
7
0
PC
-
-
-
-
-
-
PCHBUF
Situation 4: Instruction with PCL as destination
PCH PCL
8
9
7
0
PC
ALU result <7:0>
Or Opcode <7:0>
PCHBUF<1:0>
-
-
-
-
-
-
PCHBUF
Note: PCHBUF is used only for instruction with PCL as destination for FM8PB56B.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.8/FM8PB56B
EELING
FM8PB56B
2.1.4
STATUS (Status Register)
Address
03h (r/w)
Name
B7
B6
B5
B4
B3
̅̅̅̅
PD
B2
Z
B1
B0
C
̅̅̅̅
STATUS
GP2
GP1
GP0
TO
DC
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
̅̅̅̅
̅̅̅̅
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD
bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be
different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves
the STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR, ADDIA
= 1, Carry occurred.
= 0, No Carry occurred.
SUBAR, SUBIA
= 1, No borrow occurred.
= 0, Borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR,
RLR) instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit
ADDAR, ADDIA
= 1, Carry from the 4th low order bit of the result occurred.
= 0, No Carry from the 4th low order bit of the result occurred.
SUBAR, SUBIA
= 1, No Borrow from the 4th low order bit of the result occurred.
= 0, Borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, The result of a logic operation is zero.
= 0, The result of a logic operation is not zero.
̅̅̅̅
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
̅̅̅̅
TO : Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction
= 0, a watch-dog time overflow occurred
GP2:GP0 : General purpose read/write bits.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.9/FM8PB56B
EELING
FM8PB56B
2.1.5
FSR (Indirect Data Memory Address Pointer)
Address
04h (r/w)
Name
FSR
B7
*
B6
*
B5
B4
B3
B2
B1
B0
Indirect data memory address pointer
Legend: * = unimplemented, read as ‘1’.
Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
2.1.6 PORTA, PORTB (Port Data Registers)
Address
Name
PORTA
PORTB
B7
B6
B5
B4
B3
B2
B1
B0
05h (r/w)
06h (r/w)
IOA7
IOB7
IOA6
IOB6
IOA5
IOB5
IOA4
IOB4
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
Reading the port (PORTA, PORTB register) reads the status of the pins independent of the pin’s input/output
modes. Writing to these ports will write to the port data latch.
PORTA and PORTB are 8-bit port data Registers.
IOA7:IOA0 : PORTA I/O pin.
= 1, Port pin is high level.
= 0, Port pin is low level.
Note: IOA5 is open-drain output only if IOSTA5 = 0. See 2.1.17 for detail description.
IOB7:IOB0 : PORTB I/O pin.
= 1, Port pin is high level.
= 0, Port pin is low level.
2.1.7
PCON (Power Control Register)
Address
08h (r/w)
Name
PCON
B7
B6
B5
B4
B3
-
B2
-
B1
-
B0
-
WDTE
EIS
LVDTE
ROC
Legend: - = unimplemented, read as ‘0’.
ROC : R-option function of IOA0 and IOA1 pins enable bit.
= 1, Enable the R-option function. In this case, if a 430KΩ external resister is connected/disconnected to
Vss, the status of IOA0 (IOA1) is read as “0”/”1”.
= 0, Disable the R-option function.
LVDTE : LVDT (low voltage detector) enable bit.
= 1, Enable LVDT.
= 0, Disable LVDT.
EIS : Define the function of IOB0/INT pin.
= 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The
path of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read
by way of reading PORTB.
= 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked.
WDTE : WDT (watch-dog timer) enable bit.
= 1, Enable WDT.
= 0, Disable WDT.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.10/FM8PB56B
EELING
FM8PB56B
2.1.8
WUCON (Port B Input Change Interrupt/Wake-up Control Register)
Address
09h (r/w)
Name
B7
B6
B5
B4
B3
B2
B1
B0
WUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
WUB0 : = 1, Enable the input change interrupt/wake-up function of IOB0 pin.
= 0, Disable the input change interrupt/wake-up function of IOB0 pin.
WUB1 : = 1, Enable the input change interrupt/wake-up function of IOB1 pin.
= 0, Disable the input change interrupt/wake-up function of IOB1 pin.
WUB2 : = 1, Enable the input change interrupt/wake-up function of IOB2 pin.
= 0, Disable the input change interrupt/wake-up function of IOB2 pin.
WUB3 : = 1, Enable the input change interrupt/wake-up function of IOB3 pin.
= 0, Disable the input change interrupt/wake-up function of IOB3 pin.
WUB4 : = 1, Enable the input change interrupt/wake-up function of IOB4 pin.
= 0, Disable the input change interrupt/wake-up function of IOB4 pin.
WUB5 : = 1, Enable the input change interrupt/wake-up function of IOB5 pin.
= 0, Disable the input change interrupt/wake-up function of IOB5 pin.
WUB6 : = 1, Enable the input change interrupt/wake-up function of IOB6 pin.
= 0, Disable the input change interrupt/wake-up function of IOB6 pin.
WUB7 : = 1, Enable the input change interrupt/wake-up function of IOB7 pin.
= 0, Disable the input change interrupt/wake-up function of IOB7 pin.
2.1.9
PCHBUF (High Byte Buffer of Program Counter)
Address
0Ah (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
-
B1
B0
PCHBUF
2 MSBs Buffer of PC
Legend: - = unimplemented, read as ‘0’.
Bit1:Bit0 : See 2.1.3 for detail description.
2.1.10 PDCON (Pull-down Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Bh (r/w)
PDCON
/PDB3
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
/PDA0 : = 1, Disable the internal pull-down of IOA0 pin.
= 0, Enable the internal pull-down of IOA0 pin.
/PDA1 : = 1, Disable the internal pull-down of IOA1 pin.
= 0, Enable the internal pull-down of IOA1 pin.
/PDA2 : = 1, Disable the internal pull-down of IOA2 pin.
= 0, Enable the internal pull-down of IOA2 pin.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.11/FM8PB56B
EELING
FM8PB56B
/PDA3 : = 1, Disable the internal pull-down of IOA3 pin.
= 0, Enable the internal pull-down of IOA3 pin.
/PDB0 : = 1, Disable the internal pull-down of IOB0 pin.
= 0, Enable the internal pull-down of IOB0 pin.
/PDB1 : = 1, Disable the internal pull-down of IOB1 pin.
= 0, Enable the internal pull-down of IOB1 pin.
/PDB2 : = 1, Disable the internal pull-down of IOB2 pin.
= 0, Enable the internal pull-down of IOB2 pin.
/PDB3 : = 1, Disable the internal pull-down of IOB3 pin.
= 0, Enable the internal pull-down of IOB3 pin.
2.1.11 ODCON (Open-drain Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
ODB0 : = 1, Enable the internal open-drain of IOB0 pin.
= 0, Disable the internal open-drain of IOB0 pin.
ODB1 : = 1, Enable the internal open-drain of IOB1 pin.
= 0, Disable the internal open-drain of IOB1 pin.
ODB2 : = 1, Enable the internal open-drain of IOB2 pin.
= 0, Disable the internal open-drain of IOB2 pin.
ODB3 : = 1, Enable the internal open-drain of IOB3 pin.
= 0, Disable the internal open-drain of IOB3 pin.
ODB4 : = 1, Enable the internal open-drain of IOB4 pin.
= 0, Disable the internal open-drain of IOB4 pin.
ODB5 : = 1, Enable the internal open-drain of IOB5 pin.
= 0, Disable the internal open-drain of IOB5 pin.
ODB6 : = 1, Enable the internal open-drain of IOB6 pin.
= 0, Disable the internal open-drain of IOB6 pin.
ODB7 : = 1, Enable the internal open-drain of IOB7 pin.
= 0, Disable the internal open-drain of IOB7 pin.
2.1.12 PHCON (Pull-high Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
/PHB4
/PHB3
/PHB2
/PHB1
/PHB0
/PHB0 : = 1, Disable the internal pull-high of IOB0 pin.
= 0, Enable the internal pull-high of IOB0 pin.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.12/FM8PB56B
EELING
FM8PB56B
/PHB1 : = 1, Disable the internal pull-high of IOB1 pin.
= 0, Enable the internal pull-high of IOB1 pin.
/PHB2 : = 1, Disable the internal pull-high of IOB2 pin.
= 0, Enable the internal pull-high of IOB2 pin.
/PHB3 : = 1, Disable the internal pull-high of IOB3 pin.
= 0, Enable the internal pull-high of IOB3 pin.
/PHB4 : = 1, Disable the internal pull-high of IOB4 pin.
= 0, Enable the internal pull-high of IOB4 pin.
/PHB5 : = 1, Disable the internal pull-high of IOB5 pin.
= 0, Enable the internal pull-high of IOB5 pin.
/PHB6 : = 1, Disable the internal pull-high of IOB6 pin.
= 0, Enable the internal pull-high of IOB6 pin.
/PHB7 : = 1, Disable the internal pull-high of IOB7 pin.
= 0, Enable the internal pull-high of IOB7 pin.
2.1.13 INTEN (Interrupt Mask Register)
Address
Name
B7
B6
-
B5
-
B4
-
B3
-
B2
B1
B0
0Eh (r/w)
INTEN
GIE
INTIE
PBIE
T0IE
Legend: - = unimplemented, read as ‘0’.
T0IE : Timer0 overflow interrupt enable bit.
= 1, Enable the Timer0 overflow interrupt.
= 0, Disable the Timer0 overflow interrupt.
PBIE : Port B input change interrupt enable bit.
= 1, Enable the Port B input change interrupt.
= 0, Disable the Port B input change interrupt.
INTIE : External INT pin interrupt enable bit.
= 1, Enable the External INT pin interrupt.
= 0, Disable the External INT pin interrupt.
GIE : Global interrupt enable bit.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (008h).
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will
continue execution at the instruction after the SLEEP instruction.
Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set,
the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will
exit the interrupt routine and set the GIE bit to re-enable interrupt.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.13/FM8PB56B
EELING
FM8PB56B
2.1.14 INTFLAG (Interrupt Status Register)
Address
0Fh (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
B1
B0
INTFLAG
INTIF
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’.
T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.
PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software.
INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT
pin, reset by software.
2.1.15 ACC (Accumulator)
Address
N/A (r/w)
Name
ACC
B7
B6
B5
B4
B3
B2
B1
B0
Accumulator
Accumulator is an internal data transfer, or instruction operand holding. It cannot be addressed.
2.1.16 OPTION Register
Address
N/A (w)
Name
B7
-
B6
B5
B4
B3
B2
B1
B0
OPTION
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Accessed by OPTION instruction.
Legend: - = Not used.
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION
Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0 : Prescaler rate select bits.
PS2:PS0
Timer0 Rate
WDT Rate
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
PSA : Prescaler assign bit.
= 1, WDT (watch-dog timer).
= 0, TMR0 (Timer0).
T0SE : TMR0 source edge select bit.
= 1, Falling edge on T0CKI pin.
= 0, Rising edge on T0CKI pin.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.14/FM8PB56B
EELING
FM8PB56B
T0CS : TMR0 clock source select bit.
= 1, External IOA4/T0CKI pin.
= 0, internal instruction clock cycle.
INTEDG : Interrupt edge select bit.
= 1, interrupt on rising edge of INT pin.
= 0, interrupt on falling edge of INT pin.
2.1.17 IOSTA & IOSTB (Port I/O Control Registers)
Address
N/A (w)
N/A (w)
Name
IOSTA
IOSTB
B7
B6
B5
B4
B3
B2
B1
B0
IOSTA7 IOSTA6 IOSTA5 IOSTA4 IOSTA3 IOSTA2 IOSTA1 IOSTA0
IOSTB7 IOSTB6 IOSTB5 IOSTB4 IOSTB3 IOSTB2 IOSTB1 IOSTB0
Accessed by IOST instruction.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R
(05h~06h) instruction.
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
IOSTA7:IOSTA0 : PORTA I/O control bit.
= 1, PORTA pin configured as an input (tri-stated).
= 0, PORTA pin configured as an output.
Note: 1. IOA5 is open-drain output only if IOSTA5 = 0.
2. The IOA5 open-drain function will be fixed to “Disable” by H/W if the
configuration bit IOA5OD= Disable, even if bit IOSTA5 = 0.
IOSTB7:IOSTB0 : PORTB I/O control bit.
= 1, PORTB pin configured as an input (tri-stated).
= 0, PORTB pin configured as an output.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.15/FM8PB56B
EELING
FM8PB56B
2.2 I/O Ports
Port A and port B are bi-directional tri-state I/O ports. Port A and Port B are 8-pin I/O ports. Please note that IOA5
is an input or open-drain output pin.
All I/O pins (IOA<7:0> and IOB<7:0>) have data direction control registers (IOSTA, IOSTB) which can configure
these pins as output or input.
IOB<7:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high.
The weak pull-high is automatically turned off when the pin is configured as an output pin.
IOA<3:0> and IOB<3:0> have its corresponding pull-down control bits (PDCON register) to enable the weak
internal pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.
IOB<7:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when
these pins are configured to be an output pin.
IOA0 and IOA1 are the R-option pins enabled by setting the ROC bit (PCON<4>). When the R-option function is
used, it is recommended that IOA0 and IOA1 are used as output pins, and read the status of IOA0 and IOA1
before these pins are configured to be an output pin.
IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change
interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source.
The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input
change interrupt/wake-up function will be disabled by hardware even if it is enabled by software.
Please note, IOA5 voltage on this pin must not exceed VDD, otherwise it will cause the pin breakdown!!
Figure 2.3: Block Diagram of I/O Pins
IOA7, IOA6, IOA4 ~ IOA0:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
Pull-down is not shown in the figure
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.16/FM8PB56B
EELING
FM8PB56B
IOA5:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
RSTBIN
Internal
Reset
Voltage on this pin must not exceed VDD.
IOB0/INT:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
EN
Q
D
RD PORT
Set PBIF
Q
Q
Latch
WUB0
EIS
EN
INT
INTEDG
EIS
Pull-high/pull-down and open-drain are not shown in the figure
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.17/FM8PB56B
EELING
FM8PB56B
IOB7 ~ IOB1:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
Q
Q
Set PBIF
WUBn
Latch
EN
Pull-high/pull-down and open-drain are not shown in the figure
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.18/FM8PB56B
EELING
FM8PB56B
2.3 Timer0/WDT & Prescler
2.3.1
Timer0
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external
clock source (T0CKI pin).
2.3.1.1 Using Timer0 with an Internal Clock: Timer mode
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will
increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the
following two cycles.
2.3.1.2 Using Timer0 with an External Clock: Counter mode
Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on
every rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit
T0SE (OPTION<4>).
The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the
actual incrementing of Timer0 after synchronization.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of
T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of
the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2
TOSC
.
When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external
clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary
for T0CKI to have a period of at least 4Tosc divided by the prescaler value.
2.3.2
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external
components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in
SLEEP mode. During normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the
bit (STATUS<4>) will be cleared.
TO
The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”.
The WDT has a nominal time-out period of 18 ms (without prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register.
Thus, the longest time-out period is approxmately 2.3 seconds.
The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing
out and generating a device reset.
The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum
SLEEP time before a WDT Wake-up Reset.
2.3.3
Prescaler
An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog
Timer (WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus,
a prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa.
The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine
prescaler ratio.
When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the
prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.
The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s.
To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the
prescaler assignment from Timer0 to the WDT, and vice-versa.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.19/FM8PB56B
EELING
FM8PB56B
Figure 2.4: Block Diagram of the Timer0/WDT Prescaler
Instruction Cycle
(Fosc/2, Fosc/4, Fosc/8)
8
0
1
Data Bus
Sync
TMR0
T0SE
2 Cycles
Register
Set T0IF flag
on overflow
1
0
T0CKI (IOA4)
T0CS
PSA
0
1
8-Bit
WDT Time-out
Prescaler
1
0
Watchdog
Timer
PSA
PSA
PS2:PS0
2.4 Interrupts
The FM8PB56B has up to three sources of interrupt:
1. External interrupt INT pin.
2. TMR0 overflow interrupt.
3. Port B input change interrupt (pins IOB7:IOB0).
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit
will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address
008h. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.
2.4.1
External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled
by clearing INTIE bit (INTEN<2>).
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP.
If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.4.2
Timer0 Interrupt
An overflow (FFh 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
disabled by clearing T0IE bit (INTEN<0>).
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.20/FM8PB56B
EELING
FM8PB56B
2.4.3
Port B Input Change Interrupt
An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit
(INTEN<1>).
Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB,
including read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared
to “0” or configured as output or IOB0 pin configured as INT pin will be excluded from this function.
The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before
going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following
wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was
cleared, the program will execute next PC after wake-up.
2.5 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
̅̅̅̅
̅̅̅̅
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer
will be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.5.1
Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1. RSTB reset.
2. WDT time-out reset (if enabled).
3. Interrupt from IOB0/INT pin, or PORTB change interrupt.
External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to
̅̅̅̅
̅̅̅̅
̅̅̅̅
determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is
̅̅̅̅
executed. The TO bit is cleared if a WDT time-out occurred.
For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up
is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the
SLEEP instruction. If the GIE bit is set, the device will branch to the interrupt address (008h).
The system wake-up delay time is 18ms plus 128 oscillator cycle time.
2.6 Reset
FM8PB56B devices may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or
WDT Reset.
A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely
ties the RSTB pin to Vdd.
On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
̅̅̅̅
̅̅̅̅
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.21/FM8PB56B
EELING
FM8PB56B
2.6.1
Power-up Reset Timer (PWRT)
The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR),
RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.
The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.
2.6.2
Oscillator Start-up Timer (OST)
The OST timer provides a 128 oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This
delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as
long as the OST is active.
This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input
thresholds.
2.6.3
Reset Sequence
When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the
reset sequence is as follows:
1. The reset latch is set and the PWRT & OST are cleared.
2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins
counting.
3. After the PWRT time-out, the OST is activated.
4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.
The totally system reset delay time is 18ms plus 128 oscillator cycle time.
Figure 2.5: Simplified Block Diagram of on-chip Reset Circuit
WDT
Time-out
WDT
Module
RSTB
Vdd
S
R
Q
Q
Reset
Latch
Low Voltage
Detector
(LVD)
BOR
CHIP RESET
Power-on
Reset
POR
(POR)
RESET
RESET
On-Chip
RC OSC
Power-up
Reset Timer
(PWRT)
Oscillator
Start-up Timer
(OST)
OSCI
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.22/FM8PB56B
EELING
FM8PB56B
Table 2.1: Reset Conditions for All Registers
Power-on Reset
Brown-out Reset
RSTB Reset
WDT Reset
Register
Address
ACC
OPTION
N/A
N/A
xxxx xxxx
-011 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
11xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1010 ----
0000 0000
---- --00
1111 1111
0000 0000
1111 1111
0--- -000
---- -000
xxxx xxxx
uuuu uuuu
-011 1111
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
000# #uuu
11uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1010 ----
0000 0000
---- --00
1111 1111
0000 0000
1111 1111
0--- -000
---- -000
uuuu uuuu
IOSTA
N/A
IOSTB
N/A
INDF
00h
TMR0
01h
PCL
02h
STATUS
03h
FSR
04h
PORTA
05h
PORTB
06h
General Purpose Register
PCON
07h
08h
WUCON
PCHBUF
PDCON
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10 ~ 3Fh
ODCON
PHCON
INTEN
INTFLAG
General Purpose Registers
Legend: u = unchanged, x = unknown, - = unimplemented,
# = refer to the following table for possible values.
̅̅̅̅ ̅̅̅̅
Table 2.2: TO / PD Status after Reset or Wake-up
̅̅̅̅
̅̅̅̅
PD RESET was caused by
TO
1
1
u
1
0
0
1
1
u
0
1
0
Power-on Reset
Brown-out reset
RSTB Reset during normal operation
RSTB Reset during SLEEP
WDT Reset during normal operation
WDT Reset during SLEEP
Legend: u = unchanged
̅̅̅̅ ̅̅̅̅
Table 2.3: Events AffectingTO / PDStatus Bits
̅̅̅̅
̅̅̅̅
PD
Event
TO
Power-on
1
0
1
1
1
u
0
1
WDT Time-Out
SLEEP instruction
CLRWDT instruction
Legend: u = unchanged
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.23/FM8PB56B
EELING
FM8PB56B
2.7 Hexadecimal Convert to Decimal (HCD)
Decimal format is another number format for FM8PB56B. When the content of the data memory has been
assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU
instructions. When the decimal converting operation is processing, all of the operand data (including the contents
of the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal
format, or the results of conversion will be incorrect.
Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
The conversion operation is illustrated in example 2.2.
Example 2.2: DAA CONVERSION
Address Code
NA
n
#include
<8PB56B.ASH>
…
n+1
n+2
n+3
n+4
MOVIA
MOVAR
MOVIA
ADDAR
0x90
;Set immediate data = decimal format number “90” (ACC 90h)
;Load immediate data “90” to data memory address 30H
;Set immediate data = decimal format number “10” (ACC 10h)
;Contents of the data memory address 30H and ACC are binary-added
;the result loads to the ACC (ACC A0h, C 0)
0x30
0x10
0x30,A
n+5
n+6
DAA
…
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “00” and the carry bit C is “1”. This represents the
;decimal number “100”
Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
The conversion operation is illustrated in example 2.3.
Example 2.3: DAS CONVERSION
Address Code
NA
n
#include
<8PB56B.ASH>
…
n+1
n+2
n+3
n+4
MOVIA
MOVAR
MOVIA
SUBAR
0x10
;Set immediate data = decimal format number “10” (ACC 10h)
;Load immediate data “90” to data memory address 30H
;Set immediate data = decimal format number “20” (ACC 20h)
;Contents of the data memory address 30H and ACC are binary-subtracted
;the result loads to the ACC (ACC F0h, C 0)
0x30
0x20
0x30,A
n+5
n+6
DAS
…
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “90” and the carry bit C is “0”. This represents the
;decimal number “ -10”
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.24/FM8PB56B
EELING
FM8PB56B
2.8 Oscillator Configurations
FM8PB56B can be operated in six different oscillator modes. Users can program FOSC configuration bit to select
the appropriate modes:
ERC: External Resistor/Capacitor Oscillator
HF: High Frequency Crystal/Resonator Oscillator
XT: Crystal/Resonator Oscillator
LF: Low Frequency Crystal Oscillator
IRC: Internal Resistor/Capacitor Oscillator
ERIC: External Resistor/Internal Capacitor Oscillator
In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish
oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.
The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator
frequency is a function of the resistor (Rext) and capacitor (Cext), the operating temperature, and the process
parameter.
The IRC/ERIC device option offers largest cost savings for timing insensitive applications. These devices offer 4
different internal RC oscillator frequency, 8 MHz, 4 MHz, 1 MHz, and 455 KHz, which is selected by FOSC
configuration bit. Or user can change the oscillator frequency with external resistor. The ERIC oscillator frequency
is a function of the resistor (Rext), the operating temperature, and the process parameter.
Figure 2.6: HF, XT or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)
FM8PB56B
C1
OSCI
SLEEP
X`TAL
RS
R1
RF
OSCO
C2
Internal
Circuit
Figure 2.7: HF, XT or LF Oscillator Modes (External Clock Input Operation)
FM8PB56B
OSCI
Clock from
External System
OSCO
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.25/FM8PB56B
EELING
FM8PB56B
Figure 2.8: ERC Oscillator Mode (External RC Oscillator)
FM8PB56B
Rext
OSCI
Internal
Circuit
Cext
/2, /4, /8
OSCO
Figure 2.9: ERIC Oscillator Mode (External R, Internal C Oscillator)
FM8PB56B
Rext
OSCI
Internal
Circuit
Cext
(300pF~0.1uF)
C
/2, /4, /8
OSCO
The typical oscillator frequency vs. external resistor is as following table
Frequency
455KHz
1MHz
Rext @ 3V
926.8K
612.3K
217.2K
118.2K
57.2K
Rext @ 5V
1301.6K
774K
4MHz
244.6K
123.9K
61.8K
8MHz
16MHz
Note: Values are provided for design reference only.
Figure 2.10: IRC Oscillator Mode (Internal R, Internal C Oscillator)
FM8PB56B
OSCI
C
Internal
Circuit
/2, /4, /8
OSCO
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.26/FM8PB56B
EELING
FM8PB56B
2.9 Configuration Words
Table 2.4: Configuration Words
Name
Description
Oscillator Selection Bit
ERC mode (external R & C) (default)
HF mode
XT mode
LF mode
Fosc
4 MHz IRC mode
8 MHz IRC mode
1 MHz IRC mode
455 KHz IRC mode
ERIC mode (external R & internal C)
Note: See Table 2.5 for detail description.
Low Voltage Detector Selection Bit
enable, LVDT voltage = 3.6V
enable, LVDT voltage = 2.2V
enable, LVDT voltage = 2.4V
enable, LVDT voltage = 2.6V
enable, LVDT voltage = 2.0V**
enable, LVDT voltage = 1.8V**
LVDT
Note:LVDT 2.0V only for LF and IRC 4 MHz, 1 MHz, 455 KHz
LVDT 1.8V only for LF and IRC 1 MHz, 455 KHz
PWRT Time Period Selection Bit
PWRT = 18ms (default)
PWRT
PWRT = 4.5ms
PWRT = 288ms
PWRT = 72ms
IOA6/OSCO Pin Selection Bit for IRC/ERIC/ERC Mode
OSCO pin is selected (default)
IOA6 pin is selected
OSCOUT
RSTBIN
WDTEN
IOA5/RSTB Pin Selection Bit
IOA5 pin is selected (default)
RSTB pin is selected
Watchdog Timer Enable Bit
WDT enabled (default)
WDT disabled
Code Protection Bit
PROTECT OTP code protection off (default)
OTP code protection on
Instruction Period Selection Bit
four oscillator periods (default)
two oscillator periods
OSCD
eight oscillator periods
Power Mode Selection Bit
PMOD
Non-power saving (default)
Power saving
Read Port Control Bit for Output Pins
From registers (default)
From pins
RDPORT
I/O Pin Input Buffer Control Bit
SCHMITT With Schmitt-trigger (default)
Without Schmitt-trigger
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.27/FM8PB56B
EELING
FM8PB56B
Name
Description
Wake-up & Subsequent-Resets Timer for ERC/IRC/ERIC modes
140us (default)
RCT
18ms
IOA4/T0CKI Pin Selection Bit
T0CKIN
IOA5OD
T0CKI pin is selected (default)
Both T0CKI & IOA4 pin is selected
IOA5 Pin Open-Drain Output Enable Bit
Enable open-drain function (IOA5 pin is Bi-direction) (default)
Disable open-drain function (IOA5 pin is Only input)
Table 2.5: Selection of IOA7/OSCI and IOA6/OSCO Pins
Mode of oscillation
IRC
IOA7/OSCI
Force to IOA7
Force to OSCI
Force to OSCI
IOA6/OSCO
IOA6/OSCO selected by OSCOUT bit
IOA6/OSCO selected by OSCOUT bit
Force to OSCO
ERC, ERIC
HF, XT, LF
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.28/FM8PB56B
EELING
FM8PB56B
3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Affected
Description
Operation
Cycles
BCR
R, bit Clear bit in R
R, bit Set bit in R
0 R<b>
1
1
1/2(1)
1/2(1)
1
-
-
-
-
-
BSR
1 R<b>
BTRSC
BTRSS
NOP
R, bit Test bit in R, Skip if Clear
R, bit Test bit in R, Skip if Set
No Operation
Skip if R<b> = 0
Skip if R<b> = 1
No operation
00h WDT,
00h WDT prescaler
00h WDT,
̅̅̅̅ ̅̅̅̅
CLRWDT
Clear Watchdog Timer
1
TO,PD
̅̅̅̅ ̅̅̅̅
SLEEP
OPTION
DAA
Go into power-down mode
Load OPTION register
1
1
1
TO,PD
00h WDT prescaler
ACC OPTION
-
Adjust ACC’s data format from HEX to
DEC after any addition operation
ACC(hex) ACC (dec)
C
Adjust ACC’s data format from HEX to
DEC after any subtraction operation
DAS
ACC(hex) ACC (dec)
Top of Stack PC
1
2
2
C
-
RETURN
RETFIE
Return from subroutine
Top of Stack PC,
1 GIE
Return from interrupt, set GIE bit
-
PC + 1 Top of Stack
002h PC
INT
S/W interrupt
2
-
IOST
R
Load IOST register
Clear ACC
ACC IOST register
00h ACC
00h R
1
1
1
1
1
1
-
CLRA
CLRR
MOVAR
MOVR
DECR
Z
Z
-
R
R
Clear R
Move ACC to R
ACC R
R, d Move R
R dest
Z
Z
R, d Decrement R
R - 1 dest
R - 1 dest,
Skip if result = 0
DECRSZ
INCR
R, d Decrement R, Skip if 0
R, d Increment R
1/2(1)
1
-
Z
-
R + 1 dest
R + 1 dest,
Skip if result = 0
INCRSZ
R, d Increment R, Skip if 0
1/2(1)
ADDAR
SUBAR
ADCAR
SBCAR
ANDAR
IORAR
XORAR
COMR
R, d Add ACC and R
R + ACC dest
R - ACC dest
1
1
1
1
1
1
1
1
C, DC, Z
R, d Subtract ACC from R
R, d Add ACC and R with Carry
R, d Subtract ACC from R with Carry
R, d AND ACC with R
C, DC, Z
R + ACC + C dest
C, DC, Z
̅̅̅̅̅̅̅
R + ACC + C dest
C, DC, Z
ACC and R dest
ACC or R dest
R xor ACC dest
Z
Z
Z
Z
R, d Inclusive OR ACC with R
R, d Exclusive OR ACC with R
R, d Complement R
ꢀ
R dest
R<7> C,
RLR
R, d Rotate left R through Carry
R<6:0> dest<7:1>,
C dest<0>
1
C
C dest<7>,
RRR
R, d Rotate right R through Carry
R, d Swap R
R<7:1> dest<6:0>,
R<0> C
1
1
C
-
R<3:0> dest<7:4>,
R<7:4> dest<3:0>
SWAPR
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.29/FM8PB56B
EELING
FM8PB56B
Mnemonic,
Status
Description
Operation
Cycles
Operands
Affected
MOVIA
I
I
I
I
I
I
Move Immediate to ACC
I ACC
1
1
1
1
1
1
-
ADDIA
SUBIA
ANDIA
IORIA
Add ACC and Immediate
Subtract ACC from Immediate
AND Immediate with ACC
OR Immediate with ACC
I + ACC ACC
I - ACC ACC
ACC and I ACC
ACC or I ACC
ACC xor I ACC
C, DC, Z
C, DC, Z
Z
Z
Z
XORIA
Exclusive OR Immediate to ACC
I ACC,
RETIA
I
Return, place Immediate in ACC
2
-
Top of Stack PC
PC + 1 Top of Stack,
I PC
CALL
I
I
Call subroutine
2
2
-
-
GOTO
Unconditional branch
I PC
Note: 1. 2 cycles for skip, else 1 cycle.
2. bit :Bit address within an 8-bit register R
R :Register address (00h to 3Fh)
I :Immediate data
ACC :Accumulator
d :Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest :Destination
PC :Program Counter
PCH :High Byte register of Program Counter
WDT :Watchdog Timer Counter
GIE :Global interrupt enable bit
̅̅̅̅
TO :Time-out bit
̅̅̅̅
PD :Power-down bit
C :Carry bit
DC :Digital carry bit
Z :Zero bit
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.30/FM8PB56B
EELING
FM8PB56B
ADCAR
Add ACC and R with Carry
Syntax:
ADCAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDAR
Syntax:
Add ACC and R
ADDAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
ACC + R dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the
ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDIA
Add ACC and Immediate
Syntax:
ADDIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC + I ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
ACC and R dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC AND I ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.31/FM8PB56B
EELING
FM8PB56B
BCR
Clear Bit in R
Syntax:
BCR R, b
Operands:
0
0
R
b
0x3F
7
Operation:
Status Affected:
Description:
Cycles:
0 R<b>
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
Syntax:
Operands:
BSR R, b
0
0
R
b
0x3F
7
Operation:
Status Affected:
Description:
Cycles:
1 R<b>
None
Set bit ‘b’ in register ‘R’.
1
BTRSC
Test Bit in R, Skip if Clear
Syntax:
BTRSC R, b
Operands:
0
0
R
b
0x3F
7
Operation:
Skip if R<b> = 0
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is
discarded, and a NOP is executed instead making this a 2-cycle instruction.
1/2
Cycles:
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0
0
R
b
0x3F
7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1/2
Cycles:
CALL
Subroutine Call
Syntax:
CALL I
Operands:
Operation:
0
I
0x3FF
PC +1 Top of Stack;
I PC
Status Affected:
Description:
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit
immediate address is loaded into PC bits <9:0>. CALL is a two-cycle instruction.
2
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.32/FM8PB56B
EELING
FM8PB56B
CLRA
Clear ACC
Syntax:
CLRA
Operands:
Operation:
None
00h ACC;
1 Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
Syntax:
CLRR R
Operands:
Operation:
0
R
0x3F
00h R;
1 Z
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Clear Watchdog Timer
CLRWDT
Operands:
Operation:
None
00h WDT;
00h WDT prescaler (if assigned);
̅̅̅̅
1 TO;
̅̅̅̅
1 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO,PD
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
̅̅̅̅
̅̅̅̅
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Cycles:
COMR
Complement R
Syntax:
COMR R, d
Operands:
0
d
R
[0,1]
0x3F
ꢀ
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
DAA
Adjust ACC’s data format from HEX to DEC
Syntax:
DAA
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.33/FM8PB56B
EELING
FM8PB56B
DAS
Adjust ACC’s data format from HEX to DEC
Syntax:
DAS
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
1
Cycles:
DECR
Decrement R
Syntax:
Operands:
DECR R, d
0
d
R
[0,1]
0x3F
Operation:
R - 1 dest
Status Affected:
Description:
Z
Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the
result is stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R - 1 dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead and making it a two-cycle instruction.
1/2
Cycles:
GOTO
Unconditional Branch
Syntax:
GOTO I
Operands:
Operation:
Status Affected:
Description:
0
I
0x3FF
I PC
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
GOTO is a two-cycle instruction.
2
Cycles:
INCR
Increment R
Syntax:
Operands:
INCR R, d
0
d
R
[0,1]
0x3F
Operation:
R + 1 dest
Status Affected:
Description:
Z
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.34/FM8PB56B
EELING
FM8PB56B
INCRSZ
Increment R, Skip if 0
Syntax:
INCRSZ R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R + 1 dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is stored back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP
is executed instead and making it a two-cycle instruction.
1/2
Cycles:
INT
S/W Interrupt
Syntax:
Operands:
Operation:
INT
None
PC + 1 Top of Stack,
002h PC
Status Affected:
Description:
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The
address 002h is loaded into PC bits <10:0>.
2
Cycles:
IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
ACC or R dest
Status Affected:
Description:
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC or I ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
IOST
Load IOST Register
Syntax:
IOST R
Operands:
Operation:
Status Affected:
Description:
Cycles:
R = 0x05 or 0x06
ACC IOST register R
None
IOST register ‘R’ (R= 0x05 or 0x06) is loaded with the contents of the ACC register.
1
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.35/FM8PB56B
EELING
FM8PB56B
MOVAR
Move ACC to R
Syntax:
MOVAR R
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
R
0x3F
ACC R
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Move Immediate to ACC
Syntax:
MOVIA I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0
I
0xFF
I ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register
since status flag Z is affected.
1
Cycles:
NOP
No Operation
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
OPTION
Load OPTION Register
Syntax:
OPTION
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
ACC OPTION
None
The content of the ACC register is loaded into the OPTION register.
1
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
None
Top of Stack PC
1 GIE
Status Affected:
Description:
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit
is set to 1. This is a two-cycle instruction.
2
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.36/FM8PB56B
EELING
FM8PB56B
RETIA
Return with Immediate in ACC
Syntax:
RETIA I
Operands:
Operation:
0
I
0xFF
I ACC;
Top of Stack PC
None
Status Affected:
Description:
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a two-cycle instruction.
2
Cycles:
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack PC
None
The program counter is loaded from the top of the stack (the return address). This is a two-
cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0
d
R
[0,1]
0x3F
Operation:
R<7> C;
R<6:0> dest<7:1>;
C dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is
0 the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
RRR
Rotate Right R through Carry
Syntax:
Operands:
RRR R, d
0
d
R
[0,1]
0x3F
Operation:
C dest<7>;
R<7:1> dest<6:0>;
R<0> C
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.37/FM8PB56B
EELING
FM8PB56B
SLEEP
Enter SLEEP Mode
Syntax:
SLEEP
Operands:
Operation:
None
00h WDT;
00h WDT prescaler;
̅̅̅̅
1 TO;
̅̅̅̅
0 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
̅̅̅̅
̅̅̅̅
Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT and its
prescaler cleared.
The processor is put into SLEEP mode.
1
Cycles:
SBCAR
Syntax:
Subtract ACC from R with Carry
SBCAR R, d
Operands:
0
d
R
[0,1]
̅̅̅̅̅̅̅
0x3F
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBAR
Syntax:
Subtract ACC from R
SUBAR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R - ACC dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBIA
Subtract ACC from Immediate
Syntax:
SUBIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
I - ACC ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result
is placed in the ACC register.
1
Cycles:
SWAPR
Syntax:
Swap nibbles in R
SWAPR R, d
Operands:
0
d
R
[0,1]
0x3F
Operation:
R<3:0> dest<7:4>;
R<7:4> dest<3:0>
Status Affected:
Description:
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.38/FM8PB56B
EELING
FM8PB56B
XORAR
Exclusive OR ACC with R
Syntax:
XORAR R, d
Operands:
0
R
0x3F
d[0,1]
Operation:
ACC xor R dest
Status Affected:
Description:
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0
I
0xFF
ACC xor I ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.39/FM8PB56B
EELING
FM8PB56B
4.0 ABSOLUTE MAXIMUM RATINGS
Ambient Operating Temperature
Store Temperature
0℃ to +70℃
-65℃ to +150℃
0V to +6.0V
DC Supply Voltage (Vdd)
Input Voltage with respect to Ground (Vss)
-0.3V to (Vdd + 0.3)V
5.0 OPERATING CONDITIONS
DC Supply Voltage
+2.0V to +5.5V*
Operating Temperature
*: See 6.1 for detail description.
0℃ to +70℃
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.40/FM8PB56B
EELING
FM8PB56B
6.0 ELECTRICAL CHARACTERISTICS
6.1 ELECTRICAL CHARACTERISTICS of FM8PB56B
Ta=25℃
Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled
Sym
Description
Conditions
Min.
Typ.
2.0
2.0
2.2
2.4
2.8
3.0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
2.6
20
Unit
V
0Hz ~ 1MHz
1MHz ~ 4MHz
4MHz ~ 8MHz
VDD
Supply voltage
8MHz ~ 10MHz
10MHz ~ 16MHz
16MHz ~ 20MHz
TPWR Power rising time
Vdd=0V to Vdd
0.8
4
ms/V
MHz
HF mode, Vdd=5V
FHF
FXT
FLF
X’tal oscillation range
X’tal oscillation range
X’tal oscillation range
HF mode, Vdd=3V
4
16
XT mode, Vdd=5V
0.455
0.455
32
20
MHz
KHz
MHz
MHz
MHz
XT mode, Vdd=3V
16
LF mode, Vdd=5V
455
455
16
LF mode, Vdd=3V
32
ERC mode, Vdd=5V
DC
FERC RC oscillation range
FERIC RC oscillation range
ERC mode, Vdd=3V
DC
13
ERIC mode, external R, Vdd=5V
ERIC mode, external R, Vdd=3V
IRC mode, internal R, Vdd=5V
IRC mode, internal R, Vdd=3V
With Schmitter
DC
16
DC
16
0.455
0.455
8
FIRC
RC oscillation range
8
I/O ports (except IOA4, IOA5), Vdd=5V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=3V
Without Schmitter
2.2
4.0
1.7
2.4
VIH
Input high voltage
V
I/O ports (except IOA4, IOA5), Vdd=5V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=3V
With Schmitter
2.0
4.0
1.5
2.4
I/O ports (except IOA4, IOA5), Vdd=5V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=3V
Without Schmitter
0.8
1.0
0.5
0.6
VIL
Input low voltage
V
I/O ports (except IOA4, IOA5), Vdd=5V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA5/RSTB, IOA4/T0CKI pins, Vdd=3V
1.0
1.0
0.6
0.6
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.41/FM8PB56B
EELING
FM8PB56B
Sym
VOH
VOL
IPH
Description
Output high voltage
Output low voltage
Pull-high current
Pull-down current
Conditions
Min.
3.6
Typ.
Max.
Unit
V
IOH=-5.4mA, Vdd=5V
IOL=8.7mA, Vdd=5V
Input pin at Vss, Vdd=5V
Input pin at Vdd, Vdd=5V
Vdd=5V
0.6
70
55
8
V
40
25
55
40
uA
uA
IPD
5
IWDT
WDT current
uA
Vdd=3V
1
2
Vdd=3V
19.28
16.79
15.24
3
TWDT WDT period
Vdd=4V
mS
Vdd=5V
Vdd=5V LVDT = 3.6V
Vdd=5V LVDT = 2.4V
Vdd=3V LVDT = 2.4V
ILVDT
LVDT current
3.3
1.5
uA
uA
Sleep mode, Vdd=5V, WDT LVDT
disable
0.2
0.1
0.5
0.3
ISB
Power down current
Sleep mode, Vdd=3V, WDT LVDT
disable
HF mode, Vdd=5V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
20MHz
16MHz
4.55
3.84
IDD
Operating current
mA
HF mode, Vdd=3V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
16MHz
8MHz
-
0.92
XT mode, Vdd=5V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
20MHz
16MHz
8MHz
3.36
2.76
1.65
0.98
1.01
IDD
Operating current
Operating current
mA
mA
4MHz
455KHz
XT mode, Vdd=3V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
16MHz
8MHz
-
IDD
0.69
0.42
0.14
4MHz
455KHz
LF mode, Vdd=5V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
455KHz
32KHz
137.7
44.1
IDD
Operating current
Operating current
uA
LF mode, Vdd=3V, 2 clock instruction, OSCI / OSCO =20pF / 20pF
455KHz
53
32KHz
13.2
ERC mode, Vdd=5V, 2 clock instruction
IDD
R=10Kohm
R=33Kohm
F=7.29
F=2.53
1.84
0.64
mA
C=3P
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.42/FM8PB56B
EELING
FM8PB56B
Sym
IDD
Description
Conditions
Min.
Typ.
Max.
Unit
ERC mode, Vdd=3V, 2 clock instruction
Operating current
R=10Kohm
R=33Kohm
F=6.5
0.86
0.35
mA
C=3P
F=2.66
ERIC mode, external R, Vdd=5V, 2 clock instruction
IDD
Operating current
Operating current
F=8MHz
F=4MHz
R=123.9K
R=244.6K
1.92
0.94
mA
mA
ERIC mode, external R, Vdd=3V, 2 clock instruction
IDD
F=8MHz
F=4MHz
R=118.2K
R=217.2K
0.97
0.51
IRC mode, internal R, Vdd=5V, 2 clock instruction
F=8MHz
1.99
1.07
0.35
0.22
F=4MHz
F=1MHz
F=455KHz
IDD
Operating current
mA
IRC mode, internal R, Vdd=3V, 2 clock instruction
F=8MHz
F=4MHz
F=1MHz
F=455KHz
1.18
0.64
0.23
0.16
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.43/FM8PB56B
EELING
FM8PB56B
6.2 ELECTRICAL CHARACTERISTICS Typical charts of FM8PB53B
6.2.1
Operator Frequency vs. Operator voltage (Ta=25℃)
20MHz
16MHz
8MHz
4MHz
1MHz
455KHz
32KHz
Near 0Hz
2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V
6.2.2
Internal 4MHz RC vs. Temperature
3.00%
2.00%
1.00%
0.00%
Avg-5V
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-1.00%
-2.00%
-3.00%
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.44/FM8PB56B
EELING
FM8PB56B
6.2.3
Internal 8MHz RC vs. Temperature
3.00%
2.00%
1.00%
0.00%
Avg-5V
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-1.00%
-2.00%
-3.00%
Temperature
Note: Curves are for design reference only.
6.2.4
Internal 1MHz RC vs. Temperature
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
Avg-5V
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
Temperature
Note: Curves are for design reference only.
6.2.5
Internal 455KHz RC vs. Temperature
4.00%
3.00%
2.00%
1.00%
0.00%
Avg-5V
Avg-3V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.45/FM8PB56B
EELING
FM8PB56B
6.2.6
Internal 4 MHz RC vs. Supply Voltage (Ta=25℃)
3.00%
4M HV
4M LV
2.00%
1.00%
0.00%
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4
4
4.2 4.4 4.6 4.8
4.2 4.4 4.6 4.8
4.2 4.4 4.6 4.8
5
5
5
5.2 5.4 5.6 5.8
6
6
6
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
6.2.7
Internal 8 MHz RC vs. Supply Voltage (Ta=25℃)
3.00%
8M HV
8M LV
2.00%
1.00%
0.00%
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
5.2 5.4 5.6 5.8
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
6.2.8
Internal 1 MHz RC vs. Supply Voltage (Ta=25℃)
3.00%
1M HV
1M LV
2.00%
1.00%
0.00%
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
5.2 5.4 5.6 5.8
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.46/FM8PB56B
EELING
FM8PB56B
6.2.9
Internal 455 KHz RC vs. Supply Voltage (Ta=25℃)
3.00%
2.00%
1.00%
0.00%
455K HV
455K LV
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-1.00%
-2.00%
-3.00%
Voltage
Note: Curves are for design reference only.
6.2.10 Low Voltage Detect (LVDT=2.0V) vs. Temperature
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.0V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.11 Low Voltage Detect (LVDT=3.6V) vs. Temperature
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-3.6V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.47/FM8PB56B
EELING
FM8PB56B
6.2.12 Low Voltage Detect (LVDT=1.8V) vs. Temperature
2.50
2.00
1.50
1.00
0.50
0.00
Avg-1.8V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.13 Low Voltage Detect (LVDT=2.2V) vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.2V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.14 Low Voltage Detect (LVDT=2.4V) vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.4V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.48/FM8PB56B
EELING
FM8PB56B
6.2.15 Low Voltage Detect (LVDT=2.6V) vs. Temperature
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.6V
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.16 WDT 18mS Reset time vs. Temperature
35.00
30.00
25.00
20.00
15.00
10.00
5.00
Avg-5V
Avg-3V
0.00
-40 -30 -20 -10
0
10 20 25 30 40 50 60 70 80 90 100 110 120 125
Temperature
Note: Curves are for design reference only.
6.2.17 WDT 18mS Reset time vs. Supply Voltage (Ta=25℃)
30.00
25.00
20.00
15.00
10.00
5.00
Avg-18mS
0.00
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.49/FM8PB56B
EELING
FM8PB56B
7.0 PACKAGE DIMENSION
7.1 18-PIN PDIP 300mil
D
C
TOP E-PIN INDENT £ 0.079
BOTTOM E-PIN INDENT £ 0.118
0.727
e
B
B1
D1
Dimension In Inches
Symbols
Min
Nom
-
Max
0.180
-
A
A1
A2
B
-
0.05
-
-
0.130
0.018
0.060
0.010
0.904
0.022
-
0.140
0.022
0.070
0.013
0.910
0.027
0.325
0.262
-
0.014
0.050
0.008
0.894
0.017
0.300
0.252
-
B1
C
D
D1
E
E1
e
0.256
0.100
-
L
0.125
-
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.50/FM8PB56B
EELING
FM8PB56B
7.2 18-PIN SOP 300mil
View “
A
D
View “
A
7o(4x)
e
B
£
L
Dimension In Inches
Symbols
Min
0.093
0.04
-
Nom
0.098
-
Max
0.104
0.012
-
A
A1
A2
B
0.091
0.016
0.009
-
0.013
0.007
0.447
0.291
-
0.020
0.011
0.463
0.299
-
C
D
E
0.295
0.050
0.406
0.032
-
e
H
0.394
0.015
0o
0.419
0.050
8o
L
θo
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.51/FM8PB56B
EELING
FM8PB56B
7.3 20-PIN SSOP 209mil
D
View “
A
C
b
e
-H-
GAUGE PLANE
0.004max.
SEATING PLANE
o
£
L
View “
A
L1
Dimension In Millimeters
Symbols
Min
-
Nom
-
Max
2.00
-
A
A1
A2
b
0.05
1.65
0.22
0.09
6.90
7.40
5.00
-
-
1.75
-
1.85
0.38
0.21
7.50
8.20
5.60
-
c
-
D
7.20
7.80
5.30
0.65
0.75
1.25
4o
E
E1
e
L
0.55
-
0o
0.95
-
8o
L1
θo
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.52/FM8PB56B
EELING
FM8PB56B
8.0 PACKAGE IR Re-flow Soldering Curve
250 5
10 1 sec
150 10
90 30 sec
2 ~ 5 / sec
2 ~ 5 / sec
Time
9.0 ORDERING INFORMATION
OTP Type MCU
FM8PB56BP
FM8PB56BD
FM8PB56BAR
Package Type
Pin Count
Package Size
300 mil
PDIP
SOP
18
18
20
300 mil
SSOP
209 mil
Web site: http://www.feeling-techcom.tw
Rev1.00.004 Aug 21, 2014
P.53/FM8PB56B
相关型号:
©2020 ICPDF网 联系我们和版权申明