FM8PE54AER [FEELING]
EPROM/ROM-Based 8-Bit Microcontroller Series;
| 型号： | FM8PE54AER |
| 厂家： | 
Feeling Technology |
| 描述： | EPROM/ROM-Based 8-Bit Microcontroller Series 可编程只读存储器 电动程控只读存储器 微控制器 |
| 文件： | 总44页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEELING
FM8PE54/E56
EPROM/ROM-Based 8-Bit Microcontroller Series
Devices Included in this Data Sheet:
‧ FM8PE54E/E56E : EPROM devices
‧ FM8PE54/E56 : Mask ROM devices
FEATURES
‧ Only 42 single word instructions
‧ All instructions are single cycle except for program branches which are two-cycle
‧ 13-bit wide instructions
‧ All ROM/EPROM area GOTO instruction
‧ All ROM/EPROM area subroutine CALL instruction
‧ 8-bit wide data path
‧ 5-level deep hardware stack
‧ Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
Device
Pins # I/O # EPROM/ROM (Word) RAM (Byte)
FM8PE54/E54E
FM8PE56/E56E
18
18
16
16
512
1K
49
49
‧ Direct, indirect addressing modes for data accessing
‧ 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
‧ Internal Power-on Reset (POR)
‧ Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
‧ Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
‧ On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
‧ Two I/O ports IOA and IOB with independent direction control (maximum 16 I/O pins)
‧ Soft-ware I/O pull-high/pull-down or open-drain control
‧ One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change
‧ Wake-up from SLEEP by INT pin or Port B input change
‧ Power saving SLEEP mode
‧ Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator
‧ Programmable Code Protection
‧ Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- XT: Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
- IRC: Internal Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
‧ Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev1.5 May 21, 2010
P.1/FM8PE54/E56
FEELING
GENERAL DESCRIPTION
FM8PE54/E56
The FM8PE54/E56 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit
CMOS microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle
except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces
development time significantly.
The FM8PE54/E56 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer
(PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O
pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter,
Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are three oscillator
configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator.
The FM8PE54/E54E address 512×13 of program memory, and the FM8PE56/E56E address 1K×13 of program
memory.
The FM8PE54/E56 can directly or indirectly address its register files and data memory. All special function registers
including the program counter are mapped in the data memory.
BLOCK DIAGRAM
5-level
STACK
Oscillator
Circuit
SRAM
FSR
Watchdog
Timer
Program
Counter
PORTA
PORTB
EPROM
/ ROM
Instruction
Decoder
ALU
Interrupt
Control
Timer0
Accumulator
Rev1.5 May 21, 2010
P.2/FM8PE54/E56
FEELING
PIN CONNECTION
FM8PE54/E56
PDIP, SOP
SSOP
IOA2
IOA3
1
2
3
4
5
6
7
8
9
18 IOA1
IOA2
IOA3
1
2
3
4
5
6
7
8
9
20 IOA1
17 IOA0
19 IOA0
IOA4/T0CKI
IOA5/RSTB
Vss
16 IOA7/OSCI
15 IOA6/OSCO
14 Vdd
IOA4/T0CKI
IOA5/RSTB
Vss
18 IOA7/OSCI
17 IOA6/OSCO
16 Vdd
FM8PE54
FM8PE54E
FM8PE56
FM8PE56E
FM8PE54
FM8PE54E
FM8PE56
FM8PE56E
IOB0/INT
IOB1
13 IOB7
Vss
15 Vdd
12 IOB6
IOB0/INT
IOB1
14 IOB7
IOB2
11 IOB5
13 IOB6
IOB3
10 IOB4
IOB2
12 IOB5
IOB3 10
11 IOB4
PIN DESCRIPTIONS
Name
I/O
Description
IOA0 ~ IOA7
IOB0/INT
I/O IOA0 ~ IOA7 as bi-direction I/O port, and IOA5 is an input only pin.
I/O Bi-direction I/O pin with system wake-up function / External interrupt input
I/O Bi-direction I/O port with system wake-up function
IOB1 ~ IOB7
Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current
consumption
T0CKI
RSTB
OSCI
I
I
I
System clear (RESET) input. This pin is an active low RESET to the device.
X’tal type: Oscillator crystal input
RC type: Clock input of RC oscillator
X’tal type: Oscillator crystal output.
RC mode: Outputs with the instruction cycle rate
Positive supply
OSCO
O
Vdd
Vss
-
-
Ground
Legend: I=input, O=output, I/O=input/output
Rev1.5 May 21, 2010
P.3/FM8PE54/E56
FEELING
1.0 MEMORY ORGANIZATION
FM8PE54/E56
FM8PE54/E56 memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PE54/E54E have a 9-bit Program Counter (PC) capable of addressing a 512×13 program memory space.
The FM8PE56/E56E have a 10-bit Program Counter capable of addressing a 1K×13 program memory space.
The RESET vector for the FM8PE54/E54E is at 1FFh. The RESET vector for the FM8PE56/E56E is at 3FFh.
The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h.
FM8PE54/E56 supports all ROM/EPROM area CALL/GOTO instructions without page.
FIGURE 1.1: Program Memory Map and STACK
PC<9:0>
Stack 1
Stack 2
PC<8:0>
Stack 3
Stack 4
Stack 5
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
3FFh
Reset Vector
1FFh
Reset Vector
:
:
:
:
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
008h H/W Interrupt Vector
002h S/W Interrupt Vector
000h
FM8PE54/E54E
FM8PE56/E56E
Rev1.5 May 21, 2010
P.4/FM8PE54/E56
FEELING
FM8PE54/E56
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
TABLE 1.1: Registers File Map for FM8P54/56 Series
Address
00h
Description
INDF
TMR0
01h
02h
PCL
N/A
OPTION
03h
STATUS
04h
FSR
05h
PORTA
05h
06h
IOSTA
IOSTB
06h
PORTB
07h
General Purpose Register
PCON
08h
09h
WUCON
0Ah
PCHBUF
0Bh
PDCON
0Ch
0Dh
0Eh
ODCON
PHCON
INTEN
0Fh
INTFLAG
General Purpose Registers
10h ~ 3Fh
TABLE 1.2: The Registers Controlled by OPTION or IOST Instructions
Address
N/A (w)
05h (w)
06h (w)
Name
OPTION
IOSTA
B7
-
B6
B5
B4
B3
B2
B1
B0
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Port A I/O Control Register
Port B I/O Control Register
IOSTB
TABLE 1.3: Operational Registers Map
Address
00h (r/w)
01h (r/w)
02h (r/w)
03h (r/w)
04h (r/w)
05h (r/w)
06h (r/w)
07h (r/w)
08h (r/w)
09h (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
C
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
TMR0
PCL
Low order 8 bits of PC
STATUS
FSR
GP2
*
GP1
*
GP0
TO
PD
Z
DC
Indirect data memory address pointer
PORTA
PORTB
SRAM
PCON
WUCON
IOA7
IOB7
IOA6
IOB6
IOA5
IOB5
IOA4
IOB4
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
General Purpose Register
WDTE
WUB7
-
EIS
WUB6
-
LVDTE
WUB5
-
ROC
WUB4
-
-
-
-
-
WUB3
WUB2
WUB1
WUB0
0Ah (r/w) PCHBUF (2)
-
2 MSBs Buffer of PC
0Bh (r/w)
0Ch (r/w)
0Dh (r/w)
0Eh (r/w)
0Fh (r/w)
PDCON
ODCON
PHCON
INTEN
/PDB3
ODB7
/PHB7
GIE
/PDB2
ODB6
/PHB6
-
/PDB1
ODB5
/PHB5
-
/PDB0
ODB4
/PHB4
-
/PDA3
ODB3
/PHB3
-
/PDA2
ODB2
/PHB2
INTIE
INTIF
/PDA1
ODB1
/PHB1
PBIE
/PDA0
ODB0
/PHB0
T0IE
INTFLAG
-
-
-
-
-
PBIF
T0IF
Legend: - = unimplemented, read as ‘0’, * = unimplemented, read as ‘1’
Note 1 : There is only 1 bit in FM8PE54/E54E. And there are 2 bits in FM8PE56/E56E.
Rev1.5 May 21, 2010
P.5/FM8PE54/E56
FEELING
2.0 FUNCTIONAL DESCRIPTIONS
FM8PE54/E56
2.1 Operational Registers
2.1.1 INDF (Indirect Addressing Register)
Address
00h (r/w)
Name
INDF
B7
B6
B5
B4
B3
B2
B1
B0
Uses contents of FSR to address data memory (not a physical register)
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the
INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh).
EXAMPLE 2.1: INDIRECT ADDRESSING
‧ Register file 38 contains the value 10h
‧ Register file 39 contains the value 0Ah
‧ Load the value 38 into the FSR Register
‧ A read of the INDF Register will return the value of 10h
‧ Increment the value of the FSR Register by one (@FSR=39h)
‧ A read of the INDR register now will return the value of 0Ah.
FIGURE 2.1: Direct/Indirect Addressing
Direct Addressing
Indirect Addressing
5
from opcode
0
5 from FSR register 0
location select
00h
3Fh
location select
addressing INDF register
Rev1.5 May 21, 2010
P.6/FM8PE54/E56
FEELING
FM8PE54/E56
2.1.2 TMR0 (Time Clock/Counter register)
Address
01h (r/w)
Name
TMR0
B7
B6
B5
B4
B3
B2
B1
B0
8-bit real-time clock/counter
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock or by an
external clock source (T0CKI pin) defined by T0CS bit (OPTION<5>). If T0CKI pin is selected, the Timer0 is
increased by T0CKI signal rising/falling edge (selected by T0SE bit (OPTION<4>)).
The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared
when TMR0 register is written with a value.
2.1.3 PCL (Low Bytes of Program Counter) & Stack
Address
02h (r/w)
Name
PCL
B7
B6
B5
B4
B3
B2
B1
B0
Low order 8 bits of PC
FM8PE54/E56 devices have a 9-bit (for FM8PE54/E54E) or 10-bit (for FM8PE56/E56E) wide Program Counter (PC)
and five-level deep 9-bit (or 10-bit) hardware push/pop stack. The low byte of PC is called the PCL register. This
register is readable and writable. The high byte of PC is called the PCH register. This register contains the PC<9:8>
bits and is not directly readable or writable. All updates to the PCH register go through the PCHBUF register. As a
program instruction is executed, the Program Counter will contain the address of the next program instruction to be
executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PCL register is mapped to
PC<7:0>, and the PCHBUF register is not updated.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The next PC will be loaded (PUSHed)
onto the top of STACK. The PCL register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>, and the PCHBUF register is not updated.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result.
However, the PC<9:8> will come from the PCHBUF<1:0> bits (PCHBUF Æ PCH).
PCHBUF register is never updated with the contents of PCH.
Rev1.5 May 21, 2010
P.7/FM8PE54/E56
FEELING
FM8PE54/E56
FIGURE 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
PCL
9
8
7
-
0
PC
Opcode<9:0>
-
-
-
-
-
PCHBUF
Situation 2: CALL Instruction
STACK<9:0>
Opcode<9:0>
PCH
PCL
9
8
7
-
0
PC
-
-
-
-
-
PCHBUF
Situation 3: RETIA, RETFIE, or RETURN Instruction
STACK<9:0>
PCH
PCL
9
8
7
-
0
PC
-
-
-
-
-
PCHBUF
Situation 4: Instruction with PCL as destination
PCH PCL
9
8
7
0
PC
ALU result<7:0>
or Opcode<7:0>
PCHBUF<1:0>
-
-
-
-
-
-
PCHBUF
Note: 1. Bits PC<9> and PCHBUF<1> are unimplemented for FM8PE54/E54E.
2. PCHBUF is used only for instruction with PCL as destination for FM8PE54/E54E/56/E56E.
Rev1.5 May 21, 2010
P.8/FM8PE54/E56
FEELING
FM8PE54/E56
2.1.4 STATUS (Status Register)
Address
03h (r/w)
Name
B7
B6
B5
B4
B3
B2
Z
B1
B0
C
STATUS
GP2
GP1
GP0
TO
PD
DC
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the
STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR, ADDIA
= 1, a carry occurred.
= 0, a carry did not occur.
SUBAR, SUBIA
= 1, a borrow did not occur.
= 0, a borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit.
ADDAR, ADDIA
= 1, a carry from the 4th low order bit of the result occurred.
= 0, a carry from the 4th low order bit of the result did not occur.
SUBAR, SUBIA
= 1, a borrow from the 4th low order bit of the result did not occur.
= 0, a borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, the result of a logic operation is zero.
= 0, the result of a logic operation is not zero.
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
TO : Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
= 0, a watch-dog time overflow occurred.
GP2:GP0 : General purpose read/write bits.
2.1.5 FSR (Indirect Data Memory Address Pointer)
Address
04h (r/w)
Name
FSR
B7
*
B6
*
B5
B4
B3
B2
B1
B0
Indirect data memory address pointer
Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
Bit7:Bit6 : Not used. Read as “1”s.
Rev1.5 May 21, 2010
P.9/FM8PE54/E56
FEELING
2.1.6 PORTA & PORTB (Port Data Registers)
FM8PE54/E56
Address
05h (r/w)
06h (r/w)
Name
PORTA
PORTB
B7
B6
B5
B4
B3
B2
B1
B0
IOA7
IOB7
IOA6
IOB6
IOA5
IOB5
IOA4
IOB4
IOA3
IOB3
IOA2
IOB2
IOA1
IOB1
IOA0
IOB0
Reading the port (PORTA, PORTB register) reads the status of the pins independent of the pin’s input/output modes.
Writing to these ports will write to the port data latch.
PORTA and PORTB are 8-bit port data Registers.
2.1.7 PCON (Power Control Register)
Address
08h (r/w)
Name
PCON
B7
B6
B5
B4
B3
-
B2
-
B1
-
B0
-
WDTE
EIS
LVDTE
ROC
Bit3:Bit0 : Not used. Read as “0”s.
ROC : R-option function of IOA0 and IOA1 pins enable bit.
= 0, Disable the R-option function.
= 1, Enable the R-option function. In this case, if a 430KΩ external resister is connected/disconnected to Vss,
the status of IOA0 (IOA1) is read as “0”/”1”.
LVDTE : LVDT (low voltage detector) enable bit.
= 0, Disable LVDT.
= 1, Enable LVDT.
EIS : Define the function of IOB0/INT pin.
= 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked.
= 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path
of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way
of reading PORTB.
WDTE : WDT (watch-dog timer) enable bit.
= 0, Disable WDT.
= 1, Enable WDT.
2.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register)
Address
09h (r/w)
Name
B7
B6
B5
B4
B3
B2
B1
B0
WUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
WUB0 : = 0, Disable the input change interrupt/wake-up function of IOB0 pin.
= 1, Enable the input change interrupt/wake-up function of IOB0 pin.
WUB1 : = 0, Disable the input change interrupt/wake-up function of IOB1 pin.
= 1, Enable the input change interrupt/wake-up function of IOB1 pin.
WUB2 : = 0, Disable the input change interrupt/wake-up function of IOB2 pin.
= 1, Enable the input change interrupt/wake-up function of IOB2 pin.
WUB3 : = 0, Disable the input change interrupt/wake-up function of IOB3 pin.
= 1, Enable the input change interrupt/wake-up function of IOB3 pin.
WUB4 : = 0, Disable the input change interrupt/wake-up function of IOB4 pin.
Rev1.5 May 21, 2010
P.10/FM8PE54/E56
FEELING
FM8PE54/E56
= 1, Enable the input change interrupt/wake-up function of IOB4 pin.
WUB5 : = 0, Disable the input change interrupt/wake-up function of IOB5 pin.
= 1, Enable the input change interrupt/wake-up function of IOB5 pin.
WUB6 : = 0, Disable the input change interrupt/wake-up function of IOB6 pin.
= 1, Enable the input change interrupt/wake-up function of IOB6 pin.
WUB7 : = 0, Disable Enable the input change interrupt/wake-up function of IOB7 pin.
= 1, Enable the input change interrupt/wake-up function of IOB7 pin.
2.1.9 PCHBUF (High Byte Buffer of Program Counter)
Address
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
B1
B0
0Ah (r/w)
PCHBUF
2 MSBs Buffer of PC
There is only 1 bit in FM8PE54/E54E. And there are 2 bits in FM8PE56/E56E.
See 2.1.3 for detail description.
2.1.10 PDCON (Pull-down Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Bh (r/w)
PDCON
/PDB3
/PDB2
/PDB1
/PDB0
/PDA3
/PDA2
/PDA1
/PDA0
/PDA0 : = 0, Enable the internal pull-down of IOA0 pin.
= 1, Disable the internal pull-down of IOA0 pin.
/PDA1 : = 0, Enable the internal pull-down of IOA1 pin.
= 1, Disable the internal pull-down of IOA1 pin.
/PDA2 : = 0, Enable the internal pull-down of IOA2 pin.
= 1, Disable the internal pull-down of IOA2 pin.
/PDA3 : = 0, Enable the internal pull-down of IOA3 pin.
= 1, Disable the internal pull-down of IOA3 pin.
/PDB0 : = 0, Enable the internal pull-down of IOB0 pin.
= 1, Disable the internal pull-down of IOB0 pin.
/PDB1 : = 0, Enable the internal pull-down of IOB1 pin.
= 1, Disable the internal pull-down of IOB1 pin.
/PDB2 : = 0, Enable the internal pull-down of IOB2 pin.
= 1, Disable the internal pull-down of IOB2 pin.
/PDB3 : = 0, Enable the internal pull-down of IOB3 pin.
= 1, Disable the internal pull-down of IOB3 pin.
Rev1.5 May 21, 2010
P.11/FM8PE54/E56
FEELING
2.1.11 ODCON (Open-drain Control Register)
FM8PE54/E56
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Ch (r/w)
ODCON
ODB7
ODB6
ODB5
ODB4
ODB3
ODB2
ODB1
ODB0
ODB0 : = 0, Disable the internal open-drain of IOB0 pin.
= 1, Enable the internal open-drain of IOB0 pin.
ODB1 : = 0, Disable the internal open-drain of IOB1 pin.
= 1, Enable the internal open-drain of IOB1 pin.
ODB2 : = 0, Disable the internal open-drain of IOB2 pin.
= 1, Enable the internal open-drain of IOB2 pin.
ODB3 : = 0, Disable the internal open-drain of IOB3 pin.
= 1, Enable the internal open-drain of IOB3 pin.
ODB4 : = 0, Disable the internal open-drain of IOB4 pin.
= 1, Enable the internal open-drain of IOB4 pin.
ODB5 : = 0, Disable the internal open-drain of IOB5 pin.
= 1, Enable the internal open-drain of IOB5 pin.
ODB6 : = 0, Disable the internal open-drain of IOB6 pin.
= 1, Enable the internal open-drain of IOB6 pin.
ODB7 : = 0, Disable the internal open-drain of IOB7 pin.
= 1, Enable the internal open-drain of IOB7 pin.
2.1.12 PHCON (Pull-high Control Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
0Dh (r/w)
PHCON
/PHB7
/PHB6
/PHB5
/PHB4
/PHB3
/PHB2
/PHB1
/PHB0
/PHB0 : = 0, Enable the internal pull-high of IOB0 pin.
= 1, Disable the internal pull-high of IOB0 pin.
/PHB1 : = 0, Enable the internal pull-high of IOB1 pin.
= 1, Disable the internal pull-high of IOB1 pin.
/PHB2 : = 0, Enable the internal pull-high of IOB2 pin.
= 1, Disable the internal pull-high of IOB2 pin.
/PHB3 : = 0, Enable the internal pull-high of IOB3 pin.
= 1, Disable the internal pull-high of IOB3 pin.
/PHB4 : = 0, Enable the internal pull-high of IOB4 pin.
= 1, Disable the internal pull-high of IOB4 pin.
/PHB5 : = 0, Enable the internal pull-high of IOB5 pin.
= 1, Disable the internal pull-high of IOB5 pin.
/PHB6 : = 0, Enable the internal pull-high of IOB6 pin.
= 1, Disable the internal pull-high of IOB6 pin.
Rev1.5 May 21, 2010
P.12/FM8PE54/E56
FEELING
FM8PE54/E56
/PHB7 : = 0, Enable the internal pull-high of IOB7 pin.
= 1, Disable the internal pull-high of IOB7 pin.
2.1.13 INTEN (Interrupt Mask Register)
Address
Name
B7
B6
-
B5
-
B4
-
B3
-
B2
B1
B0
0Eh (r/w)
INTEN
GIE
INTIE
PBIE
T0IE
T0IE : Timer0 overflow interrupt enable bit.
= 0, Disable the Timer0 overflow interrupt.
= 1, Enable the Timer0 overflow interrupt.
PBIE : Port B input change interrupt enable bit.
= 0, Disable the Port B input change interrupt.
= 1, Enable the Port B input change interrupt .
INTIE : External INT pin interrupt enable bit.
= 0, Disable the External INT pin interrupt.
= 1, Enable the External INT pin interrupt.
Bit6:BIT3 : Not used. Read as “0”s.
GIE : Global interrupt enable bit.
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue
execution at the instruction after the SLEEP instruction.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (008h).
Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the
GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the
interrupt routine and set the GIE bit to re-enable interrupt.
2.1.14 INTFLAG (Interrupt Status Register)
Address
0Fh (r/w)
Name
B7
-
B6
-
B5
-
B4
-
B3
-
B2
B1
B0
INTFLAG
INTIF
PBIF
T0IF
T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software.
PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software.
INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION<6>)) edge on INT pin,
reset by software.
Bit7:BIT3 : Not used. Read as “0”s.
2.1.15 ACC (Accumulator)
Address
N/A (r/w)
Name
ACC
B7
B6
B5
B4
B3
B2
B1
B0
Accumulator
Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed.
Rev1.5 May 21, 2010
P.13/FM8PE54/E56
FEELING
FM8PE54/E56
2.1.16 OPTION Register
Address
N/A (w)
Name
B7
-
B6
B5
B4
B3
B2
B1
B0
OPTION
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Accessed by OPTION instruction.
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0 : Prescaler rate select bits.
PS2:PS0
Timer0 Rate
WDT Rate
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
PSA : Prescaler assign bit.
= 1, WDT (watch-dog timer).
= 0, TMR0 (Timer0).
T0SE : TMR0 source edge select bit.
= 1, Falling edge on T0CKI pin.
= 0, Rising edge on T0CKI pin.
T0CS : TMR0 clock source select bit.
= 1, External T0CKI pin.
= 0, internal instruction clock cycle.
INTEDG : Interrupt edge select bit.
= 1, interrupt on rising edge of INT pin.
= 0, interrupt on falling edge of INT pin.
Bit7 : Not used.
2.1.17 IOSTA, & IOSTB (Port I/O Control Registers)
Address
05h (w)
06h (w)
Name
IOSTA
IOSTB
B7
B6
B5
B4
B3
B2
B1
B0
Port A I/O Control Register
Port B I/O Control Register
Accessed by IOST instruction.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~06h)
instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode).
A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode).
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
Rev1.5 May 21, 2010
P.14/FM8PE54/E56
FEELING
2.2 I/O Ports
FM8PE54/E56
Port A and port B are bi-directional tri-state I/O ports. Port A and Port B are 8-pin I/O ports. Port C is a general
purpose register. Please note that IOA5 is an input only pin.
All I/O pins (IOA<7:0> and IOB<7:0>) have data direction control registers (IOSTA, IOSTB) which can configure
these pins as output or input.
IOB<7:0> have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high. The
weak pull-high is automatically turned off when the pin is configured as an output pin.
IOA<3:0> and IOB<3:0> have its corresponding pull-down control bits (PDCON register) to enable the weak internal
pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin.
IOB<7:0> have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when
these pins are configured to be an output pin.
IOA0 and IOA1 are the R-option pins enabled by setting the ROC bit (PCON<4>). When the R-option function is
used, it is recommended that IOA0 and IOA1 are used as output pins, and read the status of IOA0 and IOA1 before
these pins are configured to be an output pin.
IOB<7:0> also provides the input change interrupt/wake-up function. Each pin has its corresponding input change
interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source.
The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON<6>). In this case, IOB0 input change
interrupt/wake-up function will be disabled by hardware even if it is enabled by software.
FIGURE 2.3: Block Diagram of I/O PINs
IOA7, IOA6, IOA4 ~ IOA0 :
Data bus
D
Q
IOST
Latch
> EN
Q
Q
IOST R
I/O PIN
D
DATA
Latch
> EN
Q
WR PORT
RD PORT
Pull-down is not shown in the figure
IOA5 :
Data bus
I/O PIN
RD PORT
Rev1.5 May 21, 2010
P.15/FM8PE54/E56
FEELING
FM8PE54/E56
IOB0/INT :
Data bus
D
Q
IOST
Latch
> EN
Q
Q
IOST R
I/O PIN
D
DATA
Latch
> EN
Q
WR PORT
RD PORT
Q
Q
D
Set PBIF
Latch
EN<
WUBn
EIS
INTEDG
EIS
INT
Pull-high/pull-down and open-drain are not shown in the figure
IOB7 ~ IOB1 :
Data bus
D
Q
IOST
Latch
> EN
Q
Q
IOST R
I/O PIN
D
DATA
Latch
> EN
Q
WR PORT
RD PORT
Q
Q
D
Set PBIF
Latch
EN<
WUBn
Pull-high/pull-down and open-drain are not shown in the figure
Rev1.5 May 21, 2010
P.16/FM8PE54/E56
FEELING
2.3 Timer0/WDT & Prescler
FM8PE54/E56
2.3.1 Timer0
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external
clock source (T0CKI pin).
2.3.1.1 Using Timer0 with an Internal Clock : Timer mode
Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the timer0 register (TMR0) will
increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the
following two cycles.
2.3.1.2 Using Timer0 with an External Clock : Counter mode
Counter mode is selected by setting the T0CS bit (OPTON<5>). In this mode, Timer0 will increment either on every
rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit T0SE
(OPTION<4>).
The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the
actual incrementing of Timer0 after synchronization.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of
T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the T2 and T4 cycles of
the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2
Tosc.
When a prescaler is used, the external clock input is divided by the asynchronous prescaler. For the external clock
to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for
T0CKI to have a period of at least 4Tosc divided by the prescaler value.
2.3.2 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components.
So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode. During
normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS<4>) will
be cleared.
The WDT can be disabled by clearing the control bit WDTE (PCON<7>) to “0”.
The WDT has a nominal time-out period of 18 ms (without prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register. Thus,
the longest time-out period is approxmately 2.3 seconds.
The CLRWDT instruction clears the WDT and the prescaler, if assigned to the WDT, and prevents it from timing out
and generating a device reset.
The SLEEP instruction resets the WDT and the prescaler, if assigned to the WDT. This gives the maximum SLEEP
time before a WDT Wake-up Reset.
2.3.3 Prescaler
An 8-bit counter (down counter) is available as a prescaler for the Timer0, or as a postscaler for the Watchdog Timer
(WDT). Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a
prescaler assignment for the Timer0 means that there is no prescaler for the WDT, and vice-versa.
The PSA bit (OPTION<3>) determines prescaler assignment. The PS<2:0> bits (OPTION<2:0>) determine
prescaler ratio.
When the prescaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the
prescaler. When it is assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.
The prescaler is neither readable nor writable. On a RESET, the prescaler contains all ‘1’s.
To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the
prescaler assignment from Timer0 to the WDT, and vice-versa.
Rev1.5 May 21, 2010
P.17/FM8PE54/E56
FEELING
FM8PE54/E56
FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler
Instruction Cycle
(Fosc/4 or Fosc/2 or Fosc/8)
0
1
8
MUX
Data Bus
TMR0
Register
Sync
2 Cycles
T0CKI
1
MUX
PSA
0
Set T0IF flag
on overflow
T0SE
T0CS
0
1
1
0
8-Bit
Prescaler
MUX
PSA
Watchdog
Timer
WDT Time-out
MUX
PSA
PS2:PS0
2.4 Interrupts
The FM8PE54/E56 series has up to three sources of interrupt:
1. External interrupt INT pin.
2. TMR0 overflow interrupt.
3. Port B input change interrupt (pins IOB7:IOB0).
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h.
The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.
2.4.1 External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled by
clearing INTIE bit (INTEN<2>).
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If
GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.4.2 Timer0 Interrupt
An overflow (FFh Æ 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
disabled by clearing T0IE bit (INTEN<0>).
Rev1.5 May 21, 2010
P.18/FM8PE54/E56
FEELING
FM8PE54/E56
2.4.3 Port B Input Change Interrupt
An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit
(INTEN<1>).
Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including
read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared to “0” or
configured as output or IOB0 pin configured as INT pin will be excluded from this function.
The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before
going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following
wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared,
the program will execute next PC after wake-up.
2.5 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will
be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.5.1 Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1. RSTB reset.
2. WDT time-out reset (if enabled).
3. Interrupt from RB0/INT pin, or PORTB change interrupt.
External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to
determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is
executed. The TO bit is cleared if a WDT time-out occurred.
For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up
is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP
instruction. If the GIE bit is set, the device will branch to the interrupt address (008h).
The system wake-up delay time is 18ms plus 128 oscillator cycle time.
2.6 Reset
FM8PE54/E56 devices may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT
Reset.
A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely ties
the RSTB pin to Vdd.
On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
Rev1.5 May 21, 2010
P.19/FM8PE54/E56
FEELING
FM8PE54/E56
2.6.1 Power-up Reset Timer(PWRT)
The Power-up Reset Timer provides a nominal 18ms delay after Power-on Reset (POR), Brown-out Reset (BOR),
RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active.
The PWDT delay will vary from device to device due to Vdd, temperature, and process variation.
2.6.2 Oscillator Start-up Timer(OST)
The OST timer provides a 128 oscillator cycle delay (from OSCI input) after the PWRT delay (18ms) is over. This
delay ensures that the X’tal oscillator or resonator has started and stabilized. The device is kept in reset state as
long as the OST is active.
This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds.
2.6.3 Reset Sequence
When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset
sequence is as follows:
1. The reset latch is set and the PWRT & OST are cleared.
2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins
counting.
3. After the PWRT time-out, the OST is activated.
4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal.
The totally system reset delay time is 18ms plus 128 oscillator cycle time.
FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit
WDT
Time-out
WDT
Module
S
R
Q
Q
RSTB
Vdd
Reset
Latch
Low Voltage
Detector
(LVD)
BOR
POR
CHIP RESET
Power-on
Reset
(POR)
RESET
RESET
On-Chip
RC OSC
Power-up
Reset Timer
(PWRT)
Oscillator
Start-up Timer
(OST)
OSCI
Rev1.5 May 21, 2010
P.20/FM8PE54/E56
FEELING
FM8PE54/E56
TABLE 2.1: Reset Conditions for All Registers
Power-on Reset
RSTB Reset
WDT Reset
Register
Address
Brown-out Reset
xxxx xxxx
-011 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
11xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1010 ----
0000 0000
ACC
OPTION
IOSTA
N/A
N/A
05h
06h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
uuuu uuuu
-011 1111
1111 1111
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
000# #uuu
11uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1010 ----
0000 0000
IOSTB
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
General Purpose Register
PCON
WUCON
54: ---- ---0
56: ---- --00
54: ---- ---0
56: ---- --00
PCHBUF
0Ah
PDCON
ODCON
0Bh
0Ch
1111 1111
0000 0000
1111 1111
0--- -000
---- -000
xxxx xxxx
1111 1111
0000 0000
1111 1111
0--- -000
---- -000
uuuu uuuu
PHCON
0Dh
INTEN
0Eh
INTFLAG
0Fh
General Purpose Registers
10 ~ 3Fh
Legend: u = unchanged, x = unknown, - = unimplemented,
# = refer to the following table for possible values.
TABLE 2.2: TO /PD Status after Reset
TO
1
PD
1
RESET was caused by
Power-on Reset
1
1
Brown-out reset
u
u
RSTB Reset during normal operation
RSTB Reset during SLEEP
WDT Reset during normal operation
WDT Reset during SLEEP
1
0
0
1
0
0
Legend: u = unchanged
TABLE 2.3: Events Affecting TO /PD Status Bits
Event
TO
1
PD
1
Power-on
WDT Time-Out
0
u
SLEEP instruction
CLRWDT instruction
Legend: u = unchanged
1
0
1
1
Rev1.5 May 21, 2010
P.21/FM8PE54/E56
FEELING
2.7 Hexadecimal Convert to Decimal (HCD)
FM8PE54/E56
Decimal format is another number format for FM8PE54/E56. When the content of the data memory has been
assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU
instructions. When the decimal converting operation is processing, all of the operand data (including the contents of
the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or
the results of conversion will be incorrect.
Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and
restored to ACC.
The conversion operation is illustrated in example 2.2.
EXAMPLE 2.2: DAA CONVERSION
MOVIA
MOVAR 30h
MOVIA
ADDAR
90h
;Set immediate data = decimal format number “90” (ACC Å 90h)
;Load immediate data “90” to data memory address 30H
;Set immediate data = decimal format number “10” (ACC Å 10h)
;Contents of the data memory address 30H and ACC are binary-added
;the result loads to the ACC (ACC Å A0h, C Å 0)
10h
30h, 0
DAA
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “00” and the carry bit C is “1”. This represents the
;decimal number “100”
Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction
operation and restored to ACC.
The conversion operation is illustrated in example 2.3.
EXAMPLE 2.3: DAS CONVERSION
MOVIA
MOVAR 30h
MOVIA
SUBAR
10h
;Set immediate data = decimal format number “10” (ACC Å 10h)
;Load immediate data “10” to data memory address 30H
;Set immediate data = decimal format number “20” (ACC Å 20h)
;Contents of the data memory address 30H and ACC are binary-subtracted
;the result loads to the ACC (ACC Å F0h, C Å 0)
20h
30h, 0
DAS
;Convert the content of ACC to decimal format, and restored to ACC
;The result in the ACC is “90” and the carry bit C is “0”. This represents the
;decimal number “ -10”
Rev1.5 May 21, 2010
P.22/FM8PE54/E56
FEELING
2.8 Oscillator Configurations
FM8PE54/E56
FM8PE54/E56 can be operated in six different oscillator modes. Users can program three configuration bits
(Fosc<2:0>) to select the appropriate modes:
‧ ERC: External Resistor/Capacitor Oscillator
‧ HF: High Frequency Crystal/Resonator Oscillator
‧ XT: Crystal/Resonator Oscillator
‧ LF: Low Frequency Crystal Oscillator
‧ IRC: Internal Resistor/Capacitor Oscillator
‧ ERIC: External Resistor/Internal Capacitor Oscillator
In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish
oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin.
The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator
frequency is a function of the resistor (Rext) and capacitor (Cext), the operating temperature, and the process
parameter.
The IRC/ERIC device option offers largest cost savings for timing insensitive applications. These devices offer 4
different internal RC oscillator frequency, 8MHz, 4MHz, 1MHz, and 455KHz, which is selected by two configuration
bits (RCM<1:0>). Or user can change the oscillator frequency with external resistor. The ERIC oscillator frequency
is a function of the resistor (Rext), the operating temperature, and the process parameter.
FIGURE 2.6: HF, XT, or LF Oscillator Modes (Crystal Operation or Ceramic Resonator)
FM8PE54/E56
OSCI
C1
C2
X’TAL
RS
SLEEP
RF
OSCO
Internal
Circuit
FIGURE 2.7: HF, XT, or LF Oscillator Modes (External Clock Input Operation)
FM8PE54/E56
OSCI
Clock from
External System
OSCO
Open
Rev1.5 May 21, 2010
P.23/FM8PE54/E56
FEELING
FM8PE54/E56
FIGURE 2.8: ERC Oscillator Mode
Rext
Cext
FM8PE54/E56
OSCI
Internal
Circuit
OSCO
/2,/4,/8
FIGURE 2.9: IRC Oscillator Mode (Internal R, Internal C Oscillator)
FM8PE54/E56
OSCI
Internal
Circuit
C
OSCO
/2,/4,/8
FIGURE 2.10: ERIC Oscillator Mode (External R, Internal C Oscillator)
Rext
FM8PE54/E56
OSCI
Cext (optional)
OSCO
Internal
Circuit
C
/2,/4,/8
Rev1.5 May 21, 2010
P.24/FM8PE54/E56
FEELING
2.9 Configurations Word
FM8PE54/E56
TABLE 2.4: Configurations Word
Name
Description
Oscillator Selection Bits
= 1, 1, 1 Æ ERC mode (external R & C) (default)
= 1, 1, 0 Æ HF mode
Fosc<2:0>
= 1, 0, 1 Æ XT mode
= 1, 0, 0 Æ LF mode
= 0, 1, 1 Æ IRC mode (internal R & C)
= 0, 1, 0 Æ ERIC mode (external R & internal C)
Low Voltage Detector Selection Bit
= 1, 1, 1 Æ disable (default)
= 1, 1, 0 Æ enable, LVDT voltage = 2.0V, controlled by SLEEP
= 1, 0, 1 Æ enable, LVDT voltage = 2.0V
= 1, 0, 0 Æ enable, LVDT voltage = 3.6V
= 0, 1, 1 Æ enable, LVDT voltage = 1.8V
= 0, 1, 0 Æ enable, LVDT voltage = 2.2V
= 0, 0, 1 Æ enable, LVDT voltage = 2.4V
= 0, 0, 0 Æ enable, LVDT voltage = 2.6V
IRC Mode Selection Bits
LVDT<2:0>
= 1, 1 Æ 4MHz (default)
RCM<1:0>
= 1, 0 Æ 8MHz
= 0, 1 Æ 1MHz
= 0, 0 Æ 455KHz
PWRT Time Period Selection Bits
= 1, 1 Æ PWRT = 18ms (default)
= 1, 0 Æ PWRT = 4.5ms
PWRT<1:0>
= 0, 1 Æ PWRT = 288ms
= 0, 0 Æ PWRT = 72ms
IOA6/OSCO Pin Selection Bit for ERC/IRC/ERIC Mode
= 1, OSCO pin is selected (default)
= 0, IOA6 pin is selected
OSCOUT
RSTBIN
IOA5/RSTB Pin Selection Bit
= 1, IOA5 pin is selected (default)
= 0, RSTB pin is selected
Watchdog Timer Enable Bit
WDTEN
= 1, WDT enabled (default)
= 0, WDT disabled
Code Protection Bit
PROTECT
= 1 Æ EPROM code protection off (default)
= 0 Æ EPROM code protection on
Instruction Period Selection Bits
= 1, 1 Æ four oscillator periods (default)
= 1, 0 Æ two oscillator periods
OSCD<1:0>
= 0, 0 Æ eight oscillator periods
Power Mode Selection Bit
= 1, Non-power saving (default)
= 0, Power saving
PMOD
Read Port Control Bit for Output Pins
= 1, From registers (default)
= 0, From pins
RDPORT
SCHMITT
I/O Pin Input Buffer Control Bit
= 1, With Schmitt-trigger (default)
= 0, Without Schmitt-trigger
Rev1.5 May 21, 2010
P.25/FM8PE54/E56
FEELING
FM8PE54/E56
Name
RCT
Description
Wake-up & Subsequest-Resets Timer for ERC/IRC/ERIC modes
= 1, 140us (default)
= 0, 18ms
CAL<6:0>
Calibration Selection Bits for IRC Mode
Rev1.5 May 21, 2010
P.26/FM8PE54/E56
FEELING
FM8PE54/E56
3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Cycles
Description
Operation
Affected
BCR
BSR
BTRSC R, bit Test bit in R, Skip if Clear
R, bit Clear bit in R
0 Æ R<b>
1 Æ R<b>
1
1
-
-
-
-
-
R, bit Set bit in R
Skip if R<b> = 0
Skip if R<b> = 1
No operation
1/2 (1)
1/2 (1)
1
BTRSS
NOP
R, bit Test bit in R, Skip if Set
No Operation
00h Æ WDT,
00h Æ WDT prescaler
CLRWDT
OPTION
SLEEP
Clear Watchdog Timer
Load OPTION register
Go into power-down mode
1
1
1
TO PD
,
ACC Æ OPTION
-
00h Æ WDT,
TO PD
,
00h Æ WDT prescaler
PC + 1 Æ Top of Stack,
002h Æ PC
INT
S/W interrupt
2
1
-
Adjust ACC’s data format from
DAA
HEX to DEC after any addition ACC(hex) Æ ACC(dec)
C
operation
Adjust ACC’s data format from
HEX to DEC after any subtraction ACC(hex) Æ ACC(dec)
operation
DAS
1
-
RETURN
RETFIE
Return from subroutine
Top of Stack Æ PC
2
2
-
-
Top of Stack Æ PC,
1 Æ GIE
Return from interrupt, set GIE bit
CLRA
IOST
Clear ACC
00h Æ ACC
ACC Æ IOST register
00h Æ R
1
1
1
1
1
1
Z
-
R
R
R
Load IOST register
Clear R
CLRR
MOVAR
MOVR
DECR
Z
-
Move ACC to R
ACC Æ R
R, d Move R
R Æ dest
Z
Z
R, d Decrement R
R - 1 Æ dest
R - 1 Æ dest,
Skip if result = 0
DECRSZ R, d Decrement R, Skip if 0
INCR R, d Increment R
1/2 (1)
1
-
Z
-
R + 1 Æ dest
R + 1 Æ dest,
Skip if result = 0
INCRSZ R, d Increment R, Skip if 0
1/2 (1)
ADDAR R, d Add ACC and R
R + ACC Æ dest
R - ACC Æ dest
R + ACC + C Æ dest
R + ACC + C Æ dest
ACC and R Æ dest
ACC or R Æ dest
R xor ACC Æ dest
R Æ dest
1
1
1
1
1
1
1
1
C, DC, Z
SUBAR R, d Subtract ACC from R
ADCAR R, d Add ACC and R with Carry
SBCAR R, d Subtract ACC from R with Carry
ANDAR R, d AND ACC with R
C, DC, Z
C, DC, Z
C, DC, Z
Z
Z
Z
Z
IORAR
R, d Inclusive OR ACC with R
XORAR R, d Exclusive OR ACC with R
COMR
RLR
R, d Complement R
R<7> Æ C,
R<6:0> Æ dest<7:1>,
C Æ dest<0>
R, d Rotate left R through Carry
1
C
Rev1.5 May 21, 2010
P.27/FM8PE54/E56
FEELING
FM8PE54/E56
Mnemonic,
Status
Description
Operation
Cycles
Operands
Affected
C Æ dest<7>,
RRR
R, d Rotate right R through Carry
R<7:1> Æ dest<6:0>,
R<0> Æ C
1
C
R<3:0> Æ dest<7:4>,
R<7:4> Æ dest<3:0>
SWAPR R, d Swap R
1
-
MOVIA
ADDIA
SUBIA
ANDIA
IORIA
I
I
I
I
I
I
Move Immediate to ACC
Add ACC and Immediate
Subtract ACC from Immediate
AND Immediate with ACC
OR Immediate with ACC
I Æ ACC
1
1
1
1
1
1
-
I + ACC Æ ACC
I - ACC Æ ACC
ACC and I Æ ACC
ACC or I Æ ACC
C, DC, Z
C, DC, Z
Z
Z
Z
XORIA
Exclusive OR Immediate to ACC ACC xor I Æ ACC
I Æ ACC,
Return, place Immediate in ACC
Top of Stack Æ PC
RETIA
I
2
-
PC + 1 Æ Top of Stack,
I Æ PC<9:0>
CALL
I
I
Call subroutine
2
2
-
-
GOTO
Unconditional branch
I Æ PC<9:0>
Note: 1. 2 cycles for skip, else 1 cycle
2. bit : Bit address within an 8-bit register R
R : Register address (00h to 3Fh)
I : Immediate data
ACC : Accumulator
d : Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest : Destination
PC : Program Counter
PCHBUF : High Byte Buffer of Program Counter
WDT : Watchdog Timer Counter
GIE : Global interrupt enable bit
TO : Time-out bit
PD : Power-down bit
C : Carry bit
DC : Digital carry bit
Z : Zero bit
Rev1.5 May 21, 2010
P.28/FM8PE54/E56
FEELING
FM8PE54/E56
ADCAR
Syntax:
Add ACC and R with Carry
ADCAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R + ACC + C Æ dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDAR
Syntax:
Add ACC and R
ADDAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
ACC + R Æ dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDIA
Add ACC and Immediate
Syntax:
ADDIA I
Operands:
Operation:
Status Affected:
Description:
0 ≤ I ≤ 255
ACC + I Æ ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
ACC and R Æ dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in
the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0 ≤ I ≤ 255
ACC AND I Æ ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
Rev1.5 May 21, 2010
P.29/FM8PE54/E56
FEELING
FM8PE54/E56
BCR
Clear Bit in R
BCF R, b
0 ≤ R ≤ 63
0 ≤ b ≤ 7
Syntax:
Operands:
Operation:
0 Æ R<b>
Status Affected:
Description:
Cycles:
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
BSR R, b
0 ≤ R ≤ 63
0 ≤ b ≤ 7
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
1 Æ R<b>
None
Set bit ‘b’ in register ‘R’.
1
BTRSC
Test Bit in R, Skip if Clear
BTRSC R, b
0 ≤ R ≤ 63
Syntax:
Operands:
0 ≤ b ≤ 7
Operation:
Status Affected:
Description:
Skip if R<b> = 0
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,
and a NOP is executed instead making this a 2-cycle instruction.
1(2)
Cycles:
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0 ≤ R ≤ 63
0 ≤ b ≤ 7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1(2)
Cycles:
CALL
Subroutine Call
Syntax:
CALL I
Operands:
Operation:
0 ≤ I ≤ 1023
PC +1 Æ Top of Stack;
I Æ PC<9:0>
PCHBUF<2> Æ PC<10>
Status Affected:
Description:
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate
address is loaded into PC bits <9:0>. CALL is a two-cycle instruction.
2
Cycles:
Rev1.5 May 21, 2010
P.30/FM8PE54/E56
FEELING
FM8PE54/E56
CLRA
Clear ACC
CLRA
Syntax:
Operands:
Operation:
None
00h Æ ACC;
1 Æ Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
CLRR R
0 ≤ R ≤ 63
00h Æ R;
1 Æ Z
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Clear Watchdog Timer
CLRWDT
Operands:
Operation:
None
00h Æ WDT;
00h Æ WDT prescaler (if assigned);
1 Æ TO ;
1 Æ PD
Status Affected:
Description:
TO PD
,
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Cycles:
COMR
Complement R
Syntax:
COMR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R Æ dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
DAA
Adjust ACC’s data format from HEX to DEC
Syntax:
DAA
Operands:
Operation:
Status Affected:
Description:
None
ACC(hex) Æ ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition
operation and restored to ACC.
1
Cycles:
Rev1.5 May 21, 2010
P.31/FM8PE54/E56
FEELING
FM8PE54/E56
DAS
Adjust ACC’s data format from HEX to DEC
Syntax:
DAS
Operands:
Operation:
None
ACC(hex) Æ ACC(dec)
Status Affected:
Description:
None
Convert the ACC data from hexadecimal to decimal format after any subtraction operation
and restored to ACC.
1
Cycles:
DECR
Decrement R
Syntax:
Operands:
DECR R, d
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R - 1 Æ dest
Status Affected:
Description:
Z
Decrement register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result is
stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R - 1 Æ dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decremented. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead making it a two-cycle instruction.
Cycles:
1(2)
GOTO
Unconditional Branch
Syntax:
GOTO I
Operands:
Operation:
0 ≤ I ≤ 1023
I Æ PC<9:0>
PCHBUF<2> Æ PC<10>
Status Affected:
Description:
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
GOTO is a two-cycle instruction.
2
Cycles:
INCR
Increment R
Syntax:
Operands:
INCR R, d
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R + 1 Æ dest
Status Affected:
Description:
Z
The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
Rev1.5 May 21, 2010
P.32/FM8PE54/E56
FEELING
FM8PE54/E56
INCRSZ
Syntax:
Increment R, Skip if 0
INCRSZ R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R + 1 Æ dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is placed back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is
executed instead making it a two-cycle instruction.
Cycles:
1(2)
INT
S/W Interrupt
Syntax:
Operands:
Operation:
INT
None
PC + 1 Æ Top of Stack,
002h Æ PC
Status Affected:
Description:
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address
002h is loaded into PC bits <9:0>.
2
Cycles:
IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
ACC or R Æ dest
Status Affected:
Description:
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0 ≤ I ≤ 255
ACC or I Æ ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
IOST
Load IOST Register
Syntax:
IOST R
Operands:
Operation:
Status Affected:
Description:
Cycles:
R = 5 or 6
ACC Æ IOST register R
None
IOST register ‘R’ (R = 5 or 6) is loaded with the contents of the ACC register.
1
Rev1.5 May 21, 2010
P.33/FM8PE54/E56
FEELING
FM8PE54/E56
MOVAR
Move ACC to R
MOVAR R
0 ≤ R ≤ 63
Syntax:
Operands:
Operation:
ACC Æ R
Status Affected:
Description:
Cycles:
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Move Immediate to ACC
MOVIA I
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
0 ≤ I ≤ 255
I Æ ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R Æ dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since
status flag Z is affected.
1
Cycles:
NOP
No Operation
NOP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
OPTION
Load OPTION Register
Syntax:
OPTION
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
ACC Æ OPTION
None
The content of the ACC register is loaded into the OPTION register.
1
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack Æ PC
None
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is
set to 1. This is a two-cycle instruction.
2
Cycles:
Rev1.5 May 21, 2010
P.34/FM8PE54/E56
FEELING
FM8PE54/E56
RETIA
Return with Immediate in ACC
RETIA I
Syntax:
Operands:
Operation:
0 ≤ I ≤ 255
I Æ ACC;
Top of Stack Æ PC
Status Affected:
Description:
None
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a two-cycle instruction.
2
Cycles:
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack Æ PC
None
The program counter is loaded from the top of the stack (the return address). This is a
two-cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R<7> Æ C;
R<6:0> Æ dest<7:1>;
C Æ dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0 the
result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
RRR
Rotate Right R through Carry
Syntax:
Operands:
RRR R, d
0 ≤ R ≤ 63
d∈[0,1]
Operation:
C Æ dest<7>;
R<7:1> Æ dest<6:0>;
R<0> Æ C
Status Affected:
Description:
C
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0 the
result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
Rev1.5 May 21, 2010
P.35/FM8PE54/E56
FEELING
FM8PE54/E56
SLEEP
Enter SLEEP Mode
SLEEP
Syntax:
Operands:
Operation:
None
00h Æ WDT;
00h Æ WDT prescaler;
1 Æ TO ;
0 Æ PD
Status Affected:
Description:
TO PD
,
Time-out status bit ( TO ) is set. The power-down status bit (PD ) is cleared. The WDT and its
prescaler are cleared.
The processor is put into SLEEP mode.
1
Cycles:
SBCAR
Syntax:
Subtract ACC from R with Carry
SBCAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R + ACC + C Æ dest
Status Affected:
Description:
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBAR
Syntax:
Subtract ACC from R
SUBAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R - ACC Æ dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBIA
Subtract ACC from Immediate
Syntax:
SUBIA I
Operands:
Operation:
Status Affected:
Description:
0 ≤ I ≤ 255
I - ACC Æ ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Cycles:
SWAPR
Syntax:
Swap nibbles in R
SWAPR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
R<3:0> Æ dest<7:4>;
R<7:4> Æ dest<3:0>
Status Affected:
Description:
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
Rev1.5 May 21, 2010
P.36/FM8PE54/E56
FEELING
FM8PE54/E56
XORAR
Syntax:
Exclusive OR ACC with R
XORAR R, d
Operands:
0 ≤ R ≤ 63
d∈[0,1]
Operation:
ACC xor R Æ dest
Status Affected:
Description:
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored in
the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0 ≤ I ≤ 255
ACC xor I Æ ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
Rev1.5 May 21, 2010
P.37/FM8PE54/E56
FEELING
4.0 ABSOLUTE MAXIMUM RATINGS
FM8PE54/E56
Ambient Operating Temperature
Store Temperature
0℃ to +70℃
-65℃ to +150℃
0V to +6.0V
DC Supply Voltage (Vdd)
Input Voltage with respect to Ground (Vss)
-0.3V to (Vdd + 0.3)V
5.0 OPERATING CONDITIONS
DC Supply Voltage
+2.3V to +5.5V
Operating Temperature
0℃ to +70℃
Rev1.5 May 21, 2010
P.38/FM8PE54/E56
FEELING
6.0 ELECTRICAL CHARACTERISTICS
FM8PE54/E56
6.1 ELECTRICAL CHARACTERISTICS of FM8PE54E/E56E
Under Operating Conditions, at four clock instruction cycles and WDT & LVDT are disabled
Sym
Description
Conditions
HF mode, Vdd=5V
Min.
1
Typ.
Max.
20
15
4000
1000
15
7
Unit
FHF
X’tal oscillation range
MHz
HF mode, Vdd=3V
1
LF mode, Vdd=5V
32
FLF
X’tal oscillation range
KHZ
MHz
LF mode, Vdd=3V
32
ERC mode, Vdd=5V
DC
DC
DC
DC
0.455
0.455
FERC RC oscillation range
FIRC/ERIC RC oscillation range
ERC mode, Vdd=3V
ERIC mode, external R, Vdd=5V
ERIC mode, external R, Vdd=3V
IRC mode, internal R, Vdd=5V
IRC mode, internal R, Vdd=3V
With schmitter
15
7
MHz
8
8
I/O ports (except IOA4, IOA5), Vdd=5V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=3V
Without schmitter
2.2
4.0
1.7
2.4
VIH
Input high voltage
V
I/O ports (except IOA4, IOA5), Vdd=5V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=3V
With schmitter
2.0
4.0
1.5
2.4
I/O ports (except IOA4, IOA5), Vdd=5V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=3V
Without schmitter
0.8
1.0
0.5
0.6
VIL
Input low voltage
V
I/O ports (except IOA4, IOA5), Vdd=5V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=5V
I/O ports (except IOA4, IOA5), Vdd=3V
IOA4/T0CKI,IOA5/RSTB pins, Vdd=3V
IOH=-5.4mA, Vdd=5V
1.0
1.0
0.6
0.6
VOH
VOL
IPH
Output high voltage
Output low voltage
Pull-high current
Pull-down current
3.6
V
V
IOL=8.7mA, Vdd=5V
0.6
Input pin at Vss, Vdd=5V
-55
40
5
uA
uA
IPD
Input pin at Vdd, Vdd=5V
Vdd=5V
8
2
IWDT
WDT current
uA
Vdd=3V
1
Vdd=3V
19.2
17.3
16.1
1.9
TWDT WDT period
ILVDT LVDT current
mS
uA
Vdd=4V
Vdd=5V
Vdd=5V LVDT = 3.6V
2.9
Rev1.5 May 21, 2010
P.39/FM8PE54/E56
FEELING
FM8PE54/E56
Sym
Description
Conditions
Min.
Typ.
2.1
0.7
5.5
0.2
1.0
0.1
Max.
Unit
Vdd=5V LVDT = 2V
3.2
Vdd=3V LVDT = 2V
1.1
Sleep mode, Vdd=5V, WDT enable
Sleep mode, Vdd=5V, WDT disable
Sleep mode, Vdd=3V, WDT enable
Sleep mode, Vdd=3V, WDT disable
ISB
Power down current
uA
6.2 ELECTRICAL CHARACTERISTICS of FM8PE54/E56
To be defined.
Rev1.5 May 21, 2010
P.40/FM8PE54/E56
FEELING
7.0 PACKAGE DIMENSION
FM8PE54/E56
7.1 18-PIN PDIP 300mil
D
C
TOP E-PIN INDENT £ 0.079
BOTTOM E-PIN INDENT £ 0.118
0.727
e
B
B1
D1
Dimension In Millimeters
Dimension In Inches
Symbols
Min
-
Nom
-
Max
4.57
-
Min
-
Nom
-
Max
0.180
-
A
A1
A2
B
0.13
-
-
0.005
-
-
3.30
0.46
1.52
0.25
22.96
0.56
-
3.56
0.56
1.78
0.33
23.11
0.69
8.26
6.65
-
0.130
0.018
0.060
0.010
0.904
0.022
-
0.140
0.022
0.070
0.013
0.910
0.027
0.325
0.262
-
0.36
1.27
0.20
22.71
0.43
7.62
6.40
-
0.014
0.050
0.008
0.894
0.017
0.300
0.252
-
B1
C
D
D1
E
E1
e
6.50
2.54
-
0.256
0.100
-
L
3.18
-
0.125
-
Rev1.5 May 21, 2010
P.41/FM8PE54/E56
FEELING
FM8PE54/E56
7.2 18-PIN SOP 300mil
View “
A
D
View “
A
7o(4x)
e
B
£
L
Dimension In Millimeters
Dimension In Inches
Symbols
Min
2.36
0.10
-
Nom
2.49
-
Max
2.64
0.30
-
Min
0.093
0.04
-
Nom
0.098
-
Max
0.104
0.012
-
A
A1
A2
B
2.31
0.41
0.23
-
0.091
0.016
0.009
-
0.33
0.18
11.35
7.39
-
0.51
0.28
0.013
0.007
0.447
0.291
-
0.020
0.011
0.463
0.299
-
C
D
E
11.76
7.59
-
7.49
1.27
10.31
0.81
-
0.295
0.050
0.406
0.032
-
e
H
L
10.01
0.38
0°
10.64
1.27
8°
0.394
0.015
0°
0.419
0.050
8°
θ
Rev1.5 May 21, 2010
P.42/FM8PE54/E56
FEELING
FM8PE54/E56
7.3 20-PIN SSOP 209mil
D
View “
A
C
b
e
-H-
GAUGE PLANE
SEATING PLANE
0.004max.
o
£
L
View “
A
L1
Dimension In Millimeters
Symbols
Min
Nom
-
Max
2.00
-
A
A1
A2
b
-
0.05
1.65
0.22
0.09
6.90
7.40
5.00
-
-
1.75
-
1.85
0.38
0.21
7.50
8.20
5.60
-
c
-
D
7.20
7.80
5.30
0.65
0.75
1.25
4o
E
E1
e
L
0.55
-
0o
0.95
-
8o
L1
θo
Rev1.5 May 21, 2010
P.43/FM8PE54/E56
FEELING
ORDERING INFORMATION
FM8PE54/E56
OTP Type MCU
FM8PE54EP
FM8PE54ED
FM8PE54AER
FM8PE56EP
FM8PE56ED
FM8PE56AER
Package Type
PDIP
Pin Count
Package Size
300 mil
18
18
20
18
18
20
SOP
300 mil
SSOP
PDIP
209 mil
300 mil
SOP
300 mil
SSOP
209 mil
Mask Type MCU
FM8PE54P
Package Type
PDIP
Pin Count
Package Size
300 mil
18
18
20
18
18
20
FM8PE54D
FM8PE54AR
FM8PE56P
SOP
300 mil
SSOP
PDIP
209 mil
300 mil
FM8PE56D
FM8PE56AR
SOP
300 mil
SSOP
209 mil
Rev1.5 May 21, 2010
P.44/FM8PE54/E56
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