FP5101 [FEELING]
1 Channel Synchronous PWM Controller;
| 型号： | FP5101 |
| 厂家： | 
Feeling Technology |
| 描述： | 1 Channel Synchronous PWM Controller 射频 微波 |
| 文件： | 总20页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FP5101 / FP5101A
1 Channel Synchronous PWM Controller
General Description
The FP5101 / A is a DC-DC synchronous buck converter controller IC. It comprises high, low side
NMOS gate drivers, boot diode, internal soft start, and over current protection circuit. With +2V to +12V
VIN supply voltage, it is suitable for a wide range of applications.
Features
+12V Vcc Supply Voltage
Feedback Reference Voltage: 0.8V (±2%)
Fixed Frequency Oscillator: 300 / 600KHz
Peak Output Driving Capability: 500mA
Internal Soft Start Function
High-Gain Voltage Mode PWM Control
Over Current Protection by detecting Low-side MOS voltage drop
Package: SOP8 (EP)
Applications
Graphic Card
Telecom and Datacom Applications
High Power DC-DC Regulators
Typical Application Circuit
VIN+2V TO +12V
VCC +12V
VCC
COMP
BOOT
UGATE
PSC
FP5101 / A
SW
FB
VOUT
LGATE
GND
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
1/20
FP5101 / FP5101A
Function Block Diagram
VCC
5V
30uA
0.4V
+
Regulator
-
5V
Reference
BOOT
0.8V
21.6K
Soft-Start
OCP / SCP
0.4V
+
UGATE
SW
-
PWM Compartor
UVLO
+
-
Driver Logic
+
FB
VCC
-
Emor Amp
LGATE
COMP
5V
Oscillator
20µA
-
EN
+
0.8V
GND
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
2/20
FP5101 / FP5101A
Pin Descriptions
SOP-8L (EP)
Name No. I/O
Description
Boosted Power Supply Pin for High Side
MOS Gate Driving
1
2
3
4
8
7
6
5
BOOT
UGATE
GND
SW
COMP
FB
BOOT
1
P
UGATE
GND
LGATE
VCC
2
3
4
5
6
7
8
9
O
P
O
P
I
High Side Gate Driver Output
Ground
LGATE
VCC
Bottom View
Low Side Gate Driver Output
IC Power Supply
EP
FB
Error Amplifier Inverting Input
Error Amplifier Output
Switch Signal Input
COMP
SW
O
I
EP
P
Exposed PAD is GND
1
8
7
6
5
BOOT
UGATE
GND
SW
2
3
4
COMP
FB
LGATE
VCC
Bottom View
EP
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
3/20
FP5101 / FP5101A
Marking Information
SOP-8L (EP)
Halogen Free: Halogen free product indicator
Lot Number: Wafer lot number’s last two digits
For Example: 132386TB 86
Internal ID: Internal Identification Code
Per-Half Month: Production period indicated in half month time unit
For Example: January → A(Front Half Month), B (Last Half Month)
February → C(Front Half Month), D (Last Half Month)
Year: Production year’s last digit
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
4/20
FP5101 / FP5101A
Ordering Information
Part Number
OSC Freq.
Operating Temperature
-40°C ~ +85°C
Package
SOP-8L (EP)
SOP-8L (EP)
MOQ
2500EA
2500EA
Description
Tape & Reel
Tape & Reel
FP5101XR-LF
300KHz
FP5101AXR-LF
600KHz
-40°C ~ +85°C
Absolute Maximum Ratings
Parameter
Power Supply Voltage
BOOT Supply Voltage
BOOT to SW (VBOOT-VSW
SW Voltage
Symbol
Conditions
Min.
Typ.
Max.
Unit
V
VCC
15
30
15
15
VBOOT
-0.6
V
)
V
VSW
-0.6
V
VBOOT
0.3
+
UGATE Voltage
VUGATE
VLGATE
VSW -0.3
V
LGATE Voltage
-0.6
-0.6
VCC + 0.3
V
V
FB, COMP Voltage
6
Allowable Power Dissipation
Thermal Resistance (Junction to
Ambient)
SOP-8L (EP)
1.3
W
θJA
SOP-8L (EP)
SOP-8L (EP)
+50
+10
°C / W
°C / /W
°C
Thermal Resistance (Junction to
Case)
θJC
SOP8 (EP) Lead Temperature
(soldering, 10sec)
+260
IR Re-flow Soldering Curve
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
5/20
FP5101 / FP5101A
Recommended Operating Conditions
Parameter
Symbol
Conditions
Min.
10.8
-40
Typ.
Max.
13.2
+85
Unit
V
Supply Voltage
VCC
12
Operating Temperature
°C
Operating Junction Temperature
-40
+125
°C
DC Electrical Characteristics (VCC= 12V, TA=25°C, unless otherwise specified)
Parameter
Input Supply Current
Standby Current
Symbol
Conditions
Min.
Typ.
Max.
Unit
ISHUTDOWN VCOMP=0V
640
5
µA
Supply Current
ISUPPLY UGATE and LGATE open
mA
Enable / Disable
UVLO Threshold Voltage
Hysteresis Voltage
VUVLO
VHYS
8.8
0.4
9.6
0.8
10.4
1.6
V
V
Oscillator
FP5101
250
500
300
600
1.5
350
700
KHz
KHz
VP-P
Oscillation Frequency
Ramp Amplitude
f
FP5101A
ΔVOSC
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No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
6/20
FP5101 / FP5101A
DC Electrical Characteristics (Cont.)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Reference
Reference Voltage
VFB
0.784
0.8
5
0.816
20
V
mV
%
VFB change with Voltage
VFB change with Temperature
ΔVFB
VCC=10.8V to 13.2V
ΔVFB / ΔT TA = -40°C to 85°C
1
Error Amplifier
Unity Gain Bandwidth Product
Open Loop DC Gain
BW
AVO
15
88
MHz
dB
Gate Drivers
VBOOT
VBOOT
VBOOT
VBOOT
VBOOT
﹣
﹣
﹣
﹣
﹣
VSW=12V
VUGATE=6V
VSW=12V
VUGATE=1V
VSW=12V
Upper Gate Source Current
IUGASR
RUGSR
RUGSN
300
7
mA
Ω
Upper Gate Source Resistance
Upper Gate Sink Resistance
10
8
4
Ω
VUGATE ﹣VSW=1V
Lower Gate Source Current
Lower Gate Source Resistance
Lower Gate Sink Resistance
ILGSR
VCC=12V, VLGATE =6V
VCC=12V, VCC VLGATE=1V
500
4
mA
Ω
﹣
RLGSR
6
4
RLGSN VCC=12V, VLGATE=1V
2
Ω
Protection
FB Under Voltage Protection
Over Current Threshold
Soft-Start Interval
VFBUV
VOC
0.3
-210
2
0.4
-250
3.2
0.5
-290
4.2
V
mV
ms
TSS
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
7/20
FP5101 / FP5101A
TYPICAL CHATACTERISTICS
UGATE Rising Time
UGATE Falling Time
CH1:UGATE CH2:LGATE CH3:SW
CH1:UGATE CH2:LGATE CH3:SW
Load Transient Response
Power On then Trigger OCP
CH3:Vout CH4:IL
CH1:UGATE CH4:IL
OCP then Power On
Power On then Shorted
CH1:UGATE CH4:IL
CH1:UGATE CH4:IL
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
8/20
FP5101 / FP5101A
Shorted then Power On
Power ON
CH1:UGATE CH4:IL
CH1:Vin CH2:HGATE CH3:Vout CH4:IL
Power OFF
CH1:Vin CH2:HGATE CH3:Vout CH4:IL
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
9/20
FP5101 / FP5101A
Function Description
Power On Reset
The FP5101 / A automatically initializes upon input power VCC. The Power-On Reset (POR)
function continually monitors the bias voltage at the VCC pin. The POR threshold level is typically 9.6V
at VCC rising.
VIN Detection
After POR is outstripped, the FP5101 / A continuously generates a 10kHz pulse train with 1μs
pulse width to turn on the upper MOSFET for detecting the existence of VIN. FP5101 / A keeps
monitoring SW pin voltage during the detection period. When the SW voltage crosses 1.5V two times,
VIN existence is recognized and the FP5101 / A initiates its soft start cycle as described in next section.
Soft Start
After the existence of VIN is detected, the soft-start (SS) begins automatically. The feedback
voltage (VFB) is clamped by internal linear ramping up SS voltage during this period, causing PWM
pulse width increasing slowly and thus inducing little surge current. The maximum load current is
available after the soft-start cycle is completed. Soft-start completes when SS voltage exceeds internal
reference voltage (0.8V), the time duration is about 3.2ms.
Over Current Protection
The FP5101 / A senses the current flowing through lower MOSFET for over current protection
(OCP) by sensing the SW pin voltage as shown in the Functional Block Diagram.
A 30μA current source flows through the internal resistor 21.6kΩ to SW pin causing 0.65V voltage
drop across the resistor. OCP is triggered if the voltage at SW pin (drop of lower MOSFET VDS) is lower
than -0.25V when low side MOSFET conducting. Accordingly inductor current threshold for OCP is a
function of conducting resistance of lower MOSFET RDS (ON) as :
0.25V
RDS(ON)
IOCSET
If MOSFET with RDS (ON) = 10mΩ is used, the OCP threshold current is about 25A. Once OCP is
triggered, the FP5101 / A enters hiccup mode and re-soft starts again. The FP5101 / A shuts down
after OCP hiccups twice.
To prevent the over current protection occurs in the normal operating load range, the drift of all
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
10/20
FP5101 / FP5101A
parameters in the above equation should be considered.
-The RDS (ON) of MOSFET varies with temperature and gate to source voltage, the user should
determine the maximum RDS (ON) in manufacturer’s datasheet.
-The parasitic series resistance in PCB’s trace must be considered and added to RDS (ON) in the
above equation.
-The minimum IOCSET (=-0.21V / RDS (ON)) should be considered over the above equation.
Note that the IOCSET is the current flow through the low side MOSFET. IOCSET must be greater than
maximum output current add the half of inductor ripple current. That is,
IL(MAX )
IOCSET IO(MAX )
2
LGATE>425ns
LGATE=425ns
LGATE<425ns
LGATE<<425ns
To avoid the gate transition noise and ringing on the SW pin, the actual monitoring of the
bottom-side MOSFET's on-resistance starts 200ns (nominal) after the LGATE rising edge. The
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
11/20
FP5101 / FP5101A
monitoring ends when the LGATE goes low. The OCP can be detected anywhere within the above
window. If the regulator is running at high UGATE duty cycles (around 75% for 600kHz or 87% for
300kHz operation), then the LGATE pulse width may be not wide enough for the OCP to properly
sample the VSW. For those cases, if the LGATE is too narrow (or not there at all) for 3 consecutive
pulses, then the third pulse will be stretched and/or inserted to the 425ns minimum width. This allows
for OCP monitoring every three pulses under this kind of condition. This can introduce a small
pulse-width error on the output voltage, which will be corrected on the next pulse; and the output ripple
voltage will have an unusual 3-clock pattern, which may look like jitter.
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
12/20
FP5101 / FP5101A
Application Information
Frequency Compensation
The FP5101 / A is a voltage-mode controller for a synchronous-rectified buck converter. Figure 1
highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the reference voltage level. The error amplifier (ERROR AMP) output (VCOMP) is
compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave
with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and
COUT).
The modulator transfer function is the small-signal transfer function of VOUT / VCOMP. This function
is dominated by a DC gain and the output filter (LOUT and COUT), with a double-pole break frequency at
FLC and a zero at FESR. The DC gain of the modulator is the input voltage (VIN) divided by the
peak-to-peak oscillator voltage (ΔVOSC). The following equations define the modulator break
frequencies as a function of the output LC filter:
1
FLC
2 LOUT COUT
The ESR zero is contributed by the ESR associated with the output capacitance. Note that this
requires the output capacitor should have enough ESR to satisfy stability requirements. The ESR zero
of the output capacitor is expressed as following
1
FESR
2 COUT ESR
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
13/20
FP5101 / FP5101A
VIN
DRIVER
DRIVER
OS
C
PWM
COMPARATO
LOUT
VOUT
ΔVOSC
R
_
+
COUT
ESR
ZFB
Vcomp
_
+
ZIN
ERROR
AMP
VREF
DETAILED COMPENSATION COMPONENTS
VOUT
ZFB
C1
ZIN
C2
R2
R3
C3
R1
_
FB
COMP
+
VREF
Figure 1 Voltage-mode Buck Converter Compensation Design
The compensation network consists of the error amplifier (internal to the FP5101 / A) and the
impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed-loop
transfer function with the highest 0dB crossing frequency (F0dB) and adequate phase margin. Phase
margin is the difference between the closed loop phase at F0dB and 180 degrees. The equations below
relate the compensation network’s poles, zeros, and gain to the components (R1, R2, R3, C1, C2, and
C3), shown in Figure 1.
1
FZ1
2R2C2
1
C1C2
FP1
2R2(
)
C1 C2
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No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
14/20
FP5101 / FP5101A
1
FZ2
2C3 (R1 R3 )
1
FP2
2R3C3
Use the following steps to locate the poles and zeros of the compensation network.
1. Pick gain (R2 / R1) for the desired converter bandwidth.
Choose a value for R1, usually between 1K and 10K.
Select the desired zero crossover frequency
FO : (1/5 ~1/10)FS F
ESR
Use the following equation to calculate R2:
VOSC FO
R2
R1
V
F
LC
IN
2. Place the first zero below the filter’s double pole (~75% FLC).
FZ1 0.75F
LC
Calculate the C2 by the equation:
1
C2
2R2 FLC 0.75
3. Place the first pole at the ESR zero.
F
P1 F
ESR
Calculate the C1 by the equation:
C2
C1
2R2 C2 FESR 1
4. Place the second zero at filter’s double pole.
5. Place the second pole at half the switching frequency.
F
0.5FS
P2
FZ2 F
LC
Combine above two equations will get the following component equations
R1
R3
FS
1
2F
LC
1
C3
R3 FS
6. Check the gain against the error amplifier’s open loop gain.
7. Estimate phase margin. Repeat if necessary.
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
15/20
FP5101 / FP5101A
Figure 2 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual
modulator gain has a high gain peak due to the high Q factor of the output filter and is not shown in
Figure 2. Using the above guidelines should give a compensation gain similar to the red curve plotted.
The open-loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2
with the capabilities of the error amplifier. The closed-loop gain is constructed on the graph of Figure 2
by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiply the
modulator transfer function by the compensation transfer function and plotting the gain. The
compensation gain uses external impedance networks ZFB and ZIN to provide a stable high bandwidth
overall loop. A stable control loop has a gain crossing with a –20dB/decade slope and a phase margin
greater than 45°. Include worst-case component variations when determining phase margin.
FZ1=0.75FLC
FZ2=FLC
FP1=FESR
FP2=0.5FSW
ERROR AMP
DC GAIN
COMPENSATION
GAIN
-20dB/DEC
MODULATOR
& FILTER GAIN
0
CLOSED LOOP GAIN
BANDWIDTH
FLC
FESR
FREQUENCY(Hz)
Figure 2. Asymptotic Bode Plot of Converter Gain
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
16/20
FP5101 / FP5101A
Component Selection
Input capacitor Selection
The voltage rating at maximum ambient temperature should be 1.25 to 1.5 times the maximum
input voltage. More conservative approaches can bring the voltage rating up to 2 times the maximum
input voltage. High frequency decoupling, which is highly recommended, is implemented through the
use of ceramic capacitors in parallel with the bulk capacitor filtering.
In switch mode, the input current is discontinuous in a buck converter. The source current of the
high-side MOSFET is a square wave. To prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The RMS value of input capacitor current can be
calculated by:
VO
VIN
VO
VIN
IRMS IO_MAX
1
It can be seen that when VO is half of VIN, CIN is under the worst current stress. The worst current
stress on CIN is IO_MAX/2.
Inductor Selection
The value of the inductor is selected based on the desired ripple current. Large inductance gives
low inductor ripple current and small inductance result in high ripple current. However, the larger value
inductor has a larger physical size, higher series resistance, and/or lower saturation current. In
experience, the value is to allow the peak-to-peak ripple current in the inductor to be 10%~20%
maximum load current. The inductance value can be calculated by:
(V VO ) VO
(V VO )
2(10% ~ 20%)IO
VO
IN
IN
L
f IL
V
f
V
IN
IN
The inductor ripple current can be calculated by:
VO
VO
VIN
IL
1
f L
Choose an inductor that does not saturate under the worst-case load conditions even at the
highest operating temperature. (The load current plus half the peak-to-peak inductor ripple current).
The peak Inductor current is:
IL
2
IL _PEAK IO
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No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
17/20
FP5101 / FP5101A
MOSFET Selection
There are three major aspects of power loss that are associated with the MOSFET. These are
conduction losses, switching losses, and gate drive power losses.
PD(MOSFET) Pconduction Pswitching Pgate
1
PD(HIigh _MOSFET) IO2 RDS(ON) D VIN IO (tr tf ) fs QGate VGS fs
2
1
PD(HIigh _MOSFET) IO2 RDS(ON) (1 D) Vf IO (tr tf ) fs QGate VGS fs
2
V
IN = Input Voltage for
Vf = Lower side turn on VDS
O = Output Current
I
D = Duty Cycle
tr = MOSFET rising time
tf = MOSFET rising time
fs = Switching Frequency
QGate = MOSFET gate charge
VGS = MOSFET gate voltage
Output Capacitor Selection
The output capacitor is required to maintain the DC output voltage. Low ESR capacitors are
preferred to keep the output voltage ripple low. In a buck converter circuit, output ripple voltage is
determined by inductor value, switching frequency, output capacitor value and ESR. The output ripple
is determined by:
1
VO IL ESRCOUT
8 f COUT
Where f = operating frequency, COUT= output capacitance and ΔIL = ripple current in the inductor.
For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases
with input voltage.
The most commonly used choice for output bulk capacitors is aluminum electrolytic capacitors
because of their low cost and low ESR. Due to the capacitor ESR varies with frequency, user should
consider the ESR value rated at the PWM frequency.
The output capacitance should also include a number of small capacitance value ceramic
capacitors placed as close as possible to the chip; 0.1μF and 0.01μF are recommended values.
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
18/20
FP5101 / FP5101A
PC Board Layout Checklist
The switching power converter layout is critical to achieve low power losses, clean waveforms,
and stable operation. It needs careful attention. Following are specific recommendations for good
board layout:
1. Keep the high current traces and load connections as short as possible.
2. Use thick copper plated PCB whenever possible to achieve higher efficiency.
3. Keep the loop area between the SW node, low-side MOSFET, Inductor, and the output
capacitor as small as possible.
4. Route high DV / Dt signals, such as SW node, away from the error amplifier input/output pins.
Keep both the high DV / Dt signals and the error amplifier input/output signals as short as
possible.
5. Place VCC ceramic decoupling capacitors very close to VCC pin.
6. All input signals are referenced with respect to GND pin. Dedicate large copper area of the
PCB for a GND plane.
7. Minimize GND loops in the layout to avoid EMI-related issues.
8. Use wide traces for the lower gate drive to keep the drive impedances low.
9. Use wide land areas with appropriate thermal vias to effectively remove heat from the
MOSFETs.
10. Preserve the snubber circuit to minimize high frequency ringing at SW node for EMI issues.
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
19/20
FP5101 / FP5101A
Package Outline
SOP-8L (EP)
Symbols
Min. (mm)
1.346
Max. (mm)
A
A1
A2
D
1.752
0.152
1.498
4.978
3.987
6.197
1.270
8°
0.050
4.800
3.810
5.791
0.406
0°
E
H
L
θ°
UNIT: mm
Exposed PAD Dimensions:
Symbols
Min. (mm)
Max. (mm)
E1
D1
2.184 REF
2.971 REF
Note:
1. Package dimensions are in compliance with JEDEC outline: MS-012 AA.
2. Dimension ”D” does not include molding flash, protrusions or gate burrs.
3. Dimension “E” does not include inter-lead flash or protrusions.
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No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Website: http://www.feeling-tech.com.tw
Rev. 0.64
20/20
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