CMP0817BA0-F70I [FIDELIX]
512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM; 512K ×16位超低功耗和低电压全CMOS RAM
| 型号： | CMP0817BA0-F70I |
| 厂家： | 
FIDELIX |
| 描述： | 512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM |
| 文件： | 总10页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMP0817BA0-I
Document Title
CMOS LPRAM
512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM
Revision History
Revision
History
No.
Draft date
Remark
nd
0.0
0.1
0.2
0.3
Initial Draft
May. 2 , 2004
Final
Final
Final
Final
th
Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions
Removed 60ns descriptions
Oct. 26 , 2005
nd
Aug. 22 , 2006
th
Added Power Up Sequence
Sep. 6 , 2006
Revision 0.3
Sep. 2006
1
CMP0817BA0-I
CMOS LPRAM
512K x 16 bit Super Low Power and Low Voltage Full CMOS RAM
FEATURES
• Process Technology : Full CMOS
• Organization : 512K x 16
• Power Supply Voltage : 2.7~3.3V
• Three state output and TTL Compatible
• Package Type : 48-FBGA-6.00x8.00 mm
2
• Separated I/O power(VCCQ) & Core Power(VCC)
• Easy memory expansion with /CS1, CS2, and /OE features
• Automatic power-down when deselected
PRODUCT FAMILY
Power Dissipation
Operating
Voltage (V)
ISB1
ICC1
ICC2
Operating
Speed
Product Family
(CMOS Standby
Current)
Temperature
f = 1MHz
f = fmax
Min. Typ. Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
Industrial
70ns
1.5mA
3mA
12mA
20mA
30uA
70uA
CMP0817BA0-F70I
2.7 3.0 3.3
(-40~85’C)
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C.
2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
Precharge circuit.
Clk gen.
/LB
/OE
/UB
A0
A3
A1
A4
A2
CS2
I/O1
A
B
I/O9
/CS
VCC
VSS
I/O10
VSS
I/O11
I/O12
A6
A7
I/O2
I/O4
I/O5
I/O6
I/O3
VCC
VSS
I/O7
I/O8
NC
A5
C
D
E
F
Memory array
Row
Addresses
Row
select
A17
A16
A15
A13
A10
VCCQ
I/O15
I/O16
A18
I/O13 DNU
I/O14 A14
I/O Circuit
Data
cont
I/O1~I/O8
NC
A8
A12
A9
/WE
A11
Column select
G
H
Data
cont
I/O9~I/O16
Data
cont
48-FBGA : Top View(Ball Down)
Name
CS2
Function
Name
VCC
VCCQ
VSS
/UB
Function
Core Power
Column Addresses
Chip Select Input
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
/CS1
/OE
I/O Power
/CS1
CS2
/OE
/WE
/UB
/LB
Ground
/WE
Upper Byte(I/O9~16)
Lower Byte(I/O 1~8)
Do Not Use
Control Logic
A0~A18
/LB
I/O1~I/O16 Data Inputs/Outputs
NC No Connection
DNU
Revision 0.3
Sep. 2006
2
CMP0817BA0-I
CMOS LPRAM
PRODUCT LIST
Industrial Temperature Products(-40~85’C)
Part Name
Function
48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)
CMP0817BA0-F70I
1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
FUNCTIONAL DESCRIPTION
/CS1
H
CS2
H
/OE
X1)
X1)
X1)
H
/WE
X1)
X1)
X1)
H
/LB
X1)
X1)
H
/UB
X1)
X1)
H
I/O1-8
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
I/O9-16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Mode
Power
Standby
Standby
Standby
Active
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
X1)
X1)
L
H
H
L
X1)
L
L
L
H
H
H
X1)
L
Active
H
Active
L
H
L
H
L
High-Z
Dout
Active
L
L
Dout
Active
H
L
H
Din
High-Z
Din
Lower Byte Write
Upper Byte Write
Word Write
Active
X1)
H
L
High-Z
Din
Active
L
L
Din
Active
1. X means don’t care.(Must be low or high state)
1)
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Ratings
-0.2 to Vcc+0.3V
-0.2 to 3.6
1.0
Unit
V
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
VIN, VOUT
Vcc
V
PD
W
’C
’C
Storage temperature
TSTG
TA
-65 to 150
-40 to 85
Operating Temperature
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industrial periods
may affect reliability.
1)
RECOMMENDED DC OPERATING CONDITIONS
CMP0817BA0
Item
Symbol
Unit
Min
2.7
Max
3.3
Min
2.7
Max
3.3
Min
2.7
Max
3.3
Supply voltage
VCC
VCCQ
VSS
VIH
V
V
V
V
V
I/O operating voltage (VCCQ ≤ VCC)
Ground
2.7
3.3
2.25
2.75
1.65
1.95
0
0
0
0
0
0
Input high voltage
0.8VCCQ
-0.23)
VCC+0.22)
0.8VCCQ
-0.23)
VCC+0.22)
0.8VCCQ
-0.23)
VCC+0.22)
Input low voltage
VIL
0.2VCCQ
0.2VCCQ
0.2VCCQ
Note :
1.TA=-40 to 85’C, otherwise specified.
2. Overshoot : Vcc+1.0V in case of pulse width≤20ns.
3. Undershoot : -1.0V in case of pulse width≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
Revision 0.3
Sep. 2006
3
CMP0817BA0-I
CMOS LPRAM
1)
CAPACITANCE (f=1MHz , TA=25’C)
Item
Symbol
Test Condition
VIN=0V
Min
Max
Unit
pF
Input capacitance
CIN
-
-
8
8
Input/Output capacitance
CIO
VIO=0V
pF
1. Capacitance is sampled, not 100% tested.
DC AND OPERATING CHARACTERISTICS
Item
Symbol
Test Conditions
Min
-1
Typ
Max
1
Unit
uA
Input leakage current
Output leakage current
ILI
VIN=VSS to VCC
-
-
ILO
-1
1
uA
/CS=VIH, CS2=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCC
Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, CS2=VIH,
VIN≤0.2V or VIN≥VCC-0.2V
ICC1
ICC2
-
-
1.5
15
3
mA
mA
Average operating current
Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, CS2=VIH,
VIN=VIL or VIH
25
Output low voltage
VOL
VOH
ISB
IOL=0.5mA
0.2VCCQ
V
V
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
IOH=-0.5mA
0.8VCCQ
/CS=VIH, CS2=VIH, Other inputs=VIH or VIL
/CS≥VCC-0.2V, CS2≤0.2V, Other inputs=0~VCC
-
-
-
-
0.3
70
mA
uA
ISB1
Revision 0.3
Sep. 2006
4
CMP0817BA0-I
CMOS LPRAM
AC OPERATING CONDITIONS
TEST CONDITIONS(Test Load and Input/Output Reference)
1TTL
Input pulse level : 0.2 to VCC-0.2V
30pf
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : CL=30pF+1TTL
AC CHARACTERISTICS(VCC=2.7V~3.3V, Industrial product : TA=-40 to 85’C)
70ns
Parameter List
Symbol
Units
Min
70
-
Max
80k
70
70
25
70
-
Read Cycle Time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select to Output
tCO
tOE
tBA
-
Output Enable to Valid Output
-
/UB, /LB Access Time
-
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High- Z Output
/UB, /LB Disable to High- Z Output
Output Disable to High- Z Output
Output Hold from Address Change
Write Cycle Time
tLZ
10
10
5
Read
tBLZ
tOLZ
tHZ
-
-
0
5
tBHZ
tOHZ
tOH
tWC
0
5
0
5
5
-
70
80k
Chip Select to End of Write
Address Set-up Time
tCW
tAS
60
0
-
-
-
-
-
-
5
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write Pulse Width
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
60
60
50
0
Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
0
20
0
Data Hold from Write Time
End Write to Output Low-Z
tOW
tCP
5
/CS High Pulse Width1)
10
1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High.
Revision 0.3
Sep. 2006
5
CMP0817BA0-I
CMOS LPRAM
Power Up Sequence
1. Apply Power
2. Maintain stable power for a minimum of 200us with /CS=VIH
Standby Mode State machines
Power On
/CS=VIH
Wait
Initial State
min.200us
/CS=VIL, /ZZ=VIH
/UB or/and /LB=VIL
Active
Mode
/CS=VIH
(or/and /UB=/LB=VIH
/ZZ=VIH
/CS=VIlL
/ZZ=VIH
)
Standby Mode
Standby Mode Characteristics
Mode
Memory Cell Data
Valid
Standby Current(uA)
Wait Time(us)
Standby
70 (ISB1)
0
Revision 0.3
Sep. 2006
6
CMP0817BA0-I
CMOS LPRAM
READ CYCLE (1) (Address controlled,/CS1=/OE=VIL, CS2=/WE=VIH, /UB or/and /LB=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
READ CYCLE (2) (CS2=/WE=VIH)
tRC
Address
tOH
tAA
tCO
/CS1
CS2
tHZ
tBA
/UB, /LB
/OE
tBHZ
tOE
tOLZ
tBLZ
tOHZ
tLZ
High-Z
Data Out
Data Valid
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device
to device interconnection.
3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
Revision 0.3
Sep. 2006
7
CMP0817BA0-I
CMOS LPRAM
WRITE CYCLE (1) (/WE controlled)
tWC
Address
tCW(2)
tWR(4)
/CS1
CS2
tAW
tBW
/UB, /LB
/WE
tWP(1)
tAS(3)
High-Z
tDW
Data Valid
tDH
Data in
High-Z
tWHZ
tOW
Data Out
Data Undefined
WRITE CYCLE (2) (/CS1 controlled)
tWC
Address
tWR(4)
tAS(3)
tCW(2)
/CS1
CS2
tAW
tBW
/UB, /LB
/WE
tWP(1)
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
WRITE CYCLE (3) (CS2 controlled)
tWC
Address
tWR(4)
tCW(2)
/CS1
CS2
tAW
tBW
/UB, /LB
tAS(3)
tWP(1)
/WE
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
Revision 0.3
Sep. 2006
8
CMP0817BA0-I
CMOS LPRAM
WRITE CYCLE (4) (/UB, /LB controlled)
tWC
Address
tWR(4)
tCW(2)
/CS1
CS2
tAW
tBW
/UB, /LB
/WE
tAS(3)
tWP(1)
tDW
Data Valid
tDH
Data in
Data Out
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low /CS and /WE. A write begins when /CS goes low and /WE goes low with
asserting /UB or /LB for single byte operation or simultaneously asserting /UB and /LB for double byte operation. A write
ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the /CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high.
5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 80us.
Revision 0.3
Sep. 2006
9
CMP0817BA0-I
CMOS LPRAM
PACKAGE DIMENSION
Unit : millimeters
48 BALL FINE PITCH BGA(0.75mm ball pitch)
Top View
Bottom View
A1 INDEX MARK
B
B1
B
0.05
0.05
6
5
4
3
2
1
A
B
C
D
#A1
E
F
G
H
B/2
Side View
D
Detail A
A
Y
C
-
A
Min
-
Typ
0.75
6.00
3.75
8.00
Max
-
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerance are +/-0.050 unless
otherwise specified.
B
5.90
-
6.10
-
B1
C
7.90
8.10
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
C1
D
-
5.25
0.35
1.00
0.75
0.25
-
-
0.30
0.40
-
E
-
E1
E2
Y
-
0.20
-
-
0.30
0.08
Revision 0.3
Sep. 2006
10
相关型号：
CMP08BZ/883
Comparator, 1 Func, 3000uV Offset-Max, 6.5ns Response Time, BIPolar, CDIP8, CERDIP-8
ADI
©2020 ICPDF网 联系我们和版权申明