FT29F010B90FLF-S [FORCE]

1 Megabit (128 K x 8-bit) Uniform Sector Flash Memory CMOS 5.0 Volt-only;


型号：	FT29F010B90FLF-S
厂家：	Force Technologies
描述：	1 Megabit (128 K x 8-bit) Uniform Sector Flash Memory CMOS 5.0 Volt-only
文件：	总30页 (文件大小：2137K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FT29F010B

Uniform Sector Flash Memory

CMOS 5.0 Volt-only

1 Megabit (128 K x 8-bit)

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Embedded Algorithms

— 5.0 V ꢀ0% for read, erase, and program operations

— Simplifies system-level power requirements

— Embedded Erase algorithm automatically

pre-programs and erases the chip or any

combination of designated sector

■ Manufactured on 0.32 µm process technology

— Embedded Program algorithm automatically

programs and verifies data at specified address

— Compatible with FT29F0ꢀ0 and FT29F0ꢀ0A

device

■ Erase Suspend/Resume

■ High performance

— Supports reading data from a sector not

being erased

— 90 ns maximum access time

■ Low power consumption

■ Minimum 1 million erase cycles guaranteed per

— ꢀ2 mA typical active read current

— 30 mA typical program/erase current

— <ꢀ µA typical standby current

sector

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

■ Flexible sector architecture

— Eight ꢀ6 Kbyte sectors

— 32-pin LCC/CLCC

— 32-pin FP/FFP

— Any combination of sectors can be erased

— Supports full chip erase

— 32-pin CDIP/CSOJ

—

32-pin PLCC

■ Sector protection

— Hardware-based feature that disables/re-

enables program and erase operations in any

combination of sectors

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash

— Sector protection/unprotection can be

implemented using standard PROM

programming equipment

— Superior inadvertent write protection

■ Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

Rev 2

1/30

2014

GENERAL DESCRIPTION

The FT29F0ꢀ0B is a ꢀ Mbit, 5.0 Volt-only Flash

memory organised as ꢀ3ꢀ,072 bytes. The FT29F0ꢀ0B

is offered in 32-pin various packages.

The byte-wide data appears on DQ0-DQ7. The de-

vice is designed to be programmed in-system with the

automatically times the program pulse widths and

verifies proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This invokes the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

standard system 5.0 Volt V supply. A ꢀ2.0 volt V is not

required for program or erase operations. The device can

also be programmed or erased in standard EPROM

programmers.

This device is manufactured using 0.32 µm process

technology.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

The standard device offers access times of

90, and ꢀ20 ns, allowing high-speed microprocessors

to operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is erased

when shipped from the factory.

The device requires only a single 5.0 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The hardware data protection measures include a

detector automatically inhibits write operations

low V

during power transitions. The hardware sector protec-

tion feature disables both program and erase operations

in any combination of the sectors of memory, and is im-

plemented using standard EPROM programmers.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode.

The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte at a

time using the EPROM programming mechanism of hot

electron injection.

Device programming occurs by executing the program

command sequence. This invokes the Embedded Pro-

gram algorithm—an internal algorithm that

Rev 2

2/30

2014

PRODUCT SELECTOR GUIDE

Family Part Number FT29F010B

Speed Option

= 5.0 V ± ꢀ0%

-90

-120

ꢀ20

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM

DQ0–DQ7

Erase Voltage

Generator

Input/Output

Buffers

State

Control

WE#

Command

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

Detector

Timer

Cell Matrix

X-Decoder

A0–Aꢀ6

Rev 2

3/30

2014

CONNECTION DIAGRAMS

A16

A15

A12

WE#

31 30

1 32

A14

A13

A14

A13

LCC/CLCC

A11

OE#

A10

CE#

DQ7

DQ6

A11

OE#

A10

CE#

DQ7

DIL

DQ0

16 17

19 20

DQ0

DQ1

DQ2

DQ5

DQ4

DQ3

A11

A13

A14

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

WE#

Standard TSOP

A16

A15

A12

DQ2

DQ1

DQ0

Rev 2

4/30

2014

32 lead FP Formed

ꢀ.ꢀꢁ (0.1ꢀ2)

MAX

20.8ꢀ (0.820)

0.2ꢁ (0.010)

0.1ꢁ (0.006)

TYP

1.27 (0.0ꢁ0) TYP

10.41 (0.410)

0.1ꢀ (0.00ꢁ)

1ꢀ.47 (0.ꢁꢀ0)

0.1ꢀ (0.00ꢁ)

0.4ꢀ (0.017)

0.0ꢁ (0.002)

1.27 (0.0ꢁ0) TYP

19.0ꢁ (0.7ꢁ0) TYP

0.6ꢀ (0.02ꢁ) TYP

0°/ -4°

1.ꢁ2 (0.060) TYP

32 pin CDIL

42.4 (1.670) 0.4 (0.016)

15.04 (0.592)

0.3 (0.012)

4.34 (0.171) 0.79 (0.031)

3.2 (0.125) MIN

PIN 1 IDENTIFIER

0.25 (0.010)

0.05 (0.002)

0.84 (0.033)

0.4 (0.014)

15.25 (0.600)

0.25 (0.010)

2.5 (0.100)

TYP

1.27 (0.050)

0.1 (0.005)

0.46 (0.018)

0.05 (0.002)

Rev 2

5/30

2014

21.1 (0.830) 0.25 (0.010)

3.96 (0.156) MAX

0.89 (0.035)

Radius TYP

0.2 (0.008)

0.05 (0.002)

11.3 (0.442)

0.30 (0.012)

9.55 (0.376) 0.25 (0.010)

1.27 (0.050) 0.25 (0.010)

PIN 1 IDENTIFIER

1.27 (0.050) TYP

19.1 (0.750) TYP

32 pin CSOJ

20.83 (0.820)

0.25 (0.010)

PIN 1

2.60 (0.102) MAX

IDENTIFIER

10.41 (0.410)

0.13 (0.005)

10.16 (0.400)

0.51 (0.020)

0.43 (0.017)

0.05 (0.002)

1.27 (0.050) TYP

19.05 (0.750) TYP

0.127 (0.005)

+ 0.05 (0.002)

– 0.025 (0.001)

32 lead FP

Rev 2

6/30

2014

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory

location. The register is composed of latches that store

the commands, along with the address and data infor-

mation needed to execute the command. The contents

of the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1.FT29F010B Device Bus Operations

Addresses

(Note 1)

Operation

CE#

OE#

WE#

DQ0–DQ7

Read

OUT

Write

Standby

0.5 V

High-Z

Output Disable

Hardware Reset

Legend:

L = Logic Low = V , H = Logic High = V , V = ꢀ2.0 ± ±0.5 V, X = Don’t Care, A = Addresses In, D = Data In, D = Data Out

IH ID

OUT

Notes:

ꢀ. Addresses are Aꢀ6:A0.

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-

tection/Unprotection” section.

Requirements for Reading Array Data

Writing Commands/Command Sequences

To read array data from the outputs, the system must

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

drive the CE# and OE# pins to V . CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

CE# to V , and OE# to V .

remain at V .

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the

entire chip.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid addresses

on the device address inputs produce valid data on the

device data outputs. The device remains enabled for

read access until the command register contents are

altered.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. I

in the DC Characteristics

table represents the active current specification for

reading array data.

CCꢀ

in the DC Characteristics table represents the ac-

CC2

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Rev 2

7/30

2014

The device enters the CMOS standby mode when the

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

CE# pin is held at V_CC± 0.5 V. (Note that this is a more

restricted voltage range than V .) The device enters

the TTL standby mode when CE# is held at V . The

bits on DQ7–DQ0. Standard read cycle timings and I

device requires the standard access time (t ) before it

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section in the appropriate data sheet for timing

diagrams.

is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Standby Mode

in the DC Characteristics tables represents the

CC3

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

standby current specification.

Output Disable Mode

When the OE# input is at V , output from the device is

disabled. The output pins are placed in the high imped-

ance state.

Table 2.FT29F010B Sector Addresses Table

A15 A14

Sector

SA0

SAꢀ

SA2

SA3

SA4

SA5

SA6

SA7

A16

Address Range

00000h-03FFFh

04000h-07FFFh

08000h-0BFFFh

0C000h-0FFFFh

ꢀ0000h-ꢀ3FFFh

ꢀ4000h-ꢀ7FFFh

ꢀ8000h-ꢀBFFFh

ꢀC000h-ꢀFFFFh

ꢀ

Note: All sectors are ꢀ6 Kbytes in size.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

the appropriate highest order address bits. Refer to the

corresponding Sector Address Tables. The Command

Definitions table shows the remaining address bits that

are don’t care. When all necessary bits have been set

as required, the programming equipment may then

read the corresponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

When using programming equipment, the autoselect

mode requires V on address pin A9. Address pins A6,

tions table. This method does not require V . See

Aꢀ, and A0 must be as shown in Autoselect Codes

(High Voltage Method) table. In addition, when verifying

sector protection, the sector address must appear on

“Command Definitions” for details on using the autose-

lect mode.

Rev 2

8/30

2014

Table 3. FT29F010B Autoselect Codes (High Voltage Method)

A16 A13

to to

CE# OE# WE# A14 A10 A9

DQ7

DQ0

Description

Manufacturer ID: Spansion

Device ID: FT29F010B

VID

01h

20h

01h

(protected)

Sector Protection Verification

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

gramming, which might otherwise be caused by

spurious system level signals during V power-up

and power-down transitions, or from system noise.

Sector Protection/Unprotection

The hardware sector protection feature dis ables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors.

Low V Write Inhibit

When V

is less than V

, the device does not ac-

LKO

cept any write cycles. This protects data during V

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

Sector protection/unprotection must be implemented

using programming equipment. The pr ocedure re-

device resets. Subsequent writes are ignored until V

quires a high voltage (V ) on address pin A9 and the

is greater than V

. The system must provide the

control pins.

LKO

proper signals to the control pins to prevent uninten-

The device is shipped with all sectors unprotected.

tional writes when V is greater than V

LKO

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Hardware Data Protection

Logical Inhibit

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

Write cycles are inhibited by holding any one of OE# =

V , CE# = V or WE# = V . To initiate a write cycle,

CE# and WE# must be a lo gical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V and OE# = V during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

Rev 2

9/30

2014

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device

operations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

mers and requires V on address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX0ꢀh returns

the device code. A read cycle containing a sector ad-

dress (SA) and the address 02h in returns 0ꢀh if that

sector is protected, or 00h if it is unprotected. Refer to

the Sector Address tables for valid sector addresses.

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verify the pro-

grammed cell margin. The Command Definitions take

shows the address and data requirements for the byte

program command sequence.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by using

DQ7or DQ6. See “Write Operation Status” for informa-

tion on these status bits.

The reset command may be written between the se-

quence cycles in a program command sequence

before programming begins. This resets the device to

reading array data. Once programming begins, how-

ever, the device ignores reset commands until the

operation is complete.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “ꢀ”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “ꢀ”.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data.

Rev 2

10/30

2014

Embedded Erase algorithm is complete, the device re-

turns to reading array data and addresses are no

longer latched.

START

Figure 2 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Write Program

Command Sequence

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Increment Address

Last Address?

Yes

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The in-

terrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional sec-

tor erase commands can be assumed to be less than

50 µs, the system need not monitor DQ3. Any com-

mand during the time-out period resets the device

to reading array data. The system must rewrite the

command sequence and any additional sector ad-

dresses and commands.

Programming

Completed

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 1. Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation has begun, all other

commands are ignored.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7 or DQ6. Refer

to “Write Operation Status” for information on these

status bits.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored.

The system can determine the status of the erase op-

eration by using DQ7 or DQ6. See “Write Operation

Status” for information on these status bits. When the

Rev 2

11/30

2014

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase

Suspend command.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

START

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

Write Erase

Command Sequence

Data Poll

from System

After the erase operation has been suspended, the

system can read array data from any sector not se-

lected for erasure. (The device “erase suspends” all

sectors selected for erasure.) Normal read and write

timings and command definitions apply. Reading at any

address within erase-suspended sectors produces sta-

tus data on DQ7–DQ0. The system can use DQ7 to

determine if a sector is actively erasing or is erase-sus-

pended. See “Write Operation Status” for information

on these status bits.

Embedded

Erase

algorithm

in progress

Data = FFh?

Yes

Erasure Completed

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more

information.

Notes:

ꢀ. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

Figure 2. Erase Operation

Rev 2

12/30

2014

Command Definitions

Table 4.FT29F010B Command Definitions

Bus Cycles (Notes 2-3)

Third Fourth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

RA RD

XXXX F0

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Read (Note 4)

Reset (Note 5)

Reset (Note 6)

Manufacturer ID

ꢀ

555

2AA

555

X00

X0ꢀ

0ꢀ

Device ID

Autoselect

(Note 7)

Sector Protect Verify

(Note 8)

(SA)

X02

555

2AA

555

0ꢀ

Program

ꢀ

555

XXX

2AA

555

Chip Erase

2AA

555

ꢀ0

Sector Erase

Erase Suspend (Note 9)

Erase Resume (Note ꢀ0)

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits Aꢀ6–Aꢀ4 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

ꢀ. See Table ꢀ for description of bus operations.

7. The fourth cycle of the autoselect command sequence is a

read operation.

2. All values are in hexadecimal.

8. The data is 00h for an unprotected sector and 0ꢀh for a

protected sector. See “Autoselect Command Sequence” for

more information.

3. Except when reading array or autoselect data, all command

bus cycles are write operations.

4. No unlock or command cycles required when reading array

data.

9. The system may read in non-erasing sectors, or enter the

autoselect mode, when in the Erase Suspend mode. The

Erase Suspend command is valid only during a sector erase

operation.

5. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

ꢀ0. The Erase Resume command is valid only during the Erase

Suspend mode.

6. The device accepts the three-cycle reset command

sequence for backward compatibility.

Rev 2

13/30

2014

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ3, DQ5, DQ6, and DQ7.

Table 5 and the following subsections describe the

functions of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

Table 5 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Algorithm is in progress or

completed. Data# Polling is valid after the rising edge

of the final WE# pulse in the program or erase com-

mand sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. When the Embedded Program

algorithm is complete, the device outputs the datum

programmed to DQ7. The system must provide the pro-

gram address to read valid status information on DQ7.

If a program address falls within a protected sector,

Data# Polling on DQ7 is active for approximately 2 µs,

then the device returns to reading array data.

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, Data# Polling produces a “ꢀ” on

DQ7. This is analogous to the complement/true datum

output described for the Embedded Program algorithm:

the erase function changes all the bits in a sector to “ꢀ”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately ꢀ00 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

PASS

FAIL

Notes:

ꢀ. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section illustrates this.

2. DQ7 should be rechecked even if DQ5 = “ꢀ” because

DQ7 may change simultaneously with DQ5.

Figure 3. Data# Polling Algorithm

Rev 2

14/30

2014

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE# pulse in the com-

mand sequence (prior to the program or erase

operation), and during the sector erase time-out.

START

Read DQ7–DQ0

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

Read DQ7–DQ0

(Note ꢀ)

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

approximately ꢀ00 µs, then returns to reading array

data. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Toggle Bit

= Toggle?

Yes

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ5 = 1?

Yes

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

(Notes

ꢀ, 2)

Read DQ7–DQ0

Twice

Reading Toggle Bit DQ6

Toggle Bit

= Toggle?

Refer to Figure 4 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read

cycle.

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

ꢀ. Read toggle bit twice to determine whether or not it is

toggling. See text.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

complete the operation successfully, and the system

must write the reset command to return to reading

array data.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “ꢀ”. See text.

Figure 4. Toggle Bit Algorithm

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 4).

Rev 2

15/30

2014

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “ꢀ.” The system may ignore DQ3 if the sys-

tem can guarantee that the time between additional

sector erase commands will always be less than 50 µs.

See also the “Sector Erase Command Sequence”

section.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “ꢀ.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “ꢀ” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, DQ5 produces a “ꢀ.”

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “ꢀ”, the internally controlled erase cycle has

begun; all further commands are ignored until the

erase operation is complete. If DQ3 is “0”, the device

will accept additional sector erase commands. To en-

sure the command has been accepted, the system

software should check the status of DQ3 prior to and

following each subsequent sector erase command. If

DQ3 is high on the second status check, the last com-

mand might not have been accepted. Table 5 shows

the outputs for DQ3.

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

Table 5. Write Operation Status

DQ7

(Note 1)

DQ5

(Note 2)

Operation

DQ6

Toggle

DQ3

N/A

ꢀ

Standard

Mode

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

ꢀ

Toggle

Erase

Reading within Erase Suspended Sector

No toggle

N/A

Suspend

Mode

Reading within Non-Erase Suspended Sector

Data

Notes:

ꢀ. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘ꢀ’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Rev 2

16/30

2014

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +ꢀ25°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +ꢀ25°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

(Note ꢀ). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +ꢀ3.0 V

All other pins (Note ꢀ) . . . . . . . . . . . .–2.0 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

Notes:

Figure 5. Maximum Negative

Overshoot Waveform

ꢀ. Minimum DC voltage on input or I/O pin is –0.5 V. During

voltage transitions, inputs may overshoot V to –2.0 V

for periods of up to 20 ns. See Figure 5. Maximum DC

voltage on input and I/O pins is V + 0.5 V. During volt-

age transitions, input and I/O pins may overshoot to V

+ 2.0 V for periods up to 20 ns. See Figure 6.

20 ns

2. Minimum DC input voltage on A9 pin is –0.5V. During

voltage transitions, A9 pins may overshoot V to –2.0 V

+2.0 V

for periods of up to 20 ns. See Figure 5. Maximum DC in-

put voltage on A9 is +ꢀ2.5 V which may overshoot to ꢀ4.0

V for periods up to 20 ns.

+0.5 V

2.0 V

3. No more than one output shorted at a time. Duration of

the short circuit should not be greater than one second.

20 ns

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the op-

erational sections of this specification is not implied. Expo-

sure of the device to absolute maximum rating conditions for

extended periods may affect device reliability.

Figure 6. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T ) . . . . . . . . –55°C to +ꢀ25°C

Supply Voltages

for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V

for ꢀ0% devices . . . . . . . . . .+4.50 V to +5.50 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Rev 2

17/30

2014

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

Min

Typ

Max

± ꢀ.0

Unit

µA

Input Load Current

= V to V , V = V Max

CC CC

A9 Input Load Current

Output Leakage Current

= V Max, A9 = ꢀ2.5 V

µA

LIT

= V to V , V = V Max

± ꢀ.0

µA

OUT

CC CC

Active Read Current

CE# = V OE# = V

ꢀ2

CCꢀ

IL,

(Notes ꢀ, 2)

Active Write Current

CE# = V OE# = V

CC2

IL,

(Notes 2, 3, 4)

Standby Current

CE# and OE# = V

0.4

ꢀ.0

0.8

CC3

Input Low Voltage

Input High Voltage

–0.5

2.0

+ 0.5

Voltage for Autoselect and Sector

Protect (4)

= 5.0 V

ꢀ0.5

ꢀ2.5

0.45

Output Low Voltage

= ꢀ2 mA, V = V Min

Output High Voltage

= –2.5 mA, V = V Min

2.4

3.2

(4)

Low V Lock-out Voltage

4.2

(4)

LKO

Notes:

ꢀ. The I current listed is typically less than 2 mA/MHz, with OE# at V .

2. Maximum I specifications are tested with V =V max.

3. I active while Embedded Program or Embedded Erase Algorithm is in progress.

4. Not tested.

Rev 2

18/30

2014

DC CHARACTERISTICS (Continued)

CMOS Compatible

Parameter

Symbol

Parameter Description

Input Load Current

Test Description

Min

Typ

Max

± ꢀ.0

Unit

µA

= V to V , V = V Max

CC CC

A9 Input Load Current

Output Leakage Current

= V Max, A9 = ꢀ2.5 V

µA

LIT

= V to V , V = V Max

± ꢀ.0

µA

OUT

CC CC

Active Current (Notes ꢀ, 2) CE# = V OE# = V

ꢀ2

ꢀ

CCꢀ

CC2

CC3

IL,

Active Current

CE# = V OE# = V

IL,

(Notes 2, 3, 4)

Standby Current (Note 5)

CE# = V

± 0.5 V, OE# = V

µA

Input Low Voltage

Input High Voltage

–0.5

0.8

(4)

0.7 x V

V + 0.3

Voltage for Autoselect and

Sector Protect (4)

= 5.25 V

ꢀ0.5

ꢀ2.5

0.45

Output Low Voltage

= ꢀ2 mA, V = V Min

= –2.5 mA, V = V Min

0.85 V

OHꢀ

OH2

Output High Voltage

= –ꢀ00 µA, V = V Min

– 0.4

Low V Lock-out Voltage (4)

3.2

4.2

LKO

Notes:

ꢀ. The I current listed is typically less than 2 mA/MHz, with OE# at V .

2. Maximum I specifications are tested with V =V max.

3. I active while Embedded Program or Embedded Erase Algorithm is in progress.

4. Not tested.

5. I

= 20 µA max at extended temperatures (> +85°C).

CC3

Rev 2

19/30

2014

TEST CONDITIONS

5.0 V

2.7 kΩ

Device

Under

Test

6.2 kΩ

Note: Diodes are IN3064 or equivalent

Figure 7. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

Rev 2

20/30

2014

AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Symbol

Speed Options

-90

JEDEC

Std

Parameter Description

Test Setup

-120 Unit

Read Cycle Time (Note ꢀ)

Min

ꢀ20

AVAV

CE# = V

OE# = V

Address to Output Delay

Max

AVQV

ACC

Chip Enable to Output Delay

Output Enable to Output Delay

OE# = V

Max

ꢀ20

ELQV

GLQV

Chip Enable to Output High Z

(Note ꢀ)

Max

EHQZ

GHQZ

Output Enable to Output High Z

(Note ꢀ)

Max

Min

Read

Output Enable Hold Time

(Note ꢀ)

OEH

Toggle and Data

Polling

ꢀ0

Output Hold Time From

Addresses CE# or OE#,

Whichever Occurs First

Min

AXQX

Notes:

ꢀ. Not tested.

2. See Figure 7 and Table 6 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

Figure 8. Read Operations Timings

Rev 2

21/30

2014

AC CHARACTERISTICS

Erase and Program Operations

Parameter Symbol

Speed Options

-90

JEDEC

Std

Parameter Description

Write Cycle Time (Note ꢀ)

-120 Unit

Min

ꢀ20

AVAV

Address Setup Time

Address Hold Time

AVWL

WLAX

Data Setup Time

DVWH

WHDX

Data Hold Time

Output Enable Setup Time (Note 1)

OES

Read Recover Time Before Write

Min

GHWL

(OE# High to WE# Low) (Note 1)

CE# Setup Time

Min

µs

sec

µs

ELWL

WHEH

WLWH

WHWL

CE# Hold Time

Write Pulse Width

Write Pulse Width High (Note 1)

WPH

Byte Programming Operation (Note 1,2) Typ

Chip/Sector Erase Operation (Note 1,2) Typ

WHWHꢀ

WHWH2

WHWHꢀ

WHWH2

ꢀ.0

Set Up Time (Note ꢀ)

Min

VCS

Notes:

ꢀ. Not tested.

2. See the “Erase and Programming Performance” section for more informaiton.

Rev 2

22/30

2014

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

t_WPH

t_CS

t_DS

t_DH

D_OUT

A0h

Status

Data

V_CC

t_VCS

Note: PA = program address, PD = program data, D

is the true data at the program address.

OUT

Figure 9. Program Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

t_AS

t_WC

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

V_CC

Complete

55h

30h

Progress

10 for Chip Erase

t_VCS

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

Figure 10. Chip/Sector Erase Operation Timings

Rev 2

23/30

2014

AC CHARACTERISTICS

t_RC

Addresses

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 11. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

t_ACC

t_CE

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 12. Toggle Bit Timings (During Embedded Algorithms)

Rev 2

24/30

2014

AC CHARACTERISTICS

Erase and Program Operations

Alternate CE# Controlled Writes

Parameter Symbol

Speed Options

-90

JEDEC

Standard

Parameter Description

Write Cycle Time (Note ꢀ)

-120

Unit

µs

sec

Min

Typ

ꢀ20

AVAV

Address Setup Time

AVEL

ELAX

DVEH

EHDX

Address Hold Time

Data Setup Time

Data Hold Time

Output Enable Setup Time (Note ꢀ)

Read Recover Time Before Write

WE# Setup Time

OES

GHEL

WLEL

WE# Hold Time

EHWH

ELEH

CE# Pulse Width

CE# Pulse Width High

Byte Programming Operation (Note 2)

Chip/Sector Erase Operation (Note 2)

EHEL

CPH

WHWHꢀ

WHWH2

WHWHꢀ

WHWH2

ꢀ.0

Notes:

ꢀ. Not tested.

2. See the “Erase and Programming Performance” section for more information.

Rev 2

25/30

2014

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_DH

DQ7#

D_OUT

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

Notes:

ꢀ. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

= Array Data.

OUT

2. Figure indicates the last two bus cycles of the command sequence.

Figure 13. Alternate CE# Controlled Write Operation Timings

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Excludes 00h programming prior to

erasure (Note 4)

Chip/Sector Erase Time

ꢀ.0

ꢀ5

sec

Byte Programming Time

300

µs

Excludes system-level overhead

(Note 5)

Chip Programming Time (Note 3)

0.9

6.25

sec

Notes:

ꢀ. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , ꢀ million cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 4.5 V (4.75 V for -45), ꢀ00,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = ꢀ. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4

for further information on command definitions.

6. The device has a minimum guaranteed erase cycle endurance of ꢀ million cycles.

Rev 2

26/30

2014

21.1 (0.830) 0.25 (0.010)

3.96 (0.156) MAX

0.89 (0.035)

Radius TYP

0.2 (0.008)

0.05 (0.002)

11.3 (0.442)

0.30 (0.012)

9.55 (0.376) 0.25 (0.010)

1.27 (0.050) 0.25 (0.010)

PIN 1 IDENTIFIER

1.27 (0.050) TYP

19.1 (0.750) TYP

32 pin CSOJ

20.83 (0.820)

0.25 (0.010)

PIN 1

2.60 (0.102) MAX

IDENTIFIER

10.41 (0.410)

0.13 (0.005)

10.16 (0.400)

0.51 (0.020)

0.43 (0.017)

0.05 (0.002)

1.27 (0.050) TYP

19.05 (0.750) TYP

0.127 (0.005)

+ 0.05 (0.002)

– 0.025 (0.001)

32 Pin FP

Rev 2

27/30

2014

32 Pin TSOP

Rev 2

28/30

2014

ORDERING INFORMATION

Standard Products

FT standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

FT29F010B

XX MB - S

TEMPERATURE RANGE

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Military (–55°C to +ꢀ25°C)

Mil-Std-883 M5004

Spansion die

-S

Lead Free

PACKAGE TYPE

32-Pin FP

32-Pin FP Formed leads

32-Pin LCC

32-Pin CDIL

32-Pin Thin Small Outline Package (TSOP) Standard Pinout

SPEED OPTION

90nS 120nS

DEVICE NUMBER/DESCRIPTION

FT29F0ꢀ0B

ꢀ Megabit (ꢀ28 K x 8-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Rev 2

29/30

2014

Ashley Crt, Henley,

Marlborough, Wilts, SN8 3RH UK

Tel: +44(0)1264 731200

Fax:+44(0)1264 731444

E-mail

sales@forcetechnologies.co.uk

www.forcetechnologies.co.uk

Unless otherwise stated in this SCD/Data sheet, Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ

-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no

responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these

products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless

otherwise specified.

Life Support Applications

Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies

product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products

for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such

improper use or sale.

All trademarks acknowledged

Rev 2

30/30

2014

FT29F010B90FLF-S [FORCE]

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