FT6163LL-45JCLF [FORCE]
Ultra High Speed 8K x 9 Static Cmos Rams;型号: | FT6163LL-45JCLF |
厂家: | Force Technologies |
描述: | Ultra High Speed 8K x 9 Static Cmos Rams |
文件: | 总13页 (文件大小:932K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FT6163/FT6163L
Ultra High Speed 8K x 9
Static Cmos Rams
FEATURES
Data Retention with 2.0V Supply, 10 µA Typical
Full CMOS, 6T Cell
Current (FT6163L Military)
High Speed (Equal Access and Cycle Times)
– 25/35ns (Commercial)
Common I/O
– 25/35/45ns (Military)
Fully TTL Compatible Inputs and Outputs
Low Power Operation (Commercial/Military)
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
DESCRIPTION
Accesstimesasfastas25nanosecondsareavailable,per-
mittinggreatlyenhancedsystemoperatingspeeds.CMOS
is used to reduce power consumption in both active and
standbymodes.
TheFT6163andFT6163Lare73,728-bitultrahigh-speed
staticRAMsorganisedas8Kx9.TheCMOSmemoriesre-
quire no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
Withbatterybackup,dataintegrityismaintainedforsupply
voltages down to 2.0V. Current drain is 10 µA from a 2.0V
supply.
The FT6163 and FT6163L are available in 28-pin 300 mil
DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin
CERPACKpackagesprovidingexcellentboardleveldensi-
ties.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5), SOJ (J5)
CERPACK (F4) SIMILAR
LCC (L5
REV 1.2
1/13
2008
FT6163/FT6163L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
VTERM
TA
V
1.0
50
IOUT
mA
Operating Temperature –55 to +125 °C
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
Ambient
Temperature
Grade(2)
GND
VCC
5.0V ± 10%
Grade(2)
GND
VCC
Military
–55 to +125°C
0V
5.0V ± 10%
Commercial 0°C to +70°C
0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
FT6163
FT6163L
Symbol
Parameter
Test Conditions
Unit
Min
Max
VCC+0.5
0.8
Min
Max
VCC+0.5
0.8
VIH
Input High Voltage
2.2
–0.5(3)
2.2
–0.5(3)
V
V
V
V
V
V
VIL
Input Low Voltage
VHC
VLC
VCD
VOL
CMOS Input High Voltage
CMOS Input Low Voltage
VCC–0.2 VCC+0.5 VCC–0.2 VCC+0.5
–0.5(3)
0.2
–1.2
0.4
–0.5(3)
0.2
–1.2
0.4
Input Clamp Diode Voltage VCC = Min., IIN = –18 mA
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
IOLC = +100 µA, VCC = Min.
IOH = –4 mA, VCC = Min.
IOHC = –100 µA, VCC = Min.
VOLC
VOH
VOHC
ILI
Output Low Voltage
(CMOS Load)
0.2
0.2
V
V
Output High Voltage
(TTL Load)
2.4
2.4
Output High Voltage
(CMOS Load)
VCC–0.2
VCC–0.2
V
Input Leakage Current
VCC = Max.
VIN = GND to VCC
Mil.
Com’l.
–10
–5
+10
+5
–5
+5
µA
µA
N/A
N/A
ILO
Output Leakage Current
VCC = Max., CE = VIH,
VOUT= GND to VCC
Mil.
Com’l.
–10
–5
+10
+5
–5
+5
N/A
N/A
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Conditions Typ. Unit
pF
Symbol
Parameter
Conditions Typ. Unit
pF
COUT
Output Capacitance VOUT = 0V
7
CIN
Input Capacitance VIN = 0V
5
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
REV 1.2
2/13
2008
FT6163/FT6163L
POWER DISSIPATION CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
FT6163
FT6163L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
ICC
Dynamic Operating
Current – 25
VCC = Max., f = Max.,
Outputs Open
Mil.
Com’l.
—
—
145
125
—
—
145
N/A
mA
ICC
ISB
Dynamic Operating
Current – 35, 45
VCC = Max., f = Max.,
Outputs Open
Mil.
Com’l.
—
—
120
95
—
—
120
N/A
mA
mA
Standby Power Supply
Current (TTL Input Levels) CE2 ≤ VIL, VCC = Max.,
CE1 ≥ VIH or
Mil.
Com’l.
—
—
40
35
—
—
40
N/A
f = Max., Outputs Open
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
CE1 ≥ VHC or
Mil.
Com’l.
—
—
20
18
—
—
1
N/A
mA
CE2 ≤ VLC, VCC = Max.,
f = 0, Outputs Open,
VIN ≤ VLC or VIN ≥ VHC
n/a = Not Applicable
DATA RETENTION CHARACTERISTICS (FT6163L, Military Temperature Only)
Typ.*
VCC=
2.0V
Max
VCC=
2.0V
Symbol
Parameter
Test Condition
Min
Unit
3.0V
3.0V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
ICCDR
10
15
200
300
µA
CE1 ≥ VCC – 0.2V or
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V
tCDR
Chip Deselect to
Data Retention Time
0
ns
ns
†
§
tR
Operation Recovery Time
tRC
*TA = +25°C
§tRC = Read Cycle Time
†This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
REV 1.2
3/13
2008
FT6163/FT6163L
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-25
-35
-45
Symbol
Parameter
Unit
Min Max Min Max Min Max
tRC
tAA
tAC
Read Cycle Time
25
35
45
ns
ns
ns
Address Access Time
25
25
35
35
45
45
Chip Enable
Access Time
tOH
tLZ
Output Hold from
Address Change
3
3
3
3
3
3
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to
Output in Low Z
tHZ
Chip Disable to
Output in High Z
10
13
15
18
20
20
tOE
tOLZ
tOHZ
tPU
tPD
Output Enable
Low to Data Valid
Output Enable
Low to Low Z
3
0
3
0
3
0
Output Enable
High to High Z
12
20
15
20
20
25
Chip Enable to
Power Up Time
Chip Disable to
Power Down Time
READ CYCLE NO. 1 (OE CONTROLLED)(5)
Notes:
8. Transition is measured ± 200mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
LOW and CE2 transition HIGH.
REV 1.2
4/13
2008
FT6163/FT6163L
READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
REV 1.2
5/13
2008
FT6163/FT6163L
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-25
-35
-45
Symbol
tWC
Parameter
Unit
ns
Min Max Min Max Min Max
Write Cycle Time
25
18
35
25
45
33
tCW
Chip Enable
ns
Time to End of Write
tAW
Address Valid to
End of Write
18
25
33
ns
tAS
Address Set-up Time
Write Pulse Width
Address Hold Time
0
18
0
0
20
0
0
25
0
ns
ns
ns
ns
tWP
tAH
tDW
Data Valid to End
of Write
13
15
20
tDH
tWZ
Data Hold Time
0
3
0
5
0
5
ns
ns
Write Enable to
Output in High Z
10
14
18
tOW
Output Active
ns
from End of Write
WRITE CYCLE NO. 1 (WE CONTROLLED)(11)
Notes:
11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show tWZ and tOW
.
13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE
HIGH, the output remains in a low impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
REV 1.2
6/13
2008
FT6163/FT6163L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11)
AC TEST CONDITIONS
TRUTH TABLE
Mode
CE1 CE2 OE WE
I/O
Power
Input Pulse Levels
GND to 3.0V
Standby
Standby
H
X
X
L
X
X
X
X
High Z Standby
High Z Standby
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
DOUT
Disabled
1.5V
L
L
L
H
H
H
H
L
H
H
L
High Z Active
See Figures 1 and 2
Read
Write
DOUT
DIN
Active
Active
X
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the FT6163/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the VCC and ground
planes directly up to the contactor fingers. A 0.01 µF high frequency
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
REV 1.2
7/13
2008
FT6163/FT6163L
ORDERING INFORMATION
FT6163
FT6163L
L
XX
X
X
X
M5004
SELECTION GUIDE
The FT6163/L is available in the following temperature, speed and package options. The FT6163L is
only available over the military temperature range.
Speed
Temperature
Range
Package
Plastic DIP
35
45
25
Commercial
-35PC
-35JC
N/A
-25PC
-25JC
-25CM
-25LM
-25FM
Plastic SOJ
Side Brazed DIP
LCC
N/A
Miliitary
Temperature
-35CM
-35LM
-35FM
-35CMB
-35LMB
-35FMB
-45CM
-45LM
-45FM
-45CMB
-45LMB
-45FMB
CERPACK
Military
Processed*
Side Brazed DIP
-25CMB
-25LMB
LCC
-25FMB
CERPACK
* Military temperature range with MIL-STD-883 M5004
N/A = Not available
REV 1.2
8/13
2008
FT6163/FT6163L
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
0.020
0.011
0.730
A
A1
b
C
D
0.120
0.078
0.014
0.007
0.700
e
E
E1
E2
Q
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
0.025
-
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
5
9
REV 1.2
9/13
2008
FT6163/FT6163L
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C5
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
CERPACK CERAMIC FLAT PACKAGE
Pkg #
F4
# Pins
28
Symbol
Min
0.060
0.015
0.004
-
Max
A
b
c
D
E
e
0.090
0.022
0.009
0.730
0.380
0.330
0.050 BSC
k
L
Q
S
S1
0.005
0.018
0.370
0.045
0.085
-
0.250
0.026
-
0.005
REV 1.2
10/13
2008
FT6163/FT6163L
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
-
Max
0.210
-
0.023
0.070
0.014
1.400
0.300
0.380
A
A1
b
b2
C
D
E1
E
0.014
0.045
0.008
1.345
0.270
0.300
e
0.100 BSC
eB
L
α
-
0.430
0.150
15°
0.115
0°
REV 1.2
11/13
2008
FT6163/FT6163L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM120
FT6163/FT6163L ULTRA HIGH SPEED 8K x 9 STATIC CMOS RAMS
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTION OF CHANGE
DATE
ORIG
1997
M.S
New Data Sheet
1
Oct-05
Jul-06
M.S
M.S
M.S
Change logo to Pyramid
1.1
1.2
Added Lead-Free Designation
June-08
Updated SOJ package information and data sheet review
REV 1.2
12/13
2008
Ashley Crt, Henley,
Marlborough, Wilts, SN8 3RH UK
Tel: +44(0)1264 731200
Fax:+44(0)1264 731444
E-mail
sales@forcetechnologies.co.uk
www.forcetechnologies.co.uk
Unless otherwise stated in this SCD/Data sheet, Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ
-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no
responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these
products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless
otherwise specified.
Life Support Applications
Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies
product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products
for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such
improper use or sale.
Copyright Force Technologies Ltd 2010
All trademarks acknowledged
REV 1.2
13/13
2008
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