FT6264L-45L32ILF 概述
ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS
FT6264L-45L32ILF 数据手册
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PDF下载FT6264(L)
ULTRA HIGH SPEED 8K x 8
STATIC CMOS RAMS
FEATURES
Common Data I/O
Full CMOS, 6T Cell
Fully TTL Compatible Inputs and Outputs
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
–12/15/20/25/35/45/70/100ns(Military)
StandardPinout(JEDECApproved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP (70 & 100ns)
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
Low Power Operation
Output Enable and Dual Chip Enable Control
Functions
– 32-Pin 450 x 550 mil LCC
–28-PinCERPACK
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current(FT6264LMilitary)
2200V ESD Protection
DESCRIPTION
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The FT6264 is a 65,536-bit ultra high-speed static RAM
organised as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With
battery backup, data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
The FT6264 is available in 28-pin 300 mil DIP and SOJ, 28-
pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.
The 70ns and 100ns FT2664s are available in the 600 mil
plastic DIP.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOP(S6)
SEE PAGE 7 FOR LCC PIN CONFIGURATIONS
Rev 1.8
1/17
2012
FT6264(L)
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TBIAS
Temperature Under
Bias
–55 to +125 °C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150 °C
VTERM
TA
V
1.0
50
W
IOUT
mA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
RECOMMENDED OPERATING
VCC = 5.0V, TA = 25°C, f = 1.0MHz
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Grade(2)
GND
Symbol
Parameter
Conditions Typ. Unit
VCC
Temperature
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
0V
0V
0V
VIN = 0V
pF
pF
Input Capacitance
Output Capacitance
5
7
Industrial
Commercial
COUT
VOUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
FT6264
FT6264L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
2.2
VCC +0.5
2.2
VCC +0.5
VIH
VIL
Input High Voltage
Input Low Voltage
V
V
V
–0.5(3)
0.8
–0.5(3)
0.8
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
VHC
VLC
CMOS Input High Voltage
CMOS Input Low Voltage
–0.5(3)
0.2
–0.5(3)
0.2
V
V
VCD
VOL
–1.2
–1.2
VCC = Min., IIN = –18 mA
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
I
OL = +8 mA, VCC = Min.
V
V
0.4
0.4
Output High Voltage
(TTL Load)
VOH
ILI
IOH = –4 mA, VCC = Min.
VCC = Max.
2.4
2.4
Mil.
–10
–5
+10
+5
–5
n/a
+5
n/a
Input Leakage Current
µA
VIN = GND to VCC
Ind./Com’l.
Mil.
VCC = Max., CE = VIH,
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
ILO
Output Leakage Current
VOUT = GND to VCC Ind./Com’l.
___
___
___
___
mA
CE1 ≥ VIH or
CE2 ≤VIL,
VCC= Max,
Mil.
Ind./Com’l.
40
30
40
n/a
Standby Power Supply
Current (TTL Input Levels)
ISB
f = Max., Outputs Open
___
___
___
___
25
15
1
n/a
mA
CE1 ≥ VHC or
Mil.
Ind./Com’l.
Standby Power Supply
Current
CE2 ≤VLC,
ISB1
VCC= Max,
(CMOS Input Levels)
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUMrating conditions for extended
4. This parameter is sampled and not 100% tested.
2/17 2012
Rev 1.8
periods may affect reliability.
FT6264(L)
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
-8 -10 -12 -15 -20 -25 -35 45 -70 -100 Unit
Range
Commercial
200 180 170 160 155 150 145 N/A 130 125
N/A 190 180 170 160 155 150 N/A 145 140
N/A N/A 180 170 160 155 150 145 145 145
mA
mA
mA
ICC
Dynamic Operating Current*
Industrial
Military
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH
DATA RETENTION CHARACTERISTICS (FT6264L, Military Temperature Only)
Typ.*
VCC=
Max
VCC=
Symbol
Parameter
TestCondition
Min
Unit
2.0V
3.0V
2.0V
3.0V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
ICCDR
10
15
200
300
µA
CE1 ≥ VCC – 0.2V or
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V
or VIN ≤ 0.2V
tCDR
Chip Deselect to
0
ns
ns
Data Retention Time
Operation Recovery Time
†
§
tR
tRC
*TA = +25°C
§
tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Rev 1.8
3/17
2012
FT6264(L)
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Symbol Parameter Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
Read Cycle
Time
tRC
8
10
12
15
20
25
35
45
70
100
ns
Address
Access Time
tAA
tAC
8
8
10
10
12
12
15
15
20
20
25
25
35
35
45
45
70
70
100 ns
100 ns
Chip Enable
Access Time
Output Hold
from Address
Change
tOH
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
ns
Chip Enable to
Output in Low Z
tLZ
ns
Chip Disable
to Output in
High Z
tHZ
5
5
6
6
7
7
8
9
8
10
13
15
18
20
20
35
35
45 ns
Output Enable
Low to Data
Valid
tOE
10
45 ns
Output Enable
Low to Low Z
tOLZ
tOHZ
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
2
0
ns
Output Enable
High to High Z
5
6
7
9
9
12
15
20
25
35
35
45 ns
Chip Enable to
Power Up
Time
tPU
ns
Chip Disable
to Power Down
Time
tPD
8
10
12
15
20
20
20
45 ns
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
Notes:
5. WE is HIGH for READ cycle.
6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE1 transition
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Rev 1.8
LOW and CE2 transition HIGH.
4/17
2012
FT6264(L)
TIMING WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE1, CE2 CONTROLLED)(5,7,10)
Notes:
10. Transitions caused by a chip enable control have similar delays
irrespective of whether CE1 or CE2 causes them.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Symbol
Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC
Write ycle iCme 8T
Chip Enable
10
7
12
8
15
12
20
15
25
18
35
25
45
33
70
50
100
70
ns
tCW
Time to End of
Write
6
ns
Address Valid to
End of Write
tAW
tAS
tWP
tAH
7
0
7
0
8
0
8
0
10
0
12
0
15
0
18
0
25
0
33
0
50
0
70
0
ns
ns
ns
ns
Address Set-up
Time
Write Pulse
Width
9
12
0
15
0
18
0
20
0
25
0
40
0
50
0
Address Hold
Time
0
Data Valid to
End of Write
tDW
tDH
tWZ
6
7
0
8
0
9
0
11
0
13
0
15
0
20
0
30
0
40
0
ns
ns
Date old imeH
0T
Write Enable to
Output in High Z
6
7
7
7
8
10
14
18
30
40 ns
Output Active
from End of
tOW
3
3
3
3
3
3
3
3
3
3
ns
Write
Rev 1.8
5/17
2012
FT6264(L)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(11)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(11)
Notes:
11. CE1 and WE must be LOW, and CE 2 HIGH for WRITE cycle.
12. OE is LOW for this WRITE cycle to show t WZ and tOW
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
.
13. If CE1 goes HIGH, or CE goes LOW, simultaneously withWE HIGH,
the output remains in a2high impedance state.
Rev 1.8
6/17
2012
FT6264(L)
AC TEST CONDITIONS
TRUTH TABLE
Mode
CE1 CE2
O
E
WE
I/O
Power
Input Pulse Levels
GND to 3.0V
Standby
Standby
H
X
X
L
X
X
X
High Z Standby
High Z Standby
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
X
DOUT
Disabled
1.5V
L
L
L
H
H
H
H
L
H
H
L
High Z Active
See Figures 1 and 2
Read
Write
DOUT
Active
X
High Z Active
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the FT6264/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
LCC PIN CONFIGURATIONS
LCC (L5)
"L" - STANDARD PIN-OUT
LCC (L5)
"LS" - SPECIAL PIN-OUT
LCC (L6)
Rev 1.8
7/17
2012
FT6264(L)
ORDERING INFORMATION
L
X
X
X
x
FT6264
M5004
SELECTION GUIDE
The FT6264 is available in the following temperature, speed and package options. The F6T264L is available only over
the military temperature range.
Speed (ns)
Temperature
Range
Package
8
10
-10PC
N/A
12
-12PC
N/A
15
-15PC
N/A
20
-20PC
N/A
25
-25PC
N/A
35
-35PC
N/A
45
70
N/A
100
N/A
Commercial
Plastic DIP (300 mil)
Plastic DIP (600 mil)
Plastic SOJ
-8PC
N/A
-8JC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-70P6C
N/A
-100P6C
N/A
-10JC
N/A
-12JC
N/A
-15JC
N/A
-20JC
N/A
-25JC
N/A
-35JC
N/A
Plastic SOP
-70SNC
N/A
-100SNC
N/A
Industrial
Plastic DIP (300 mil)
Plastic DIP (600 mil)
Plastic SOJ
-10PI
N/A
-12PI
N/A
-15PI
N/A
-20PI
N/A
-25PI
N/A
-35PI
N/A
-70P6I
N/A
-100P6I
N/A
-10JI
N/A
-12JI
N/A
-15JI
N/A
-20JI
N/A
-25JI
N/A
-35JI
N/A
Plastic SOP
-70SNI
-100SNI
N/A = Not available
Rev 1.8
8/17
2012
FT6264(L)
SELECTION GUIDE (continued)
Speed (ns)
Temperature
Package
Range
8
10
12
15
20
25
35
45
70
100
Military
Temperature
Side Brazed DIP
CERDIP (300 mil)
CERDIP (600 mil)
CERPACK
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-12CM
-15CM
-20CM
-25CM
-35CM
-45CM
-70CM
-70DM
-100CM
-100DM
-12DM
-15DM
-20DM
-25DM
-35DM
-45DM
-12DWM
-12FM
-15DWM
-15FM
-20DWM
-20FM
-25DWM
-25FM
-35DWM
-35FM
-45DWM
-45FM
-70DWM -100DWM
-70FM
-70LM
-100FM
-100LM
28-Pin LCC
-12LM
-15LM
-20LM
-25LM
-35LM
-45LM
-12LSM
-12L32M
-12CMB
-12DMB
-15LSM
-15L32M
-15CMB
-15DMB
-20LSM
-20L32M
-20CMB
-20DMB
-25LSM
-25L32M
-25CMB
-25DMB
-35LSM
-35L32M
-35CMB
-35DMB
-45LSM
-45L32M
-45CMB
-45DMB
-70LSM
-100LSM
28-Pin LCC
32-Pin LCC
**
-70L32M -100L32M
Military
Side Brazed DIP
CERDIP (300 mil)
CERDIP (600 mil)
CERPACK
-70CMB
-70DMB
-100CMB
-100DMB
Processed
*
-12DWMB -15DWMB -20DWMB -25DWMB -35DWMB -45DWMB -70DWMB -100DWMB
-12FMB
-12LMB
-15FMB
-15LMB
-20FMB
-20LMB
-25FMB
-25LMB
-35FMB
-35LMB
-45FMB
-45LMB
-70FMB
-70LMB
-100FMB
-100LMB
28-Pin LCC
-12LSMB -15LSMB -20LSMB -25LSMB -35LSMB -45LSMB
-70LSMB -100LSMB
28-Pin LCC
32-Pin LCC
**
-12L32MB -15L32MB -20L32MB -25L32MB -35L32MB -45L32MB -70L32MB -100L32MB
* Military temperature range with MIL-STD-883 M5004
** SPECIAL PINOUT
N/A = Not available
Rev 1.8
9/17
2012
FT6264(L)
SIDE BRAZED DUAL IN-LINE PACKAGE (300 mils)
Pkg #
C5
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
SIDE BRAZED DUAL IN-LINE PACKAGE (600 mils)
Pkg #
C5-1
# Pins
28 (600 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.232
0.026
0.065
0.018
1.490
0.610
0.500
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.060
-
-
Rev 1.8
10/17
2012
FT6264(L)
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D5-1
# Pins
28 (600 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.232
0.026
0.065
0.018
1.490
0.610
0.500
eA
e
0.600 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D5-2
# Pins
28 (300 mil)
Symbol
Min
-
0.014
0.045
0.008
-
Max
A
b
b2
C
D
E
0.225
0.026
0.065
0.018
1.485
0.310
0.240
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Rev 1.8
11/17
2012
FT6264(L)
CERPACK CERAMIC FLAT PACKAGE
Pkg #
F4
# Pins
28
Symbol
Min
0.060
0.015
0.004
-
Max
A
b
c
D
E
e
0.090
0.022
0.009
0.730
0.380
0.330
0.050 BSC
k
L
Q
S
S1
0.005
0.018
0.370
0.045
0.085
-
0.250
0.026
-
0.005
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
0.020
0.011
0.730
A
A1
b
C
D
0.120
0.078
0.014
0.007
0.700
e
E
E1
E2
Q
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
0.025
-
MSL Level: 3
Rev 1.8
12/17
2012
FT6264(L)
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
5
9
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L6
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
7
9
Rev 1.8
13/17
2012
FT6264(L)
PLASTIC DUAL IN-LINE PACKAGE (300 mils)
Pkg #
P5
# Pins
28 (300 mil)
Symbol
Min
-
Max
0.210
-
0.023
0.070
0.014
1.400
0.300
0.380
A
A1
b
b2
C
D
E1
E
0.014
0.045
0.008
1.345
0.270
0.300
e
0.100 BSC
eB
L
α
-
0.430
0.150
15°
0.115
0°
MSL Level: 3
PLASTIC DUAL IN-LINE PACKAGE (600 mils)
Pkg #
# Pins
P6
28 (600 mil)
Symbol
Min
Max
A
A1
b
b2
C
D
E1
E
0.090
0.000
0.014
0.015
0.008
1.380
0.485
0.600
0.200
0.070
0.020
0.065
0.012
1.480
0.550
0.625
e
eB
L
α
0.100 BSC
0.600 TYP
0.100 0.200
0° 15°
MSL Level: 3
Rev 1.8
14/17
2012
FT6264(L)
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
5
9
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L6
32
Min
Max
0.060
0.050
0.022
0.442
0.075
0.065
0.028
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
-
0.458
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
7
9
Rev 1.8
15/17
2012
Ashley Crt, Henley,
Marlborough, Wilts, SN8 3RH UK
Tel: +44(0)1264 731200
Fax:+44(0)1264 731444
E-mail
sales@forcetechnologies.co.uk
www.forcetechnologies.co.uk
Unless otherwise stated in this SCD/Data sheet, Force Technologies Ltd reserve the right to make changes, without notice, in the products, Includ
-ing circuits, cells and/or software, described or contained herein in order to improve design and/or performance. Force Technologies resumes no
responsibility or liability for the use of any of these products, conveys no licence or any title under patent, copyright, or mask work to these
products, and makes no representation or warranties that that these products are free f rom patent, copyright or mask work infringement, unless
otherwise specified.
Life Support Applications
Force Technologies products are not designed for use in life support appliances, devices or systems where malfunction of a Force Technologies
product can reasonably be expected to result in a personal injury. Force Technologies customers using or selling Force Technologies products
for use in such applications do so at their own risk and agree to fully indemnify Force Technologies for any damages resulting from such
improper use or sale.
Copyright Force Technologies Ltd 2012
All trademarks acknowledged
Rev 1.8
16/17
2012
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM115
FT6264 ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAMS
ORIG. OF
CHANGE
ISSUE
DATE
REV.
DESCRIPTIONOFCHANGE
OR
1.1
1.2
1.3
1997
Oct-05
Jun-06
Aug-06
M.S
New Data Sheet
M.S
M.S
M.S
Data sheet review
Added 28-pin ceramic DIP
Added Lead Free Designation
1.4
1.5
Aug-06
Aug-06
M.S
M.S
Added "LS" - SPECIAL PIN-OUT
Updated SOJ package information
1.6
Jun-07
M.S
Corrected SOP package details
1.7
1.8
Jan-11
Feb-12
B.S
B.S
New logos added
Added MSL levels
Rev 1.8
17/17
2012
FT6264L-45L32ILF 相关器件
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