FS9912 [FORTUNE]
8-bit MCU with 4k program ROM;
| 型号： | FS9912 |
| 厂家： | 
Fortune Semiconductor |
| 描述： | 8-bit MCU with 4k program ROM |
| 文件： | 总34页 (文件大小：859K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REV. 3.6
FS9912-DS-36_EN
MAY 2014
Datasheet
FS9912
8-bit MCU with 4k program ROM,
128-byte data RAM,
1 low nosie OPAMP,
8-ch 14-bit ADC and 4 × 16LCD drive
FS9912
Fortune Semiconductor Corporation
富晶電子股份有限公司
23F., No.29-5,Sec. 2, Zhongzheng E. Rd.,
Danshui Town, Taipei County 251, Taiwan
Tel.：886-2-28094742
Fax：886-2-28094874
www.ic-fortune.com
This manual cotains new product information. Fortune Semiconductor Corporation reserves the rights to
modify the producpecification without further notice. No liability is assumed by Fortune Semiconductor
Corporation as a result of the use of this product. No rights under any patent accompany the sale of the
product.
Rev. 3.6
2/34
FS9912
Contents
1
2
3
4
5
6
7
8
GENERAL DESCRIPTION ...........................................................................................................................5
FEATURES ...................................................................................................................................................5
APPLICATIONS............................................................................................................................................5
ORDERING INFORMATION.......................................................................................................................5
PIN CONFIGURATION ...............................................................................................................................6
PIN DESCRIPTION....................................................................................................................................7
FUNCTIONAL BLOCK DIAGRAM ...........................................................................................................8
TYPICAL APPLICATION CIRCUIT.............................................................................................................9
8.1 Application Circuit of Ear Thermometer.......................................................................................9
8.2 Application Circuit of Scale (Lod Cell...................................................................10
8.3 Reference Circuit of AC To DC Conerter ..........................................................10
ABSOLUTE MAXIMUM RTINGS ........................................................................................................... 11
9
10 ELECTRICAL CHARACTERSTICS.................................................................................................11
10.1 DC Charactic (Unless otherwise specied VDD=3V，Ta=25℃).................................11
10.2 ADC Chatic (Unless otherwise sified VDD=3V，Ta=25℃........................................11
10.3 OPAMP Characteristic (Unless otherwispeified VDD=3V，Ta=25℃)...................................12
10.4 Tyrmance Characteris......................................................................................13
11 UNCTIOIPTION ...........................................................................................................14
11.1 CPU Core.................................................................................................................14
11.1.1 CPU Core Blck m............................................................................................14
11.1.2 Program Memry Organization......................................................................................14
11.1.3 Datory Organization ..................................................................................15
11.1.4 Syspecial Register Desriptio.........................................................................15
11.1.5 Instrucon Set.................................................................................................................16
11.1.6 Instruction Description...........................................................................................17
11.2 Power System..........................................................................................................................22
11.3 I/O Port..............................................................................................................................22
11.3.1 I/O Port1(PT1)..........................................................................................................22
11.3.2
I/O Port2 (PT2).............................................................................................................23
11.4 8 Bits Timer ..................................................................................................................................24
11.5 Dual 24 Bit Programmable Counter ............................................................................................24
11.6 Measuremenock Diagram ..............................................................................................26
11.7 ADC...............................................................................................................................................26
11.8 Analog Multiplex...........................................................................................................................27
11.9 Low Noise OPAMP........................................................................................................................27
11.10 LCD Driver...................................................................................................................................27
Rev. 3.6
3/34
FS9912
11.11 Watch Dog Timer ........................................................................................................................28
11.12 Special Register External Reset (Power On Reset) and WDT Reset State ............................29
11.13 Application Notes.......................................................................................................................29
12 ACKAGE OUTLINE..................................................................................................................................31
13 PAD ASSIGNMENT..................................................................................................................................32
14 PAD COORDINATE..................................................................................................................................33
15 REVISION HISTORY................................................................................................................................34
Rev. 3.6
4/34
FS9912
1. General Description
The FS9912 is a high performance, low cost CMOS 8-bit single chip microcontroller with embedded a 4kx16
bits ROM, an 8-channel 14-bit fully differential input analog to digital converter, low noise amplifier, and 4x16
LCD driver.
The FS9912 is best suited for applications such as low cost, high performance digital thermometer, ear
thermometer, scale, barometer, and hygrometer.
2. Features
z
z
z
z
z
z
z
z
z
z
z
8-bit microcontroller, 37 single word instructions
Embedded 4k x 16 program memory, 128-byte ata memory
Voltage operation ranges from 2.4V to 3.6V, 4MHz cystal oscillator
Operation current is less than 2mA, sleep mode crrent is about 1μA (LVR disable).
Low voltage reset (LVR) function mask opion. FS9912R_nnnV LVR enable, FS9912_nnnV Ldisable.
8-level deep hardware stacks
5 Interrupt sources (external: 2internal: 3
8-channel 14-bit ADC (±00mV input range, ±2LSB linearity errr) with 40Hz output rate
Embedded charge pumper and voltage regulator (4V egulated output)
Embedded bandgoltage reference (typical 1.2V50mV, 100ppm/°C)
Low noise (1without chopper, 0.5μV Vpp wih chopper, 0.1Hz~1Hz) OPAMPs with chopper
controller
z
z
z
z
16-bit binal I/O port and buzzer output
Dual mmable timers
4 x 16 L(3V Vpp)
Watchdog timer
3. Applications
z
z
z
Ear thermometer
Thermometer/Hygrometer
Scale/ Barometer
4. Ordering Information
Product Number
FS9912-nnnV
FS9912R-nnnV
Package Type
Dice form, or 64-pin LQFP
Dice form, or 64-pin LQFP
Note1: Code number (nnnigned for customer; ”nnn” = 001~999; ”V” means Version = A~Z.
Note2: FS9912R_nnnV means LVR enable, FS9912_nnnV means LVR disable.
Rev. 3.6
5/34
FS9912
5. Pin Configuration
49
50
51
52
53
54
55
56
57
58
59
60
61
64
OP1N
OP1O
REFO
REFI
FT2
SEG5
SEG4
SEG3
SEG2
SEG1
RLCD
VDDA
32
31
30
29
28
27
26
23
22
21
20
19
18
17
FT1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
FS9912
LQFP 64
CB
VDD
RST
TST
WDTEN
XOUT
XIN
D
Rev. 3.6
6/34
FS9912
6. Pin Description
Name
VDD
VSS
AGND
CB
CA
VGG
VDDA
RLCD
In/Out Pin No
Description
I
I
22
48
Positive Power Supply
Negative Power Supply
Analog Ground
I/O
I/O
I/O
I/O
I/O
I/O
I
64
23
24
25
26
27
17
Charge Pump Capacitor Negative Connection
Charge Pump Capacitor Positive Connection
Charge Pump Voltage
Analog Power Otput
LCD Bias Volage Input
4MHz Osciator Input
XIN
XOUT
P1.0~P1.7
P2.0~P2.7
SEG1~SEG16
COM1~COM4
AD0~AD7
REFO
REFI
O
I/O
I/O
O
O
I
O
I
I
18
4MHz Osillator Output
I/O Port 0
I/O Por1
1~8
9~16
28~43
LCD Segment Driver Output
47~44 D CommDriver Output
62~55 Anaog Input Channel
54
55
9
50
andgp Reference Output
ADC Reference Voltage Input
OPAMP 1 Negative Inpu
OPAMP 1 Output
OP1N
OP1O
FT1, FT2
VB
RST
TST
I
I/O
I
I
54,53 ADC Pre-Filter Capactor Connection
63
2
20
19
Analog Circuit BCurrent Input
CPU Reset
Testing Mode
WDTEN
Watchdog Timer Enable Control
Rev. 3.6
7/34
FS9912
7. Functional Block Diagram
4k x 16
Program Memory
128 Byte Data Memory
4 x 16 LCD Driver
Digital In/Out Port 1
and
Exteranl Interrupt Input
FSC 8bit CPCore
Charge Pumper,
Voltage Reglator,
LCD Bias Generator
and Bandgap Reference
Digital In/out Port 2
and
Buzzer Ouut
Analut
Mr
8-bit Time Base Counter
Low Noise OPAMP
Dual 24-bits Event Counter
Analog to Digital
Converter
Watchdog Timer
Rev. 3.6
8/34
FS9912
8. Typical Application Circuit
8.1 Application Circuit of Ear Thermometer
8888
C
49
50
51
52
53
54
55
56
57
58
63
64
OP1N
OP1O
REFO
REFI
FT2
SEG5
SEG4
SEG3
SEG2
SEG
R
A
VGG
32
31
30
29
28
2
25
24
23
22
21
20
19
18
10
k
300
k
-
AD3
AD2
+
20
k
50
k
27n
F
600
k
100
k
FT1
Rref
700k
AD7
AD6
AD5
D4
AD3
AD1
AD0
VB
1u
F
S9912
LQFP 64
Thermister
1u
F
1u
F
CB
VDD
RST
2.2n
F
OP1O
AD1
VIN+
TST
Analog to Digital
Converter
2.2
2.4V~3.6V
WDTEN
XOUT
XIN
VIN-
VR+
REFI
VR-
AGN
DC
Thermopile
AGND
1M
4MHz
Rev. 3.6
9/34
FS9912
8.2 Application Circuit of Scale (Load Cell)
8888C
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
OP1N
OP1O
REFO
REFI
FT2
SEG5
EG4
SEG3
SEG2
SEG1
RLCD
VD
GG
CA
32
31
30
29
28
26
25
24
23
22
21
20
19
17
200
k
2.5
k
-
AD6
+
E+
REFI
100
k
27n
F
90
k
FT1
VDDA
REFI
AD1
AD4
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VB
10
k
1u
F
Load
Cell
FS9912
LQF4
90
k
2.5
k
200
k
AD4
CB
10
k
VDD
RST
100
k
OP1O
AD1
3.3V Regulator
VIN+
AD1
TST
Analog to ital
onverter
2.2
F
TEN
XOUT
N
VI
VR+
REFI
VR
-
3.6V ~9V
AD4
10n
F
AGND
1
M
4
z
1u
F
E+
VDDA
8.3 Reference Circuit of AC To Derter
ADC
INH
ADC
INL
Vin
ND
AC to DC converter
Rev. 3.6
10/34
FS9912
9. Absolute Maximum Ratings
Parameter
Rating
-0.3 to 5.0
-0.3 to VDD+0.3
0 to +70
-55 to +150
260°C, 10 Sec
Unit
V
V
°C
°C
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Ambient Operating Temperature
Storage Temperature
Soldering Temperature, Time
10. Electrical Characteristics
10.1 DC Characteristic (Unless otherwise speciied VDD=3V，Ta=25℃)
Symbol
Parameter
Test Condtions
Mn.
Typ.
Max.
Unit
VDD
Recommend Operation
Power Voltage
2.4
3.6
V
IDD
IPO1
Supply Current
Power-off Supply Current
U, ADC
At Power Off, LVR
disable
1.5
1
mA
ꢀꢀμA
IPO2
Power-off Supply Current
At Power Off, LVR
enae
2
VIH
VIL
Ipu
Digital Input High Votage
Digital Input Low Vltage
Pull up Current
VD.5
V
ꢀμA
mA
mA
V
0.5
10
Vin=0
5
IOH
IOL
AGND
VDDA
VREF
VCREF
High Level Output Curren
High Level t Current
Analog oltage
Analog Po
Build in Refernce Voltage
BReference Voltage VD2.4~3.6
ge Coefficient
Beference Voltage Ta℃
Temre Coefficient
Low Battery Detector Volta
LCD Frame Frequency
VOH=0.9xVDD
VOL=0.1xVDD
1
2
VDD/2
4
1.20
V
V
To AGN
-2000
2.
+2000
ppm/V
TCREF
100
ppm/℃
VLBAT
FLCD
VLCD
24
32
3
V
Hz
V
LCD Pk-Pk Driver Voltge
3.2
10.2 ADC Charactenless otherwise specifiDD=3V，Ta=25℃)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VAIN
ADC Differential Inut Range
AGND-0.4 0
AGND+0. V
4
VRFIN
ADC Reference Input Range
Resolution
ADC Linearity Error
ADC Input Offset Voltage
With Zero Cancellation
0.25
0.5
V
Counts
mV
V
±15625
0
0
RFIN=0.44V
VRFIN=0.44V
VAIN=0
-0.1
+0.1
Rev. 3.6
11/34
FS9912
10.3 OPAMP Characteristic (Unless otherwise specified VDD=3V，Ta=25℃)
Symbol Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Input Offset
Input Offset Voltage with Zero Rs<100ꢀ
Cancellation
1
2
mV
ꢀV
Input Offset Voltage with Rs<100ꢀꢀ
Chopper
20
ꢀV
Input Offset Drift with Zero -20℃<TA<+50℃ꢀ
Cancellation
30
nV/℃
ꢀVpp
ꢀVpp
Input Reference Noise
Rs=100ꢀ,
1.0
0.5
0.1Hz~1Hz
Input Reference Noise with Rs=100ꢀ,
Chopper
0.1Hz~1Hz
Input Bias Current
Input Bias Current with
Chopper
10
100
30
300
pA
pA
Input Common Mode Range
Output Voltage Range
Chopper Clock Frequency
Capacitor Load
0.5
0.5
2.4
2.4
1k
0
100
Rev. 3.6
12/34
FS9912
10.4 Typical Performance Characteristics
VDDA vs Load
REFO vs Load
4.5
4
1.26
1.15
04
0.93
0.82
0
0.6
3.5
3
2.5
2
CVGG = 1uF
CCA-CB = 1uF
CVGG = 1uF
CCA-CB = 1uF
1.5
1
0.5
0
0.0 0.5 1.0 12.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
d (mA)
0
1
2
3
4
5
6
7
8
9
10
Load (mA)
urce vs Load
AGND Sink Load
1.4
1.2
1
3
2.75
2.5
2.25
2
0.8
0.6
4
0.2
CVGG = 1uF
CCA-CB = 1uF
CVGG =
CCA-CB
0
10
20
30
60
80
90
100
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
uA)
Load (mA)
Rev. 3.6
13/34
FS9912
11. unction Description
11.1 CPU Core
11.1.1 CPU Core Block Diagram
Data Bus
[7:0]
Oscillator
Clock Generator
8-Level Stack
Address Bus
[7:0]
Status Flag
Program Counter
Program Memory
ALU
Control Unit
FSR
Intrrupt Un
Gener
Data Memory
Interrupt Event
Input
11.1.2 rogram Memory Organzatio
FS9912 CPU h2-bit program counter capaf address an 4k x 16 program memory space.
The reset vec0000h and the interrupt vis a0004h.
0000h
0004h
Reset Vector
Program Conter
Interrupt Vector
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Le
tack Lev
Stack Level 7
Sck Level 8
0FFFh
Rev. 3.6
14/34
FS9912
11.1.3 Data Memory Organization
The data memory is partitioned into three parts. The address 00h~07h areas are system special registers, like
indirect address, indirect address pointer, status register, working register, interrupt flag, interrupt control
register. The address 08h~7Fh areas are peripheral special registers, like I/O ports, timer, ADC, signal
Name
IND0
IND1
FSR0
FSR1
Address
00h
01h
02h
03h
Content
Uses contents of FSR0 to address data memory
Uses contents of FSR1 to address data memory
Indirect data memory, address point
Indirect data memory, address pont 1
STATUS 04h
PD
TO
C
Z
WORK
INTF
INTE
05h
06h
07h
WORK register
GIE
MIF
TMIE
PCIF
PCIE
ADIF
ADIE
E1IF
E1IE
E0IF
E0IE
08h~7Fh Peripheral special registers
80h~FFh General data Memory
conditional network control register, LCD river… .The address 80h~FFh areas ae general data y.
IND0, IND1: indirect addressing mode adress
FSR0, FSR1: indirect addressig mode pnt
PD: Power Down Flag. Ceared by writing 0 or power-on resetet bsleep instruction
TO: Watch Dog Time Out Flag. Cleared by writing 0 or powe-on reset. Set by Watch Dog Time Out
C: Carry Flag
Z: Zero Flag
E0IF, E0IE: PTrnal interrupt flag and enable.
E1IF, E1IE: PTxternal interrupt flag and e.
ADIF, ADIE: Analoto digital converter interruflag nd enable.
PCIF, ram counter interrupt fland enable.
TMIF, Timer interrupt flag ae.
GE: Glupt enable.
11.1.4 System Special Register tion
11.1.4Indirect Addressing IND0 d FSR0 Register
The IND0 register is not a ical register. Addressing th0 (00h) will cause an indirect addressing. Any
instruction using the INer actually accessedata ted o by the FSR0 register.
A simple program to clear M 80h-FFh using indiret addressing is shown in following:
MOVLW 080h
MOVWF FSR0
NEXT: CLRF IND0
INCFSZ FSR0, 1
GOTO NEXT
11.1.4.2 Status Register
C： bit 1 R/W Carry Flag or (~Borrow).
Z： bit 0 R/W Zero Flag, st if ALU operation is zero. Reset otherwise.
Two simple examples to ille the relation between carry flag and arithmetic instructions.
Example 1
M (80h) = 3Fh M 81h) = F0h WORK = 99h
ADDWF 80h, 1
ADDWF 81h, 1
SUBWF 80h, 1
SUBWF 81h, 1
3Fh+99h=D8h DC=1, C=0, Z=0
; F0h+99h=89h DC=0, C=1, Z=0
; 3Fh-99h=A6hDC=1, C=0, Z=0
; F0h-99h=57hDC=0, C=1, Z=0
Rev. 3.6
15/34
FS9912
Example 2
16-bit add: {M (83h), M (82h)} = {M (83h), M (82h)} + {M (81h), M (80h)}
16-bit sub: {M (83h), M (82h)} = {M (83h), M (82h)} - {M (81h), M (80h)}
add:
MOVFW 80h
ADDWF 82h, 1
MOVFW 81h
ADDWFC83h, 1
sub:
MOVFW 80h
SUBWF 82h, 1
MOVFW 81h
SUBWFC83h, 1
11.1.4.3 Interrupt Flag INTF and Interrpt enable register INTE
The interrupt enable register (INTE) recods individual interrupt requet .WheInterrupt evand
Interrupt enable bit =1 , the interrupt flag will be set。The global interrupt enable bit (GIE) PU
interrupt procedure. When GIE=1 ad any inteupt flag is set, CPerrupt procedure woulted.
CPU interrupt procedure executs GIE eset and CALL 0004h.
Note. When interrupt signal hapened within Instruction Duty Cycle, the CPU must wait and till Instruction Duty
Cycle end of this program then produce an “Interrupt Flag” before go into next step.
11.1.5 Instruction
Inction
Operation
Cylce
Flag
No op
f=0
1
1
None
Z
d
INCF f, d
d=f+W
1
1
C, Z
Z
INCFSZ f, d
DECF f, d
DECFSZ f, d
SUBWF f,
COMF f, d
MOVWF f
MOVFW f
ADDWFC f, d
ANDWF f, d
IORWF f, d
XORWF f, d
RLF f, d
SUBWFC f, d
RRF f, d
ADDLW k
SUBLW k
ANDLW k
IORLW k
kip if d=0
d
d=f-1 skip if d=0
d=f-W
d=~f
f=W
W=f
d=f+W+C
d=f&W
[7:0]=f [7:0], C
d=-W- (~C)
d [7:0, c=C, f [7:0]
W=k+W
W=k-W
W=k&W
1,2
1
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
Z
None
C, Z
Z
None
None
C, Z
Z
Z
Z
C
C, Z
C
C, Z
C, Z
Z
W=k|W
Z
XORLW k
MVLW
RETLW k
CALL k
GOTO k
RETFIE
W=k^W
W=k
1
1
2
2
2
2
2
Z
None
None
None
None
None
None
RETURN and W=k
Push PC+1 and GOTO k
PC=k
Pop PC and GIE=1
Pop PC
RETURN
Rev. 3.6
16/34
FS9912
HALT
SLEEP
CLRWDT
ADDPCW
Stop uP clock
Stop OSC
Clear watch dog timer
PC=PC+1+{6{W [7], W 2
[6:0]}
1
1
1
None
PD
None
None
BCF f, b
BSF f, b
BTFSC f, b
BTFSS f, b
f [b]=0
f [b]=1
Skip if f[b]=0
Skip if f[b]=1
1
1
1,2
1,2
None
None
None
None
f : memory address ( 0h ~ FFh)
w: work register
k : literal field , constant data or label
d: destination select : d=0 store result in W, d=1: tre result in memory address f.
b: bit select(0~7)
M(f): the content of memory address f
PC: program counter
11.1.6 Instruction Description
NOP
No Opration
Syntax
NOP
Operation
Status Affected
Description
NOperation
Non
No opertion. NOP is used foone instruction cycle delay.
CLRF
Clear f
Syntax
CLRF f
Operation
Status Affecte
Description
0 => M (f)
1=> Z
Reset memory f content.
ADDWF
Add W to f
Syntx
ADDWF
Opeation
Status Aected
Description
W + M (f) tination)
DC, , Z
dd thcontent of the W regisand M (f). If d is 0, the result is stored in the W
ister. If d is 1, the result is d back in M (f).
INCF
Increment f
Syntax
INCF
f, d
Operation
Status Affected
Description
M (f) + 1 =stination)
Z
M (f) is imented. If d is 0, the result is stored in the W register. If d is 1, the
result is stod back in M (f).
INCFSZ
Incement f, skip if zero
Syntax
INCSZ f, d
Operation
Status Affected
Description
M (f) + 1 => (destination), skip if result is zero
is incremented. If d is 0, the result is stored in the W register. If d is 1, the
rsult is stored back in M (f). If the result is 0, then the next fetched instruction is
discarded and a NOP is executed instead making it a two-cycle instruction.
DECF
Decrement f
Syntax
DECF f, d
Operation
M (f) - 1 => (destination)
Rev. 3.6
17/34
FS9912
Status Affected
Description
Z
M (f) is decremented. If d is 0, the result is stored in the W register. If d is 1, the
result is stored back in M (f).
DECFSZ
Decrement f, skip if zero
Syntax
DECFSZ f, d
Operation
M (f) - 1 => (destination), skip if result is zero
Status Affected
Description
None
M (f) is decremented. If d is 0, he result is stored in the W register. If d is 1, the
result is stored back in M (f. If the result is 0, then the next fetched instruction is
discarded and a NOP is executed instead making it a two-cycle instruction.
SUBWF
Subtract W from f
Syntax
SUBWF f, d
Operation
Status Affected
Description
M (f) + NOT (W) + 1 => (destination)
DC, C, Z
Subtract the content of the W register from M (f). If d is 0, the result is d in te
W register. If d s 1, the result is stored back in M (f),
COMF
Complement f
Syntax
COMF f, d
Operation
NOT (M (f)) => M (f)
Status Affected
Description
Z
M (f) is complemented. If d is 0, the result is stored in the W regiser. If d is 1, the
result is stored back in M f)
MOVWF
Move W to f
Syntax
MOVWF f
Operation
Status Affect
Descrption
W => M (f)
None
Move data the register to M (f).
MOVW
Move f to
Syntax
MOVW f
Operation
Status Affected
Description
(f) => W
ne
Move data from M (f) to te W egister.
ADDWFC
Syntax
Add W, f and Carry
ADDWFCf, d
Operation
Status Affected
Description
W + M (f) + => (dtinatin)
DC, C, Z
Add the of te W register, M (f) and Carry bit. If d is 0, the result is stored
in the W rster. If d is 1, the result is stored back in M (f).
ANDWF
And W and f
Syntax
ANWF f, d
Operation
Status Affected
Description
W AND M (f) => (destination)
he content of the W register with M (f). If d is 0, the result is stored in the W
ter. If d is 1, the result is stored back in M (f).
IORWF
Inclusive OR W and f
Syntax
IORWFf, d
Operation
Status Affected
Description
W OR M (f) => (destination)
Z
Inclusive OR the content of the W register and M (f). If d is 0, the result is stored in
Rev. 3.6
18/34
FS9912
the W register. If d is 1, the result is stored back in M (f).
XORWF
Syntax
Exclusive OR W and f
XORWF f, d
Operation
Status Affected
Description
W XOR M (f) => (destination)
Z
Exclusive OR the content of the W register and M (f). If d is 0, the result is stored
in the W register. If d is 1, the result is stored back in M (f).
RLF
Rotate left M (f) through Carr
Syntax
RLF f, d
Operation
Status Affected
Description
M (f) [6:0], C => (destinaton)
C
M (f) is rotated one bit to tleft thrugh the Carry bit. If d is 0, the result is stored
in the W register. If d i1, the result is stored back in M (f).
SUBWFC
Syntax
Subtract W anCarry frof
SUBWFCf, d
Operation
Status Affected
Description
M (f) + NOT (W) + C => (destination)
DC, C, Z
Subtracthe contenof the W register fM (f). If d is 0, the result the
W egister. f d is 1, the result is stored ck in M (f).
RRF
Rotate right M (f) through Cay
Syntax
RRF f, d
Operation
Status Affected
Description
C, M (f) [7:1] => (destination)
C
M (f) is rotated one bit right through the Carry bt. If d is 0, the result is stored
in the W register. If d ithe esult is stored back in M (f).
ADDLW
ADD literal to
Syntax
ADDLW k
Operaon
Stats Affected
Desciptin
W + k =>
DC, C, Z
Add the cf the W register and the eight-bit literal "k". The result is stored in
the W register.
SUBLW
btract literal from W
Syntax
UBLW k
Operation
Status Affected
Description
k + NOT (W) + 1 => W
D, C, Z
Subtract the eight-eral "k" from the content of the W register. The result is
stored in the W regr.
ANDLW
AND litW
Syntax
ANDLW
Operation
Status Affected
Description
W AND k => W
Z
ANthe content of the W register with the eight-bit literal "k". The result is stored
in thW register.
IORLW
sive OR literal with W
Syntax
IORLWk
Operation
Status Affected
Description
W OR k => W
Z
Inclusive OR the content of the W register and the eight-bit literal "k". The result is
stored in the W register.
Rev. 3.6
19/34
FS9912
XORLW
Exclusive OR literal with W
Syntax
XORLW k
W XOR k => W
Z
Operation
Status Affected
Description
Exclusive OR the content of the W register and the eight-bit literal "k". The result is
stored in the W register.
MOVLW
Move literal to W
Syntax
MOVLW k
Operation
Status Affected
Description
k => W
None
Move the eight-bit literal "k" to the content of the W register.
RETLW
Syntax
Return and move literal W
RETLW
k
Operation
k => W
[Top Stack] =>
Pop Stack
Status Affected
Description
None
Move the eight-biliteral "k" to the content of the W register. The pnter
is loaded from the op stack, then pop .
CALL
Sbroutine CALL
Syntax
CALL k
Operation
Push Stack
PC + 1 => [Top Stack]
k => PC
Status Affected
Description
None
Subroutine Call. Firstturn address PC + 1 is pushed onto the stack. The
immediate address is loaded into PC.
GOTO
Unconditional
Syntax
GOTO k
Opeation
Status Affcted
Descripon
k => PC
None
The imediate address is loaded intPC.
Return
urn from Subroutine
Syntax
ETURN
Operation
[Top Stack] => PC
Pp Stack
Status Affected
Description
None
The program counts loaed from the top stack, then pop stack.
RETFIE
Syntax
Return errupt
RETFIE
Operation
[Top Stack] > PC
Pop Stack
1 =GIE
Status Affected
Description
Non
e program counter is loaded from the top stack, then pop stack. Setting the GIE
ables interrupts.
ADDPCW
Syntax
ADD W to Program Counter
ADDPCW
Operation
Status Affected
Description
PC + 1 + W => PC
None
The relative address PC + 1 + W is loaded into PC. The working register must less
than 80h (128d).
Rev. 3.6
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FS9912
HALT
Stop CPU Core Clock
Syntax
HALT
Operation
Status Affected
Description
CPU Stop
None
CPU clock is stopped. Oscillator is running. CPU can be waked up by internal and
external interrupt sources.
SLEEP
Oscillator stop
Syntax
SLEEP
Operation
Status Affected
Description
CPU oscillator is stopped
PD
CPU oscillator is stopp. CPU can be waked up by external interrupt sources.
PS. Please make sure all interrupt flags are cleared befrrunning SLEEP; "NOP" command must follow HALT
and SLEEP commands.
CLRWDT
Syntax
Clear watch dog timer counter
CLRWDT
Operation
Status Affected
Description
Watch dog timer counter will reset
None
CLRWDT instruction will reset watch dmecounter.
BSF
Bit Set f
Syntax
BSF f, b
Operation
Status Affected
Description
1 => M (f) [b]
None
Bit b in M (f) is set to 1.
BCF
Bit Clear f
Syntax
BCF f, b
Operation
Status ffecte
Desciption
0 => M (f) [b]
None
Bit b in M set t0.
BTFSC
Bit Tst skiClear
Syntax
BTFSCf, b
Operation
Status Affected
Description
p if M f) [b] = 0
one
If bit 'b' in M (f) is 0, e next fetched instruction is discarded and a NOP is
xecuted instead making it a two-cycle instruction.
BTFSS
Bit Test skip if Se
Syntax
BTFSSf, b
Operation
Status Affected
Description
Skip if M 1
None
If bit 'b' in (f) is 1, the next fetched instruction is discarded and a NOP is
executed instead making it a two-cycle instruction.
Rev. 3.6
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FS9912
11.2 Power System
Address
Name
NETD
Content
02CH
02DH
PUMPEN
LBCEN BNDEN LCDEN REGEN GNDEN BIASEN
LB
SVD
100k
1uF
1uF
VDD
Bandgap
Voltage
Reference
Vltage
egulator
LCD
Bias
Low Battery
Compararor
VSS
VGG
1uF
1uF
REGEN
LCDEN
BNDEN
LBCEN LB
tage
Doubler
MPEN
CA
CB
VC3,VC2,V1
(To LCD Diver)
Pump Clock
GNDEN
Analog
Cmon
Gerator
AD
VB
1uF
Bias
Circuit
BIAEN
Bias(to log Circuit
10nF
BIASEN=1 will the bias circuit of the anarcuit. When power on reet, BIASEN is 0
GNDEN=1 will stathe internal analog commgenerator circuit, and the AGND voltage is about (vdd,
vss)/2.
PUMPart the voltage doubt. VGG voltage is abot 2VDD.
PMPS ]) will set the voltage doperation frequeny: 0 is 2.7kHz, and 1 is 10kHz.
REGEN=1 start the internal vreguator. VDDA voltaabout 4V.
LCDEN=1 will start the LCD dricircuit. The LCD ias ltages are RLCD, 2/3RLCD, 1/3RLCD,
nd vss respectively.
BNDEN=1 will start thinternal bandgap voltage reference. The output voltage (REFO, AGND) is about
1.2V.
LBCEN=1 will stlow battery check ompaor. Te comparator inputs are VDD and REFO
respectively, and the w battery check voltage iabout 2.4V.
11.3 I/O Port
11.3.1 I/O Port1(PT1)
Address
Name
Content
020H
021H
022H
023H
PT1
PT1 [7:0]
PT1EN [7:0]
PT1PU [7:0]
PT1EN
PT1PU
PT1MR
E1M1
E1M0
E0M1
E0M0
Rev. 3.6
22/34
FS9912
PT1PU[7:0]
Databus[7:0]
D
Q
PT1[7:0]
LOAD
CK
AR==20h
Write
PT1EN[7:0]
EAD&A
PT1 is I/O port with pull-up restor enable control.
PT1EN [N] =0: PT1 [N] is as inpuport, 1PT1 [N] is as outpuort, sstem reset is 0.
PT1PU [N]=0: PT1 [N] wihout pull-up resistor, 1: PT1 [N] wth pull-up resistor, system reset is 0.
PT1 [1] PT1 [0] can be as exernal interrupt sources. Interrupt mode is controlled bM, E0M. 00:
negative edge, 01: ositive edge10&11: interrupt when change.
PT1 has Schmir input
11.3.2 I/O Port2 (PT
Address
024H
025H
026H
027
U
PT2MR
Content
PT2 [7:0]
PT2EN [7:0]
PT2PU
BPE2
BPE1
OPC1
OPC0
BPS PMPS
7:0]
Databus[7:0]
D
Q
PT2[7:0]
LOAD
CK
AR==24h
Write
PT:0]
4h
PT2 is I/O pos with pull-up resistor enable control.
PT2EN [N] =0: PT2 [N] is as input port, 1: PT2 [N] is as output port, system reset is 0.
BPE2 =1 & PT2EN [7]=1: PT2 [7] as buzzer output. BPE1=1 & PT2EN [6]=1: PT2 [6] as inverter buzzer
output. BPS=1: buzzer frequency=4kHz, BPS=0 buzzer frequency=2.7kHz.
Rev. 3.6
23/34
FS9912
11.4 8 Bits Timer
Address
00CH
00DH
Name
TMOUT
TMCON
Content
TMOUT [7:0]
TRST
WTS2
WTS1
WTS0
TMEN
INS2
INS1
INS0
TMOUT[7:0]
Tmer Interrupt Signal
8 to 1
Mux
TMEN
EN
CK
Out
8 bits Counter
128Hz Input
Reset
TRST
Write a “0” to bit 7 of address 0Dh, the CPU will send a low to TRST and reset thter.
Then read bit 7 of 0DH to et “1”
TMEN=1, the 8-bit counr will be enabled. TMEN=0, the 8bit counter will stop.
INS [2:0] selects timer interrpt source. The selection des are as follows, 000: TMT [0], 001 TMOUT
[1], 010: TMOUT [2], 011: TMOUT [3], 100: TMOUT [4], 101: TMOUT [5], 110: TT [6], 111: TMOUT
[7].
TMOUT [7:0] iput of the 8-bit counter. It is read-only.
11.5 Dual 24 Bit Prgrammable Counter
Address
014H
015H
016H
017H
018H
019H
01AH
CTAL
CTBH
CTBM
CTBL
FQCON
Content
CTA [23:16]
CTA [15:8]
CTA [7:0]
CTB [23:1
CTB [5:8]
TB [70]
LOAD
FCM1
M0
FCRST
GT2
GT1
GT0
Rev. 3.6
24/34
FS9912
FCRST
D
If FCM=10 Out=1
else Out=~Stop
Set
Set
Start
1
STOP
D
Q
Q
CTA=FFFFFFh
DCK
Load
CK
Load
CK
Program Counter
Interrupt Signal
P1.2
If FCMODE=10 Out=CTA Overflow
else Out=Stop
Rst
Rst
FCRST
Databus[7:0]
Start
Enable
CTA[7:0]
16-bit Counter
with Load
CTA[23:8]
8-bit counter
Multilex
DCK(1MHz)
Multiplex
CK
reset
GT
FCRST
Load
Wre
If FCM=10 Out=P1.2
else if FCM=01&Start=1 Out=P1.2
else if FCM=00&Start=1 Out=1
else Out=0
Databus[7:0]
Enable
C7:0]
CTB[7]
16-it Counter
witLoad
CTB[23:8]
8-bit counte
Multiplex
if FCM=00 Out=P1.2
else Out= DCK
CK
reset
FCRST
Write
Under modes FC0 and 01, we can set Load=to load data into CTA [23:8] d simultaneously set
GT. When LoaFCRST=1, CTA and CTB will start counting after the first positive edge signal from
input PT1.2. Tunters will not stop couuntil CTA overflows anafter te first positive edge
signal from input T1.2, and then the system l sed out an interrupt signal. Threfore, we can count
the cyclT1.2 nput signal to calculate he high-resolution frequency and duty cycle of the low
frequegnal by the following tion approach.
Under =10, CTA and CTB sting when FCRST=1. The counters will not stop counting
until CTws, and then the systeill send out an inpt signal. The calculating flows and
methods are described as follow
A.
Frequency Measurement CM=00
a.
b.
c.
Load=1, FCRST=0
Write 1415h to CTA [23:8] to set inalue of CTAI.
Set Go select the length ocounCTAGT=000 sets CTA [23:8] as a 16-bit counter
and CTis as the clock input; CA [230] is a 24-bit counter. GT=111 sets CTA [23:8] as a
16-bit counter and CTA [0] is as the clock input; {CTA [23:8], CTA[0]} is set as a 17-bit
counter.
d.
e.
f.
Gate Time = (1000000h-CTAI 6) x 1us … if GT=000
Set LOAD=0, FCRSTnd P.2 frequency starts measuring.
Wait till positive ed.2, then Start=1 and CTA and CTB start counting.
g.
Wait till CTA overflond at the next positive edge of P1.2, then Start=0 and CTA and CTB
stop counting.
h.
i.
When the CPU receives iterrupt signal, the CPU will read CTA and CTB. Here CTA is the
reference cloccounter, and CTB is the input clock counter
Frequency of P1.2 is 1MHz x CTB/(CTA+CTAI). Go to “a” for next measurement.
B.
Duty Cycle MemenMode: FCM=01
a.
b.
c.
Load=1=0
Write 14h 15h to CTA [23:8] to set initial value of CTAI.
Set GT [2:0] to select the length of counter CTA. GT=000 sets CTA [23:8] as a 16-bit counter
d CTA [7] is as the clock input; CTA [23:0] is a 24-bit counter. GT=111 sets CTA [23:8] as a
16-it counter and CTA [0] is as the clock input; {CTA [23:8], CTA [0]} is set as a 17-bit
counter.
d.
Gate Time = (1000000h-CTAI x 256) x 1us … if GT=000
Rev. 3.6
25/34
FS9912
e.
f.
Set LOAD=0, FCRST=1, and P1.2 frequency starts measuring.
Wait till positive edge of P1.2, then Start=1 and CTA and CTB start counting.
g.
Wait till CTA overflows and at the next positive edge of P1.2, then Start=0 and CTA and CTB
stop counting.
h.
i.
When the CPU receives interrupt signal, the CPU will read CTA and CTB. Here CTA is the
reference clock counter, and CTB counts when P1.2=1.
The duty cycle of P1.2 is 100% x CTB/(CTA+CTAI). Go to “a” for next measurement.
C.
Timer Mode: FCM=10
a.
b.
c.
Load=1, FCRST=0
Write 14h and 15h to CTA [23:8] to set nitial value of CTAI.
Set GT [2:0] to select the length of counter CTA. GT=000 sets CTA [23:8] as a 16-bit counter
and CTA [7] is as the clock input; TA [230] is a 24-bit counter. GT=111 sets CTA [23:8] as a
16-bit counter and CTA [0] is as thlock input; {CTA [23:8], CTA [0]} is set as a 17-bit
counter.
d.
e.
f.
Gate Time = (1000000h-CTAI x 256) x 1us … if GT=000
When CTA overflows, then end interrupt signal to the CPU.
If CPU receives interrupt signa, then Go to “a”.
11.6 Measurement Part Block Diagram
AGND
REFI
AD0
AD1
AD2
SONE
AD3
AD4
SONE=1
AD5
AD6
-
AD7
OP1
AD1
AGN
D6
AD
AD0
AD3
AD4
AD2
+
OP1P=111
SOP1P=110
SOP101
S1P=100
S=011
SOP1P=
SOP1P=001
SOP1P=000
ENOP
ADO[15:0]
AD
OP1P
Analog to Digital Converter
ADCGB[1:0]
AZ
ADINL
ADEN
ADRST
VRH
VRL
AD5
SINH=111
SINH=110
SINH=101
SINH=100
SINH=011
SINH=010
SINH=001
SINH=000
AD1
AD4
SFTA=1
SFT=00
SFT=01
SF
S=11
SL=10
SINL=01
SINL=00
VDD
OP1P
VRL
FTIN
AD0
AD4
AGND
AD7
AD0
REFI
AD4
SVRH=1
SVRH=0
SVRL=1
SVRL=0
AGND
VRH
OP1O
11.7 ADC
Address Name
Co
010H
011H
013H
02BH
AOH
ADL
ADCO
NETC
ADO [15:8]
ADO [7:0]
ADRST
AZ
ADG1
ADG0
ADEN
The ADC (analog to digital converter) contains Σ-Δ modulator and digital comb filter. When ADRST=1,
comb filter will be enabled. When ADRST=0, the comb filter will be reset. ADEN=1 starts the S-D
Rev. 3.6
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FS9912
modulator.
ADO is the ADC output. The maximum value is 3D09h and the minimum is C2F7h (-3D09h). FFFF
means (-0001).
The output rate of the ADC is 40Hz. When the output data are updated, the interrupt signal is sent to the
CPU. If ADIE=1, then ADIF is set to 1.
AZ=0 means that the ADC differential inputs are (INH, INL); AZ= 1 means that the ADC differential inputs
are (INL,INL). We can use this mode to measure the ADC offset.
ADCGB [1:0] will set ADC input gain as follows, 00: 2/3, 01: 1, 10: 2, 11: 2 1/3.
11.8 Analog Multiplex
Address Name
Content
029H
02AH
NETA
NETB
SINL1 SINL0
SVRH SVRL
SINH2
SINH1
EP
SINH0
SONE
SOP1P2 SOP1P1 SOP1P0
SFTA
SFT1
SFT0
OP1P: OP1 Positive Input
SOP1O
Select
000
AD2
001
AD4
010
A3
011
AD0
100
AD5
101
AD6
110
AGND
111
FTIN: Low Pass Filter Input
SINH
000
001
010
011
100
101
110
Select
OP1O
VH
VRL
OP1P
VDD
AD5
ADINL: ADC Negative Input
SINL
00
1
10
11
Select
AD7
GND
AD4
AD1
4. ADINH: Filter Output, ADC Positive Input
SFT [1:0]
Select
01
FTIN
10
AD0
11
D4
VRH: ADC Reference Voltage Positive
SVH
Select
0
1
AD0
REFI
VRL: ADC Reference Voegative Input
SVRL
Select
0
D4
AGND
External Filter Control: SFTA=0: FTIN and FT1 SFTA=1: FTIN and FT1 short.
11.9 Low Noise OPAMP
Address Name
Content
PT2MR BPE2, BPE1
NETB SVRH SVRL
ENOP is the OPAMP enabe control signal
027H
02AH
OPC1
SONE
OPC0
SFTA
BPS
SFT1
PMPS
SFT0
ENOP
SONE=1, the output and negative input of OPAMP is short and OPAMP is unit gain buffer.
OPC can set OP1 inration mode as follows, 00: +Offset, 01: -Offset, 10: 2KHz chopper frequency,
11: 1KHz Chopper fy.
11.10 LCD Diver
030H
031H
032H
033H
LCD1
LCD2
LCD3
LCD4
SEG1 [3:0], SEG2 [3:0]
SEG3 [3:0], SEG4 [3:0]
SEG5 [3:0], SEG6 [3:0]
SEG7 [3:0], SEG8 [3:0]
Rev. 3.6
27/34
FS9912
034H
035H
036H
037H
038H
LCD5
LCD6
LCD7
LCD8
LCDEN
SEG9 [3:0], SEG10 [3:0]
SEG11 [3:0], SEG12 [3:0]
SEG13 [3:0], SEG14 [3:0]
SEG15 [3:0], SEG16 [3:0]
LCDEN
LCD Common Driver Waveform
RLCD
2/3 RLCD
1/3 RLCD
COM1
VSS
RLCD
2/3 RLCD
1/3 RLCD
COM2
VSS
RLCD
2/3 RLCD
1/3 RLCD
COM3
VSS
RLCD
2/3 RLCD
1/3 RLCD
COM4
VSS
32Hz
LCD Common eform
LCDEN =1 will start the LCD clo
LD1~LCD8 is the LCD disay darea.
11.11 Watch Dog Tim
Address
04H
00DH
Name
STATUS
TMCON
ontent
PD
WTS0
TO
TMEN
C
INS1
Z
INS0
TRST,
WTS2
W
INS2
Watch Dog
Timer
Oscillator
WDTEN
WDTA[7:0]
WDTOUT
8 bits ounter1
Multiplex
8 bits Counter2
WDTS[2:0]
CLRWDT
WDTEN is an exernal input pin. It can be connected to VDD and then starts watchdog timer oscillator. If
it is floated or connected to VSS, the watchdog timer function will be disabled.
When WDT Counter 2 overflows, it will send WDTOUT to reset the CPU and set TO flag.
Rev. 3.6
28/34
FS9912
CLRWDT instruction will reset WDT Counter 2
WTS [2:0] selects WDT Counter 2 and the code selections are as follows, 000: WDTA [0], 001: WDTA [1],
010: WDTA [2], 011: WDTA [3], 100: WDTA [4], 101: WDTA [5], 110: WDTA [6], 111: WDTA [7].
11.12 Special Register External Reset (Power On Reset) and WDT Reset State
Register Name
Address
FSR0
02h
FSR1
03h
STATUS
04h
WORK
05h
INTF
06h
INTE
07h
External reset
WDT reset
Register Name
Address
uuuuuuuu
uuuuuuuu
PT1
uuuuuuuu
uuuuuuuu
PT1EN
21h
00000000
uuuu1uuu
PT1PU
22h
uuuuuuuu
uuuuuuuu
PT1MR
23h
00000000
00000000
PT2
00000000
00000000
PT2EN
25h
20h
24h
External reset
WDT reset
Register Name
Address
00000000
uuuuuuuu
PT2PU
26h
00000000
uuuuuuuu
PT2MR
27h
000000
uuu1uuu
MOUT
0Ch
00000000
uuuuuuu
TMCON
0Dh
00000000
uuuuuuuu
NETA
00000000
uuuuuuuu
NETB
29h
2Ah
External reset
WDT reset
Register Name
Address
00000000
uuuuuuuu
NETC
0000000
uuuuuuuu
NETD
000000
00000000
SVD
10000000
10000000
ADOH
00000000
00000000
ADOL
00000000
000000
2Bh
2Ch
2Dh
10h
11h
External reset
WDT reset
Register Name
Address
00000000
00000000
CTAH
0000000
0000000
CTAM
00000000
00000000
CTAL
0000
000000
CTBH
00000000
00000000
CTBM
0
00000
CTBL
014h
015h
016h
017h
018h
019h
External reset
WDT reset
Register Name
Address
00000000
000
1
0000000
00000000
LCD1
0000000
0000000
LC
00000000
00000000
LCD3
000000
0000000
LCD4
0000000
00000000
LCD5
30h
3
32h
3h
34h
External reset
WDT reset
Register Na
Address
0000000
000000
D6
uuuuuuuu
uuuuuuuu
LCD7
uuuuuu
uuuuuuuu
D8
uuuuuuuu
uuuuuuuu
LCDEN
38h
uuuuuuuu
uuuuuuuu
uuuuuuuu
uuuuuuuu
h
36h
h
External reset
WDT rese
uuuuuuuu
uuuuuuuu
uu
uu
uuuuuuuu
uuuuuuuu
uuuu
uuuuuu
u ean unknown or unchaned
11.13 Application No
A
HALT and SLEEP Cnds
Please make sure all interrupflags are cleared before running SLEEP; ”NOP” command must follow HALT and
SLEEP commands.
Example:
MAIN:
HALT
NOP
GOTO MAIN
MAIN_SLEEP:
CLRF INTF
SLEEP
NOP
GOTO SYSINI
Rev. 3.6
29/34
FS9912
B
VDDA Regulator
VDDA Regulator uses Bias Circuit as its bias current, while Bias Circuit uses VDDA power. According to the test
so far, when VDD<2.7V, it is easy to got the Start up problem and cause VDDA unable to start up. We strongly
recommend our customer doing the following setup when start VDDA Regulator. This setup can make VDDA
have one Diode Connection to VDD and start up VDDA Regulator
Example:
MOVLW 10001111B
MOVWF NETD
MOVLW 00100000B
MOVWF NETA
MOVLW 00000101B
MOVWF NETB
CALL
DELAY10ms
Customer must know how to use FS912_ICE o test the operatinrret of the chip, and tethe
operating current of the chip and sleep current for corresndincustom specification. Reference
Document: ”FS9912_ICEUserManual_VXX”.
Rev. 3.6
30/34
FS9912
12. Package Outline
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x1.4 mm
c
y
x
48
33
ZE
49
e
E
H
A
(A3)
A1
M
w
Θ
bp
1 index
64
17
detax
16
ZD
A
e
M
w
bp
D
M
H
B
D
0
2.5
scale
5 mm
DMENSIONS (mm e orignal dimensions)
A
(1)
(1)
UNIT
A1
bp
c
D(1)
E(1)
HD
L
Lp
v
w
y
ZD
ZE
Θ
max.
1.60
0.15 1.4
0.05 1.35
0.27 0.20 10.1 10.1
0.17 0.09 9.9 9.9
2.15 12
115 11.85
0.75
0.45
1.45 1.45
1.05 1.05
7 °
0 °
mm
25
0.5
1.0
0.2 0.12 0.075
Note: 1.Plastic or metal protrusions of 0.25 mm um per side are not included.
Rev. 3.6
31/34
FS9912
13. Pad Assignment
32
17
33
16
Y
48
1
49
64
(0,0)
ad oening : 90um
hip size : 2.112mm x 2.740mm
Substrate should nneced to VSS
Rev. 3.6
32/34
FS9912
14. Pad Coordinate
Pad No.
Name
X [mm]
Y [mm]
Pad No.
Name
X [mm]
Y [mm]
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
XI
2.035
2.035
2.035
2.035
2.035
2.035
2.035
2.035
2.035
2.035
2.035
2.05
2.035
2035
2.035
2.035
2.035
1.885
1.745
1.6
1.49
1.370
1.245
1.120
0.995
0.870
0.
0.6
0.495
0.370
0.230
0.082
0.385
0.525
0.665
0.790
0.915
1.040
1.165
1.290
1.415
1.540
1.665
1.790
1.915
2.040
2.180
2.3
2.6
3
3
2.663
2.663
2.663
2.63
2.663
63
2.663
2.663
2.663
2.663
2.663
2.663
33
34
35
36
37
38
39
40
41
42
43
44
45
6
47
48
49
50
51
52
5
54
55
56
57
58
59
60
61
62
63
64
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
COM4
COM3
COM2
COM1
VSS
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
77
0077
0.077
0.225
0.365
0.490
0.615
0.740
0.865
0.990
1.115
1.240
1.365
1.490
1.615
1.740
1.880
2.035
2.320
2.180
2.040
1.915
1.790
1.665
1.540
1.415
1.290
5
0.790
0.665
0.525
0.385
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
0.077
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
19
20
21
2
23
24
25
26
27
28
29
30
31
32
OP1N
P1O
REFO
REFI
OUT
TEN
TST
RST
FT2
VD
FT1
AD7
CA
AD6
VGG
VDDA
RLCD
SEG1
SEG2
SEG3
SEG4
SE
AD5
AD4
AD3
AD2
AD1
AD0
VB
AGND
Rev. 3.6
33/34
FS9912
15. Revision History
Ver.
Date
Page
Description
2.9
2003/04/16
27
MOVLW 00100000B
MOVWF NETA
3.0
2003/08/29
2
2
8
Operation current is less than 2mA, sleep mode current is about 1uA (LVR
disable)
Low voltage reset (LVR) function mask option. FS9912R-nnnV LVR
enable, FS9912-nnnV LVR disable.
IPO1: Sleep current of FS9912-nnnV
IPO2: Sleep current of FS9912R-nnnV
12
All
4
Change circuit drawing from draft to Visio format
Reformat and crrect the contents
2. Features
3.1
3.2
2004/04/05
2004/06/23
Correct “Low noie (1mV peak-to-peak without chopper, 0.5mV
peak-to-peak wih choper, 0.1Hz~1Hz) OPAMP with chopper controller.”
To “Low noise (1μpeak-to-peak without chopper, 0.5μV peak-to-peak
with chopper, 0.1Hz~1Hz) OPAMP with chopper controller.”.
2. Fetures
Correct Operation current is less than 2mAsleep mode out
1mA (LVR disable).” to “Operaturrent is less than 2mode
crrent is aout 1μA (LVR disa”.
3.3
3.4
2004/07/26
2004/10/18
4
-
1.
FSC will switch FS9912R ersin A to version B from 2004/10/18.
The reason is that FSC did some improvement about the ESD
immunity and LVR circuit of the FS9912. FSC’s FS9912R
version B test eview meeting minutes waceped by DCC on
2004/9/3.
2.
3.
1.
1.
Change the right-top title word of each page: “-Bit” to “–bit”.
Change ft-bottom word of each pge: “C” to “Corp”.
Add “Typl Peormance Characteristics”.
3.5
3.6
2005/12/02
12
35
2
Add evision History”.
Revised ny address
Rev. 3.6
34/34
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