DSP56724_技术文档

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: DSP56724EC

Rev. 1, 12/2008

DSP56724/DSP56725

DSP56724

144-Pin LQFP

20 mm × 20 mm

0.5 mm pitch

Symphony^™DSP56724/

DSP56725 Multi-Core Audio

Processors

DSP56725

80-Pin LQFP

14 mm × 14 mm

0.65 mm pitch

See Table 19.

meeting high MIPs requirements. Legacy peripherals from the

previous DSP5636x/37x families are included, as are a variety

of new modules available in the DSP5672x family. Modules

from the DSP56720 are included, such as an Asynchronous

Sample Rate Converter (ASRC), an Inter-Core

Communication (ICC) module, an External Memory

Controller (EMC) to support SDRAM (DSP56724 only), and

a Sony/Philips Digital Interface (S/PDIF) transceiver.

The Symphony DSP56724/DSP56725 Multi-Core Audio

Processors are part of the DSP5672x family of programmable

CMOS DSPs, designed using dual DSP56300 24-bit cores.

The DSP56724 is intended for consumer and professional

audio applications that require high performance for audio

processing. In addition, the DSP56724 is ideally suited for

applications that need the capability to expand memory

off-chip or to interface to external parallel peripherals.

Potential applications include A/V receivers, DVD Receivers,

Home Theater in a Box (HTIB), and professional audio

equipment including portable recording equipment, musical

instruments, guitar amplifiers and pedals. The DSP56724

offers customers flexibility in their designs by providing a

more cost-effective alternative to the DSP56720 while

maintaining pin compatibility.

The DSP56724/DSP56725 devices offer up to 250 million

instructions per second (MIPs) per core using an internal

250 MHz clock. The DSP56724/ DSP56725 products are high

density CMOS devices with 3.3 V inputs and outputs.

The DSP56724 block diagram is shown in Figure 1; the

DSP56725 block diagram is shown in Figure 2.

NOTE

The DSP56725 is intended for automotive and audio

applications that require high performance for audio

processing. Potential applications include A/V receivers,

DVD Receivers, Home Theater in a Box (HTIB), and

automotive amplifiers and entertainment systems. The

DSP56725 offers customers flexibility in their designs by

providing a more cost-effective alternative to the DSP56721

while maintaining pin compatibility.

This document contains information on a new product.

Specifications and information herein are subject to change

without notice. Finalized specifications may be published

after further characterization and device qualifications are

completed.

The DSP56724/DSP56725 devices provide a wealth of

on-chip audio processing functions, via a plug and play

software architecture system that supports audio decoding

algorithms, various equalization algorithms, compression,

signal generator, tone control, fade/balance, level

meter/spectrum analyzer, among others. The

DSP56724/DSP56725 devices also support various matrix

decoders and sound field processing algorithms.

With two DSP56300 cores, a single DSP56724/ DSP56725

device can replace dual-DSP designs, saving costs while

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Table of Contents

1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2.7 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . . . . 31

1.2.8 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.2.9 EMC Timing Specifications—DSP56724 . . . . . . . . 33

Functional Description and Application Information . . . . . . . 38

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

4.1 Pinout and Package Information . . . . . . . . . . . . . . . . . 39

4.1.1 Pinout for DSP56724 144-Pin Plastic

1.1 Chip-Level Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.1.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . 6

1.1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1.4 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . 7

1.1.5 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 8

1.1.6 Internal Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1.7 External Clock Operation. . . . . . . . . . . . . . . . . . . . . 9

1.1.8 Reset, Stop, Mode Select, and Interrupt Timing . . 10

1.2 Module-Level Specifications. . . . . . . . . . . . . . . . . . . . . . .13

1.2.1 Serial Host Interface SPI Protocol Timing . . . . . . . 14

1.2.2 Serial Host Interface (SHI) I²C Protocol Timing . . 20

1.2.3 Programming the SHI I²C Serial Clock . . . . . . . . . 22

1.2.4 Enhanced Serial Audio Interface Timing . . . . . . . . 23

1.2.5 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.2.6 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2

3

4

LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1.2 Pinout for DSP56725 80-Pin Plastic

LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.1.3 Pin Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2 144-Pin Package Outline Drawing. . . . . . . . . . . . . . . . 41

4.3 80-Pin Package Outline Drawing. . . . . . . . . . . . . . . . . 43

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5

6

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Freescale Semiconductor

EXTAL/XTAL

DSP

Core-0

DSP

Core-1

CGM

ASRC

On-Chip

Memory

On-Chip

Memory

Arbiter 9

Arbiter 8

Shared Bus 0

P

X

Y

P

X

Y

Shared Bus 1

Arbiters 0–7

PCU

DMA

OnCE

DMA

/ AGU

/ ALU

/ AGU

/ ALU

Shared Memory 4 Kbytes

Blocks 0–7 (32 Kbytes total)

MODA0, MODB0,

MODC0, MODD0

2 JTAGs

JTAG

MODA1, MODB1,

MODC1, MODD1

Figure 1. DSP56724 Block Diagram

EXTAL/XTAL

DSP

Core-0

DSP

Core-1

CGM

ASRC

On-Chip

Memory

On-Chip

Memory

Arbiter 8

Shared Bus 0

Shared Bus 1

P

X

Y

P

X

Y

Arbiters 0–7

PCU

DMA

OnCE

DMA

/ AGU

/ ALU

/ AGU

/ ALU

Shared Memory 4 Kbytes

Blocks 0–7 (32 Kbytes total)

MODA0, MODB0,

MODC0, MODD0

2 JTAGs

JTAG

MODA1, MODB1,

MODC1, MODD1

Figure 2. DSP56725 Block Diagram

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

3

1

Electrical Characteristics

1.1

Chip-Level Conditions

Table 1 provides a quick reference to the subsections in this section.

Table 1. Chip-Level Conditions

For

Section 1.1.1, “Maximum Ratings”

See

on page 4

on page 6

on page 7

on page 8

on page 9

on page 10

Section 1.1.2, “Thermal Characteristics”

Section 1.1.3, “Power Requirements”

Section 1.1.4, “DC Electrical Characteristics”

Section 1.1.5, “AC Electrical Characteristics”

Section 1.1.6, “Internal Clocks”

Section 1.1.7, “External Clock Operation”

Section 1.1.8, “Reset, Stop, Mode Select, and Interrupt Timing”

1.1.1

Maximum Ratings

CAUTION

This device contains circuitry protecting against damage due to high

static voltage or electrical fields. However, normal precautions

should be taken to avoid exceeding maximum voltage ratings.

Reliability of operation is enhanced if unused inputs are pulled to an

appropriate logic voltage level (for example, either GND or V ).

DD

The suggested value for a pull-up or pull-down resistor is 4.7 kΩ.

NOTE

In the calculation of timing requirements, adding a maximum value of one specification to

a minimum value of another specification does not yield a reasonable sum. A maximum

specification is calculated using a worst case variation of process parameter values in one

direction. The minimum specification is calculated using the worst case for the same

parameters in the opposite direction. Therefore, a “maximum” value for a specification will

never occur in the same device that has a “minimum” value for another specification;

adding a maximum to a minimum represents a condition that can never exist.

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Table 2 lists the maximum ratings.

Table 2. Maximum Ratings

1

1, 2

Rating

Symbol

Value

Unit

Supply Voltage

V

–0.3 to + 1.26

V

CORE_VDD, PLLD_VDD

V

PLLP_VDD, IO_VDD,

V

–0.3 to + 4.0

V

IO_VDD_25, PLLA_VDD

Maximum CORE_VDD power supply ramp time

Input Voltage per pin excluding VDD and GND

Tr

10

ms

V

GND – 0.3 to 5.5 V

IN

Current drain per pin excluding V and GND (Except for pads listed below)

I

12

5

mA

°C

DD

LSYNC_OUT

LCLK

I

lsync_out

I

5

lclk

LALE

I

5

ale

TDO

I

12

JTAG

Operating temperature range

• Fsys < 200 MHz

• Fsys < 250 MHz

T

J

–40 to +100

0 to 90

Storage temperature

T

–65 to +150

2000

°C

V

STG

ESD protected voltage (Human Body Model)

—

ESD protected voltage (Charged Device Model)

—

V

• All pins

• Corner pins

500

750

Note:

1. GND = 0 V, T = –40° C to 100° C, CL = 50 pF

J

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the maximum rating may affect device reliability or cause permanent damage to the device.

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

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1.1.2

Thermal Characteristics

Table 3 lists the thermal characteristics.

Table 3. Thermal Characteristics

Symbol

Characteristic

LQFP Values

Unit

Natural Convection, Junction-to-ambient thermal Single layer board

57 for 80 QFP

49 for 144 QFP

°C/W

1,2

resistance

(1s)

R

or θ

θJA

JA

JC

Four layer board

(2s2p)

44 for 80 QFP

40 for 144 QFP

°C/W

3

Junction-to-case thermal resistance

—

10 for 80 QFP

9 for 144 QFP

θJC

Note:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Thermal resistance between the die and the case top surface as measured by the cold plate method

(MIL SPEC-883 Method 1012.1).

1.1.3

Power Requirements

To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode

as shown in Figure 3, connected between the DSP56724/DSP56725 IO_VDD and Core_VDD power pins.

IO_VDD

External

Schottky

Diode

Core_VDD

Figure 3. Prevent High Current Conditions by Using External Schottky Diode

If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead

of Core_VDD, as shown in Figure 4.

Core_VDD

IO_VDD

Figure 4. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Freescale Semiconductor

For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,

as shown in Figure 4.

Tr

1.0 V

0 V

Core_VDD

Tr must be < 10 ms

Figure 5. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD

1.1.4

DC Electrical Characteristics

Table 4. DC Electrical Characteristics

Characteristics

Symbol

Min

Typ

Max

Unit

Core Supply voltages

• Fsys < 200 MHz

• Fsys < 250 MHz

V

0.95

1.14

1.0

1.2

1.05

1.26

CORE_VDD,

PLLD_VDD

IO Supply voltages

V

3.14

3.3

3.45

V

IO_VDD,

V

PLLP_VDD,

V

PLLA_VDD

Input high voltage

V

2.0

—

V

+ 2V

IO_VDD

IH

Note: To avoid a high current condition and possible system damage, all 3.3-V and 2.5-V supplies must rise before the 1.0-V

supplies rise.

Input low voltage

V

I

–0.3

—

0.8

80

V

IL

Input leakage current

μA

pF

μA

IN

Clock pin Input Capacitance (EXTAL)

C

—

2.057

—

IN

High impedance (off-state) input current (@ 3.3 V or

0 V)

I

–10

10

TSI

Output high voltage

V

2.4

—

V

OH

I

= –12 mA

OH

LSYNC_OUT, LALE, LCLK Pins I

= –16 mA,

OH

TDO Pin I = –24 mA

OH

Output low voltage

V

—

0.4

V

OL

I

= 12 mA

OL

LSYNC_OUT, LALE, LCLK Pins I = 16 mA,

OL

TDO Pins I = 24 mA

OL

Internal pull-up resistor

R

63

57

92

91

142

159

kΩ

PU

PD

Internal pull-down resistor

1

Internal supply current (core only) operating at

Fsys < 200 MHz

• In Normal mode

mA

I

—

90

60

280

250

CCI

• In Wait mode

I

CCW

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Table 4. DC Electrical Characteristics (Continued)

Characteristics

Symbol

Min

Typ

Max

Unit

2

• In Stop mode

I

—

30

220

mA

CCS

1

Internal supply current (core only) operating at

Fsys < 250 MHz

• In Normal mode

I

—

140

90

340

290

240

10

mA

pF

CCI

• In Wait mode

I

CCW

2

• In Stop mode

I

40

CCS

Input capacitance

C

—

IN

Note:

1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In

order to obtain these results, all inputs must be terminated (for example, not allowed to float). Measurements are based on

synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured

results of this benchmark. This reflects typical DSP applications. Typical internal supply current with Fsys < 200 MHz is

measured with V

= 1.0 V, V

= 3.3 V at T = 25° C. Maximum internal supply current is measured with

CORE_VDD

DD_IO J

V

= 1.05 V, V

= 3.6 V at T = 100° C. Typical internal supply current with Fsys < 250 MHz is measured with

CORE_VDD

IO_VDD) J

= 1.2 V, V

= 3.3 V at T = 25° C. Maximum internal supply current is measured with V

= 1.26 V,

CORE_VDD

DD_IO

J

= 3.6 V at T = 90° C.

IO_VDD)

J

2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (that is, not allowed

to float).

1.1.5

AC Electrical Characteristics

The timing waveforms shown in the AC electrical characteristics section are tested with a V maximum of 0.8 V and a V

IL

IH

minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in

production with respect to the 50% point of the respective input signal’s transition. For all pins, output levels are measured with

the production test machine V and V reference levels set at 0.4 V and 2.4 V, respectively.

OL

OH

1.1.6

Internal Clocks

Table 5 lists the internal clocks.

Table 5. Internal Clocks

No.

Characteristics

Symbol

Min

Typ

Max

Unit

Condition

1

2

Comparison Frequency

Fref

Fin

2

—

8

MHz Fref = Fin/NR

Input Clock Frequency

• with PLL enabled

• with PLL disabled

—

2

—

248

200

MHz

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Table 5. Internal Clocks (Continued)

No.

Characteristics

Symbol

Min

Typ

Max

Unit

Condition

3

4

PLL VCO Frequency

Fvco

Fout

200

—

500

MHz Fvco = (Fin * NF)/NR

[1] [2]

Output Clock Frequency

• with PLL enabled

• with PLL disabled

25

—

200 or 250

MHz Fout = Fvco/NO

Fout = Fin

5

System Clock Frequency

• with PLL enabled

• with PLL disabled

Fsys

—

[2]

DF

0.195

0

200 or 250

200

MHz Fsys = Fout/2

Fsys = Fout

Note:

1. Fin = External frequency

NF = Multiplication Factor

NR = Predivision Factor

NO = Output Divider

DF = Division Factor

2. Maximum frequency of 200 MHz supported at 0.95 V < V

Maximum frequency of 250 MHz supported at 1.14 V < V

< 1.05 V and –40 < Tj < 100° C

< 1.26 V and 0 < Tj < 90° C

VDD_CORE

1.1.7

External Clock Operation

The DSP56724/DSP56725 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip

oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see Figure 6.

EXTAL

XTAL

Suggested component values:

f

osc = 24.576 MHz

R = 1 M 10%

C (EXTAL)= 18 pF

C (XTAL) = 18 pF

R

XTAL1

Calculations are for a 5–30 MHz crystal with the following parameters:

C

• shunt capacitance (C ) of 10 pq–F12 pF

0

• series resistance 40 Ohm

• drive level of 10 μW

Figure 6. Using the On-Chip Oscillator

If the DSP56724/DSP56725 system clock is an externally supplied square wave voltage source, it is connected to EXTAL

(Figure 7). When the external square wave source is connected to EXTAL, the XTAL pin is not used.

V

IH

Midpoint

EXTAL

Eth

Etl

V

IL

6

7

8

Etc

Note:

The midpoint is 0.5 (V + V ).

IH IL

Figure 7. External Clock Timing

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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9

Table 6 lists the clock operation.

Table 6. Clock Operation

Symbol

No.

Characteristics

Min

Max

Units

1

6

EXTAL input high

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Eth

16.67

2.5

100

inf

ns

1

7

EXTAL input low

(40% to 60% duty cycle)

• Crystal oscillator

• Square wave input

Etl

Etc

Tc

16.67

2.5

100

inf

ns

8

9

EXTAL cycle time

• With PLL disabled

• With PLL enabled

5

33.3

inf

500

Instruction cycle time

• With PLL disabled

• With PLL enabled

5

inf

5120

4

Note:

1. Measured at 50% of the input transition.

2. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time

required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock

frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low

time requirements are met.

3. Maximum frequency of 200 MHz supported at 0.95 V < V

Maximum frequency of 250 MHz supported at 1.14 V < V

< 1.05 V and –40 < Tj < 100° C

< 1.26 V and 0 < Tj < 90° C

VDD_CORE

4. PLL

= 200 μs.

LOCK

1.1.8

Reset, Stop, Mode Select, and Interrupt Timing

Table 7 lists the reset, stop, mode select, and interrupt timing.

Table 7. Reset, Stop, Mode Select, and Interrupt Timing

No.

Characteristics

Expression

Min

Max

Unit

3

10

11

Delay from RESET assertion to all pins at reset value

—

11

ns

4

Required RESET duration

• Power on, external clock generator, PLL disabled

• Power on, external clock generator, PLL enabled

2 × T

10

—

ns

C

2 × T

C

13

Syn reset deassert delay time

• Minimum

2 × T

10

200

10

12

7

—

ns

us

ns

C

• Maximum (PLL enabled)

Mode select setup time

Mode select hold time

(2xT )+PLL

C

LOCK

14

15

16

17

18

—

Minimum edge-triggered interrupt request assertion width

Minimum edge-triggered interrupt request deassertion width

Delay from interrupt trigger to interrupt code execution

—

4

10 × T

54

C + 4

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Table 7. Reset, Stop, Mode Select, and Interrupt Timing (Continued)

No.

Characteristics

Expression

Min

Max

Unit

19

Duration of level sensitive IRQA assertion to ensure interrupt

service (when exiting Stop)

1, 2, 3

• PLL is active during Stop and Stop delay is enabled (OMR Bit

6 = 0)

(128 Kbytes × T

655

125

855

200

—

μs

ns

μs

ns

C)

• PLL is active during Stop and Stop delay is not enabled (OMR

Bit 6 = 1)

25 × T

C

• PLL is not active during Stop and Stop delay is enabled (OMR

Bit 6 = 0)

(128KxT ) + PLL

—

C

LOCK

• PLL is not active during Stop and Stop delay is not enabled

(OMR Bit 6 = 1)

(25 × T ) + PLL

—

C

LOCK

20

21

• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to

general-purpose transfer output valid caused by first interrupt

10 × T + 3.8

53.8

C

1

instruction execution

1

Interrupt Requests Rate

• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1

12 × T

—

60.0

40.0

60.0

ns

C

• DMA

8 × T

C

• IRQ, NMI (edge trigger)

• IRQ (level trigger)

8 × T

C

12 × T

C

22

DMA Requests Rate

• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

6 × T

—

30.0

35.0

10.0

15.0

ns

C

• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1

• Timer, Timer_1

7 × T

C

2 × T

C

• IRQ, NMI (edge trigger)

3 × T

C

Note:

1. When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply

to prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using

fast interrupts. Long interrupts are recommended when using Level-sensitive mode.

2. For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined

by the OMR Bit 6 settings.

For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL

to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 us.

3. Periodically sampled and not 100% tested.

4. RESET duration is measured during the time in which RESET is asserted, V is valid, and the EXTAL input is active and

DD

valid. When V is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the

DD

device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up. Designs should

minimize this state to the shortest possible duration.

™

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11

Figure 8 shows the reset timing diagram.

V

IH

RESET

11

13

10

All Pins

Reset Value

Figure 8. Reset Timing

Figure 9 shows external fast interrupt timing diagram.

a) First Interrupt Instruction Execution

19

18

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

b) General Purpose I/O

General

Purpose

I/O

20

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

Figure 9. External Fast Interrupt Timing

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Figure 10 shows external interrupt timing (negative edge-triggered).

IRQA, IRQB,

IRQC, IRQD,

NMI,

NMI_1

16

IRQA, IRQB,

IRQC, IRQD,

NMI,

17

NMI_1

Figure 10. External Interrupt Timing (Negative Edge-Triggered)

Figure 11 shows MODE select set-up and hold time diagram.

V

RESET

IH

14

15

V

IH

IL

MODA, MODB,

MODC, MODD,

PINIT

V

IRQA, IRQB,

IRQC,IRQD, NMI

IL

Figure 11. MODE Select Set-Up and Hold Time

1.2

Module-Level Specifications

Table 8 provides a quick reference to the subsections of this section.

Table 8. Module-Level Specifications

For

See

Section 1.2.1, “Serial Host Interface SPI Protocol Timing”

on page 4

on page 6

on page 7

on page 28

on page 29

on page 31

on page 32

on page 33

2

Section 1.2.2, “Serial Host Interface (SHI) I C Protocol Timing”

2

Section 1.2.3, “Programming the SHI I C Serial Clock”

Section 1.2.4, “Enhanced Serial Audio Interface Timing”

Section 1.2.5, “GPIO Timing”

Section 1.2.6, “JTAG Timing”

Section 1.2.7, “Watchdog Timer Timing”

Section 1.2.8, “S/PDIF Timing”

Section 1.2.9, “EMC Timing Specifications—DSP56724”

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

13

1.2.1

Serial Host Interface SPI Protocol Timing

Table 9 lists the serial host interface SPI protocol timing.

Table 9. Serial Host Interface SPI Protocol Timing

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

23 Minimum serial clock cycle = t

(min)

Master/Slave

Bypassed

Very Narrow

Narrow

10 × T + 9

59.0

183.0

383.0

—

0

ns

SPICC

C

10 × T + 9

C

10 × T + 133

C

Wide

10 × T + 333

C

XX Tolerable Spike width on data or clock in.

—

Bypassed

Very Narrow

Narrow

—

10

50

100

—

Wide

—

24 Serial clock high period

Master

Bypassed

29.5

0.5 × (t

)

SPICC

Very Narrow

Narrow

29.5

91.5

191

—

ns

Wide

Slave

Bypassed

Very Narrow

Narrow

2.5 × T + 12

24

C

2.5 × T + 12

24

C

2.5 × T + 102

114.5

201.5

29.5

C

Wide

2.5 × T + 189

C

25 Serial clock low period

Master

Bypassed

0.5 × (t

0.5 × t

)

SPICC

Very Narrow

Narrow

29.5

91.5

191

—

ns

Wide

)

SPICC

Slave

Bypassed

Very Narrow

Narrow

2.5 × T + 12

24

C

2.5 × T + 12

24

C

2.5 × T + 102

114.5

201.5

C

Wide

2.5 × T + 189

C

26 Serial clock rise/fall time

Master

Slave

—

5

ns

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Freescale Semiconductor

Table 9. Serial Host Interface SPI Protocol Timing (Continued)

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

27 SS assertion to first SCK edge

CPHA = 0

Slave

Bypassed

Very Narrow

Narrow

3.5 × T + 15

32.5

22.5

0

—

ns

C

3.5 × T + 5

C

—

Wide

0

—

CPHA = 1

Slave

Bypassed

Very Narrow

Narrow

10

0

—

0

—

Wide

0

—

28 Last SCK edge to SS not asserted

Bypassed

Very Narrow

Narrow

12

22

100

200

0

—

Wide

—

29 Data input valid to SCK edge (data input

set-up time)

Master

/Slave

Bypassed

Very Narrow

Narrow

—

0

—

0

—

Wide

0

—

30 SCK last sampling edge to data input not

valid

Master

/Slave

Bypassed

Very Narrow

Narrow

2 × T + 10

20

40

70

100.0

5

—

C

2 × T + 30

—

C

2 × T + 60

—

C

Wide

—

31 SS assertion to data out active

Slave

—

2

32 SS deassertion to data high impedance

—

9

33 SCK edge to data out valid

(data out delay time)

Master

/Slave

Bypassed

Very Narrow

Narrow

—

46.2

270

376

521

—

Wide

—

34 SCK edge to data out not valid

(data out hold time)

Master

/Slave

Bypassed

Very Narrow

Narrow

11.67

15

55

105

—

Wide

—

35 SS assertion to data out valid

(CPHA = 0)

Slave

—

14.0

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

15

Table 9. Serial Host Interface SPI Protocol Timing (Continued)

1,3,4

No.

Characteristics

Mode

Filter Mode

Expression

Min

Max

Unit

36 First SCK sampling edge to HREQ output

deassertion

Slave

Bypassed

Very Narrow

Narrow

—

45

55

—

ns

95

Wide

145

50.0

60.0

100.0

150.0

45.0

37 Last SCK sampling edge to HREQ output

not deasserted (CPHA = 1)

Slave

Bypassed

Very Narrow

Narrow

Wide

38 SS deassertion to HREQ output not

deasserted (CPHA = 0)

—

39 SS deassertion pulse width (CPHA = 0)

40 HREQ in assertion to first SCK edge

Slave

—

T + 6

11.0

96.0

—

ns

C

Master

0.5 × T

SPICC

+ 3.0 × T + 43

C

41 HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

0

—

ns

42 First SCK edge to HREQ in not asserted

(HREQ in hold time)

43 HREQ assertion width

3.0 × T

15

C

Note:

1. 0.95 V < V

< 1.05 V and T < 100° C, C = 50 pF

VDD_CORE

J

L

2. Periodically sampled, not 100% tested

3. All times assume noise free inputs.

4. All times assume internal clock frequency of 200 MHz.

5. SHI_1 specs match those of SHI

6. Slave timings should equal the serial clock high period + the serial clock low period.

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

16

Freescale Semiconductor

Figure 12 shows the SPI master timing (CPHA = 0).

SS

(Input)

25

23

24

26

SCK (CPOL = 0)

(Output)

24

25

SCK (CPOL = 1)

(Output)

29

30

m29

30

MISO

(Input)

MSB

Valid

LSB

Valid

34

33

MSB

MOSI

(Output)

LSB

40

42

HREQ

(Input)

43

Figure 12. SPI Master Timing (CPHA = 0)

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

17

Figure 13 shows the SPI master timing (CPHA = 1).

SS

(Input)

25

24

23

24

26

SCK (CPOL = 0)

(Output)

26

25

26

SCK (CPOL = 1)

(Output)

29

30

MISO

(Input)

MSB

Valid

LSB

Valid

33

34

MOSI

(Output)

MSB

LSB

40

41

42

HREQ

(Input)

43

Figure 13. SPI Master Timing (CPHA = 1)

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

18

Figure 14 shows the SPI slave timing (CPHA = 0).

SS

(Input)

25

23

28

24

26

39

SCK (CPOL = 0)

(Input)

27

24

26

25

SCK (CPOL = 1)

(Input)

35

33

34

32

31

MISO

(Output)

MSB

LSB

29

30

MSB

Valid

MOSI

(Input)

LSB

Valid

36

38

HREQ

(Output)

Figure 14. SPI Slave Timing (CPHA = 0)

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

19

Figure 15 shows the SPI slave timing (CPHA = 1).

SS

(Input)

25

23

28

24

26

SCK (CPOL = 0)

(Input)

27

24

26

25

SCK (CPOL = 1)

(Input)

33

34

32

31

MISO

(Output)

MSB

LSB

29

30

MSB

Valid

LSB

Valid

MOSI

(Input)

37

36

HREQ

(Output)

Figure 15. SPI Slave Timing (CPHA = 1)

1.2.2

Serial Host Interface (SHI) I²C Protocol Timing

2

Table 10 lists the SHI I C protocol timing diagram.

2

Table 10. SHI I C Protocol Timing

2

Standard I C

Standard

Fast-Mode

Symbol/

Expression

1,2,3,4,5

No.

Characteristics

Unit

Min

Max

Min

Max

XX Tolerable Spike Width on SCL or SDA

Filters Bypassed

—

0

10

50

100

—

0

10

50

100

ns

Very Narrow Filters enabled

Narrow Filters enabled

Wide Filters enabled.

44 SCL clock frequency

44 SCL clock cycle

F

T

—

10

100

—

400

—

kHz

μs

SCL

BUF

2.5

1.3

0.6

45 Bus free time

4.7

—

μs

46 Start condition set-up time

T

—

μs

SUSTA

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

20

Freescale Semiconductor

2

Table 10. SHI I C Protocol Timing (Continued)

2

Standard I C

Standard

Fast-Mode

Symbol/

Expression

1,2,3,4,5

No.

Characteristics

Unit

Min

Max

Min

Max

47 Start condition hold time

48 SCL low period

T

4.0

4.7

4.0

—

0.6

1.3

—

μs

ns

μs

HD;STA

T

LOW

49 SCL high period

T

—

HIGH

7

50 SCL and SDA rise time

T

1000

5.0

—

300

5.0

—

R

7

51 SCL and SDA fall time

T

F

—

52 Data set-up time

53 Data hold time

T

250

0.0

100

0.0

SU;DAT

—

0.9

HD;DAT

54 DSP clock frequency

• Filters bypassed

F

OSC

10.6

11.8

13.1

—

28.5

39.7

61.0

—

MHz

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

55 SCL low to data out valid

56 Stop condition setup time

T

—

3.4

—

0.9

—

μs

ns

VD;DAT

SU;STO

SU;RQI

T

4.0

0.0

0.6

0.0

57 HREQ in deassertion to last SCL edge (HREQ in

set-up time)

t

—

58 First SCL sampling edge to HREQ output

deassertion²

T

NG;RQO

• Filters bypassed

4 × T + 30

—

50.0

70.0

250.0

150.0

—

50.0

70.0

150.0

250.0

ns

C

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

⁴× T + 50

C

⁴× T + 130

C

⁴× T + 230

C

59 Last SCL edge to HREQ output not deasserted²

• Filters bypassed

T

AS;RQO

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

2 × T + 30

40

50

90

—

40

50

90

—

ns

C

²× T + 40

C

²× T + 80

C

²× T + 130

140

C

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

21

2

Table 10. SHI I C Protocol Timing (Continued)

2

Standard I C

Standard

Fast-Mode

Symbol/

Expression

1,2,3,4,5

No.

Characteristics

Unit

Min

Max

Min

Max

60 HREQ in assertion to first SCL edge

• Filters bypassed

T

AS;RQI

4327

4317

4282

4227

—

927

917

877

827

—

ns

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

61 First SCL edge to HREQ is not asserted

(HREQ in hold time.)

t

0.0

—

0.0

—

ns

HO;RQI

Note:

1. V

= 1.00 0.05 V; T = –40° C to 100° C, C = 50 pF

CORE_VDD

J

L

2. Pull-up resistor: R ^P(min) = 1.5 kΩ

3. Capacitive load: C ^b(max) = 50 pF

5. All times assume noise free inputs

5. All times assume internal clock frequency of 200 MHz

6. SHI_1 specs match those of SHI

7. The numbers listed are based on the module/pad design and its characteristics during output. The module is compliant with

2

I C standard, so the module should receive I C bus compliant signal without any issue.

1.2.3

Programming the SHI I²C Serial Clock

2

The programmed serial clock cycle, T

, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock

I CCP

control register).

2

The expression for T

is

I CCP

T ²

= [T × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]

Eqn. 1

I CCP

C

where

— HRS is the prescaler rate select bit. When HRS is cleared, the fixed

divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.

— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be

selected.

2

In I C mode, the user may select a value for the programmed serial clock cycle from

6 × T (if HDM[7:0] = $02 and HRS = 1)

Eqn. 2

C

to

4096 × T (if HDM[7:0] = $FF and HRS = 0)

Eqn. 3

C

2

The programmed serial clock cycle (T

shown in next.

) should be chosen in order to achieve the desired SCL serial clock cycle (T

), as

SCL

I CCP

T ²

+ 3 × T + 45ns + T

(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)

Eqn. 4

I CCP

C

R

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

22

Freescale Semiconductor

2

Figure 16 shows the I C timing diagram.

44

46

49

48

SCL

SDA

50

53

51

45

52

MSB

LSB

ACK

Stop

Start

47

60

58

55

56

59

61

57

HREQ

2

Figure 16. I C Timing

1.2.4

Enhanced Serial Audio Interface Timing

Table 11 lists the enhanced serial audio interface timing.

Table 11. Enhanced Serial Audio Interface Timing

1, 2, 3

3

4

No.

Characteristics

Symbol Expression

Min

Max Condition Unit

5

62 Clock cycle

t

4 × T

20.0

—

i ck

ns

SSICC

c

63 Clock high period

• For internal clock

ns

—

2 × T

10

—

c

• For external clock

64 Clock low period

• For internal clock

ns

—

2 × T

—

10

—

c

• For external clock

65 SCKR rising edge to FSR out (bl) high

66 SCKR rising edge to FSR out (bl) low

67 SCKR rising edge to FSR out (wr) high

—

17.0

7.0

x ck

i ck a

ns

—

17.0

7.0

x ck

i ck a

6

—

19.0

9.0

x ck

i ck a

6

68 SCKR rising edge to FSR out (wr) low

—

19.0

9.0

x ck

i ck a

69 SCKR rising edge to FSR out (wl) high

70 SCKR rising edge to FSR out (wl) low

—

16.0

6.0

x ck

i ck a

—

17.0

7.0

x ck

i ck a

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

23

Table 11. Enhanced Serial Audio Interface Timing (Continued)

1, 2, 3

3

4

No.

Characteristics

Symbol Expression

Min

Max Condition Unit

71 Data in setup time before SCKR (SCK in synchronous

mode) falling edge

—

12.0

19.0

—

x ck

i ck

ns

72 Data in hold time after SCKR falling edge

3.5

9.0

—

x ck

i ck

6

73 FSR input (bl, wr) high before SCKR falling edge

2.0

12.0

—

x ck

i ck a

74 FSR input (wl) high before SCKR falling edge

75 FSR input hold time after SCKR falling edge

76 Flags input setup before SCKR falling edge

77 Flags input hold time after SCKR falling edge

78 SCKT rising edge to FST out (bl) high

2.0

12.0

—

x ck

i ck a

2.5

8.5

—

x ck

i ck a

0.0

19.0

—

x ck

i ck s

6.0

0.0

—

x ck

i ck s

—

18.0

8.0

x ck

i ck

79 SCKT rising edge to FST out (bl) low

—

20.0

10.0

x ck

i ck

6

80 SCKT rising edge to FST out (wr) high

—

20.0

10.0

x ck

i ck

6

81 SCKT rising edge to FST out (wr) low

—

22.0

12.0

x ck

i ck

82 SCKT rising edge to FST out (wl) high

—

15.0

9.0

x ck

i ck

83 SCKT rising edge to FST out (wl) low

—

15.0

10.0

x ck

i ck

84 SCKT rising edge to data out enable from high impedance

85 SCKT rising edge to transmitter #0 drive enable assertion

86 SCKT rising edge to data out valid

—

22.0

17.0

x ck

i ck

—

17.0

11.0

x ck

i ck

—

25.0

13.0

x ck

i ck

7

87 SCKT rising edge to data out high impedance

—

25.0

16.0

x ck

i ck

88 SCKT rising edge to transmitter #0 drive enable

—

14.0

9.0

x ck

i ck

7

deassertion

6

89 FST input (bl, wr) setup time before SCKT falling edge

2.0

18.0

—

x ck

i ck

90 FST input (wl) setup time before SCKT falling edge

91 FST input hold time after SCKT falling edge

2.0

18.0

—

x ck

i ck

4.0

5.0

—

x ck

i ck

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24

Freescale Semiconductor

Table 11. Enhanced Serial Audio Interface Timing (Continued)

1, 2, 3

3

4

No.

Characteristics

Symbol Expression

Min

Max Condition Unit

92 FST input (wl) to data out enable from high impedance

93 FST input (wl) to transmitter #0 drive enable assertion

94 Flag output valid after SCKT rising edge

—

21.0

14.0

—

ns

—

14.0

9.0

x ck

i ck

95 HCKR/HCKT clock cycle

—

2 × T

—

10

—

ns

C

96 HCKT input rising edge to SCKT output

97 HCKR input rising edge to SCKR output

18.0

—

Note:

1. 0.95 V < V

< 1.05 V and Tj < 100° C, C = 50 pF

VDD_CORE

L

2. i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

3. bl = bit length

wl = word length

wr = word length relative

4. SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5. For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.

6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync

signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one

before last bit clock of the first word in frame.

7. Periodically sampled and not 100% tested.

8. ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

25

Figure 17 shows the ESAI transmitter timing diagram.

62

63

SCKT

64

(Input/Output)

78

79

FST (Bit)

Out

82

83

FST (Word)

Out

86

84

86

87

First Bit

Last Bit

Data Out

93

Transmitter #0

Drive Enable

(Internal Signal)

89

85

88

91

FST (Bit) In

92

91

90

FST (Word) In

Flags Out

94

See Note

Note: In network mode, output flag transitions can occur at the start of each time slot within the

frame. In normal mode, the output flag state is asserted for the entire frame period.

Figure 17. ESAI Transmitter Timing

™

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26

Freescale Semiconductor

Figure 18 shows the ESAI receiver timing diagram.

62

63

SCKR

64

(Input/Output)

65

66

FSR (Bit)

Out

69

70

FSR (Word)

Out

72

71

Data In

Last Bit

First Bit

75

73

FSR (Bit)

In

74

75

77

FSR (Word)

In

76

Flags In

Figure 18. ESAI Receiver Timing

Figure 19 shows the ESAI HCKT timing diagram.

HCKT

95

SCKT(output)

96

Figure 19. ESAI HCKT Timing

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

27

Figure 20 shows the ESAI HCKR timing diagram.

HCKR

95

SCKR (output)

97

Figure 20. ESAI HCKR Timing

1.2.5

GPIO Timing

Table 12 lists the GPIO timing.

Table 12. GPIO Timing

1

No.

Characteristics

Expression

Min

Max

Unit

2

100 Fsys edge to GPIO out valid (GPIO out delay time)

—

2

7

ns

2

101 Fsys edge to GPIO out not valid (GPIO out hold time)

2

102 Fsys In valid to EXTAL edge (GPIO in set-up time)

—

2

103 Fsys edge to GPIO in not valid (GPIO in hold time)

—

0

—

104 Minimum GPIO pulse high width

105 Minimum GPIO pulse low width

106 GPIO out rise time

2 × TC

—

10

—

13.0

107 GPIO out fall time

—

Note:

1. 0.95 V < V

< 1.05 V and Tj < 100° C, C = 50 pF

VDD_CORE

L

2. Simulation numbers-subject to change.

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

28

Freescale Semiconductor

Figure 21 shows the GPIO timing diagram.

Fsys

100

101

GPIO

(Output)

102

103

GPIO

(Input)

Valid

GPIO

(Output)

105

107

104

106

Figure 21. GPIO Timing

Table 13. JTAG Timing

1.2.6

JTAG Timing

Table 13 lists the JTAG timing.

All Frequencies

No.

Characteristics

Unit

Min

Max

108 TCK frequency of operation (1/(T × 3); maximum 10 MHz)

—

10.0

—

MHz

ns

C

109 TCK cycle time in Crystal mode

110 TCK clock pulse width measured at 1.65 V

111 TCK rise and fall times

100.0

50.0

—

3.0

—

112 Boundary scan input data setup time

113 Boundary scan input data hold time

114 TCK low to output data valid

115 TCK low to output high impedance

116 TMS, TDI data setup time

15.0

24.0

—

40.0

—

5.0

25.0

—

117 TMS, TDI data hold time

—

118 TCK low to TDO data valid

44.0

119 TCK low to TDO high impedance

—

Note:

1. 0.95 V < V

< 1.05 V and Tj < 100° C, C = 50 pF

VDD_CORE

L

2. All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.

™

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29

Figure 22 shows the text clock input timing diagram.

109

110

V

M

V

M

TCK

(Input)

IH

V

IL

111

Figure 22. Test Clock Input Timing Diagram

Figure 23 shows the debugger port timing diagram.

VIH

TCK

(Input)

VIL

112

Input Data Valid

113

Data

Inputs

114

115

114

Data

Output Data Valid

Outputs

Data

Outputs

Data

Outputs

Output Data Valid

Figure 23. Debugger Port Timing Diagram

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30

Figure 24 shows the test access port timing diagram.

VIH

117

TCK

(Input)

VIL

116

Input Data Valid

TDI

TMS

(Input)

118

TDO

(Output)

Output Data Valid

119

TDO

(Output)

118

TDO

(Output)

Output Data Valid

Figure 24. Test Access Port Timing Diagram

1.2.7

Watchdog Timer Timing

Table 14 lists the watchdog timer timings.

Table 14. Watchdog Timer Timing

No.

Characteristics

Expression

2 × T

Min

Max

Unit

120 Delay from time-out to fall of WDT, WDT_1

121 Delay from timer clear to rise of WDT, WDT_1

10.0

—

ns

c

2 × Tc

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31

1.2.8

S/PDIF Timing

Table 15 lists the S/PDIF timing.

Table 15. S/PDIF Timing

Symbol

All Frequency

Characteristics

Unit

Min

Max

—

0.7

ns

SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew:

asynchronous inputs, no specs apply

SPDIFOUT1,SPDIFOUT2 output (Load = 50pf)

• Skew

• Transition Rising

—

1.5

24.2

31.3

ns

• Transition Falling

SPDIFOUT1, SPDIFOUT2 output (Load = 30pf)

• Skew

• Transition Rising

—

1.5

13.6

18.0

• Transition Falling

SRCK period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SRCK high period

SRCK low period

STCLK period

STCLK high period

STCLK low period

Figure 25 shows the SRCK timing diagram.

srckp

srckpl

srckph

V

M

SRCK

(Output)

Figure 25. SRCK Timing

Figure 26 shows the STCLK timing diagram.

stclkp

stclkpl

stclkph

V

M

STCLK

(Input)

Figure 26. STCLK Timing

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1.2.9

EMC Timing Specifications—DSP56724

Table 16 lists the EMC timing parameters with EMC PLL enabled.

NOTE

The DSP56725 device does not have an EMC module.

Table 16. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

T

2 × T

—

3

—

160

—

ns

ps

ns

clk

c

LCLK skew to LSYNC_OUT

T

clk_skew

Input setup to LSYNC_IN (except LGTA/LUPWAIT)

Input hold from LSYNC_IN (except LGTA/LUPWAIT)

LGTA valid time

T

in_s

in_h

2

—

T

12

3

—

gta

LUPWAIT valid time

T

—

upwait

LALE negedge to LAD (address phase) invalid (address latch hold time)

LALE valid time

T

—

ale_h

T

3.8

4

—

ale

Output setup from LSYNC_IN (except LAD[23:0] and LALE)

Output hold from LSYNC_IN (except LAD[23:0] and LALE)

LAD[23:0] output setup from LSYNC_IN

LAD[23:0] output hold from LSYNC_IN

T

—

out_s

T

2

—

out_h

T

3.5

1.5

—

ad_s

T

—

ad_h

LSYNC_IN to output high impedance for LAD[23:0]

T

4.3

ad_z

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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33

Figure 27 shows the EMC signals diagram, with EMC PLL enabled.

T_clk

LCLK

T_{clk_skew}

LSYNC_OUT

T_{sync_in_skew}

LSYNC_IN

T_{in_s}

T_{in_h}

LAD[23:0] (data)

asynchronous input

LGTA

T_gta

T_upwait

asynchronous input

LUPWAIT

T_{out_s}

T_{out_h}

Output Signals

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LSDWE/LSDRAS/LSDCAS

LGPL[5:0]

T_{ad_z}

T_{ad_s}

T_{ad_h}

LAD[23:0]

T_{ale_h}

T_ale

LALE

Figure 27. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)

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Freescale Semiconductor

Table 17 lists the EMC timing parameters with EMC PLL bypassed.

Table 17. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

T

4 × T

8

—

ns

clk

c

Input setup to LCLK (except LGTA/LUPWAIT)

Input hold from LCLK (except LGTA/LUPWAIT)

LGTA valid time

T

in_s

in_h

1

–1

22

4

T

gta

LUPWAIT valid time

T

upwait

LALE negedge to LAD (address phase) invalid (address latch hold

time)

T

ale_h

LALE valid time

T

14

9

—

ns

ale

Output setup from LCLK (except LAD[23:0] and LALE)

Output hold from LCLK (except LAD[23:0] and LALE)

LAD[23:0] output setup from LCLK

T

out_s

T

8

—

out_h

T

8

—

ad_s

LAD[23:0] output hold from LCLK

T

7

—

ad_h

LCLK to output high impedance for LAD[23:0]

T

—

8.1

ad_z

Note: Negative hold time means the signal could be invalid before LCLK rising edge.

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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35

Figure 28 shows the EMC signals diagram, with EMC PLL bypassed.

T_clk

LCLK

T_{in_s}

T_{in_h}

LAD[23:0] (data)

asynchronous input

LGTA

T_gta

T_upwait

asynchronous input

LUPWAIT

T_{out_s}

T_{out_h}

Output Signals

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LSDWE/LSDRAS/LSDCAS

LGPL[5:0]

T_{ad_z}

T_{ad_s}

T_{ad_h}

LAD[23:0]

T_{ale_h}

T_ale

LALE

Figure 28. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4

Table 18 lists the EMC timing parameters with EMC PLL bypassed.

Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

T

8 × T

8

—

ns

clk

c

Input setup to LCLK (except LGTA/LUPWAIT)

Input hold from LCLK (except LGTA/LUPWAIT)

LGTA valid time

T

in_s

in_h

1

–1

42

5

T

gta

LUPWAIT valid time

T

upwait

LALE negedge to LAD (address phase) invalid (address latch hold time)

LALE valid time

T

ale_h

T

34

ale

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Freescale Semiconductor

Table 18. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

Parameter

Symbol

Min

Max

Unit

Output setup from LCLK (except LAD[23:0] and LALE)

Output hold from LCLK (except LAD[23:0] and LALE)

LAD[23:0] output setup from LCLK

LAD[23:0] output hold from LCLK

T

19

18

17

—

ns

out_s

T

out_h

T

—

ad_s

T

—

ad_h

LCLK to output high impedance for LAD[23:0]

Note:

T

17.1

ad_z

1. Negative hold time means the signal could be invalid before LCLK raising edge.

Figure 29 shows the EMC signals diagram, with EMC PLL bypassed.

T_clk

LCLK

T_{in_s}

T_{in_h}

LAD[23:0] (data)

asynchronous input

T_gta

LGTA

T_upwait

asynchronous input

LUPWAIT

T_{out_s}

T_{out_h}

Output Signals

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LSDWE/LSDRAS/LSDCAS

LGPL[5:0]

T_{ad_z}

T_{ad_s}

T_{ad_h}

LAD[23:0]

T_{ale_h}

T_ale

LALE

Figure 29. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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37

2

Functional Description and Application Information

Refer to the Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual (DSP56724RM) for detailed

functional and applications information.

3

Ordering Information

Table 19 shows the ordering information for the DSP56724/DSP56725 devices.

Table 19. Ordering Information

Device

Device Marking

Ambient Temp.

Speed

Voltage

LQFP Package

DSP56724

DSP56725

DSPB56724AG

DSPB56724CAG

DSPB56725AF

DSPB56725CAF

0° C–70° C

–40° C–85° C

0° C–70° C

250 MHz

200 MHz

250 MHz

200 MHz

1.14–1.26 V

0.95–1.05 V

1.14–1.26 V

0.95–1.05 V

20 mm × 20 mm

14 mm × 14 mm

–40° C–85° C

Contact your local Freescale sales representative for ordering information.

4

Package Information

This section provides package and pinout information.

Table 20 is a quick reference to the package outline drawings.

Table 20. Package Outline Drawings

Package See

Device

DSP56724 144-pin plastic LQFP See Section 4.2, “144-Pin Package Outline Drawing,” on page 41.

DSP56725 80-pin plastic LQFP See Section 4.3, “80-Pin Package Outline Drawing,” on page 43.

™

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Freescale Semiconductor

4.1

Pinout and Package Information

This section provides information about the available package for DSP56724 and DSP56725 devices, including diagrams of the

package pinouts. See Figure 30 for the DSP56724 pin assignments and Figure 31 for the DSP56725 pin assignments. For more

detailed information about signals, refer to the Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors Reference

Manual (DSP56724RM).

4.1.1

Pinout for DSP56724 144-Pin Plastic LQFP Package

CORE_VDD

CORE_GND

LALE

1

2

108

107

106

105

104

103

102

101

100

99

IO_GND

IO_VDD

3

WDT

PINIT/NMI

TDO

TDI

TCK

TMS

SDO2_1/SDI3_1

SDO3_1/SDI2_1

SDO4_1/SDI1_1

SDO5_1/SDI0_1

CORE_GND

CORE_VDD

FSR

LCS0

4

LCS1

5

LCS2

6

LCS3

7

LCS4

8

9

LCS5

LCS6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

LCS7

98

IO_VDD

IO_GND

CORE_VDD

CORE_GND

LWE

97

96

95

DSP56724

144-Pin

94

93

SCKR

LOE

LGPL5

LSDA10

LCKE

LCLK

LBCTL

LSDWE

LSDCAS

LGTA

92

HCKR

91

SCKT

90

FST

89

HCKT

88

SDO2/SDI3

SDO3/SDI2

SDO4/SDI1

SDO5/SDI0

SPDIFOUT1

SPDIFIN1

IO_GND

87

86

85

84

LA0

LA1

LA2

83

82

81

IO_VDD

IO_GND

PLLP1_GND

PLLP1_VDD

PLLD1_GND

PLLD1_VDD

PLLA1_GND

PLLA1_VDD

80

EXTAL

79

XTAL

78

PLLP_GND

PLLD_GND

PLLD_VDD

PLLA_GND

PLLA_VDD

PLLP_VDD

77

76

75

74

73

Figure 30. DSP56724 144-Pin Package Pinout

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39

4.1.2

Pinout for DSP56725 80-Pin Plastic LQFP Package

SDO2_3/SDI3_3

1

2

3

4

5

6

7

8

9

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

WDT

SDO3_3/SDI2_3

SDO4_3/SDI1_3

SDO5_3/SDI0_3

IO_VDD

PINIT/NMI

TDO

TDI

TCK

IO_GND

TMS

CORE_VDD

CORE_GND

CORE_VDD

SDO4/SDI1

SDO5/SDI0

IO_GND

IO_VDD

EXTAL

DSP56725

80-Pin

SPDIFIN1/SDO2_2/SDI3_2

SPDIFOUT1/SDO3_2/SDI2_2 10

SDO4_2/SDI1_2

SDO5_2/SDI0_2

FSR_3

11

12

13

14

15

16

17

18

19

20

SCKR_3

SCKT_3

GND

XTAL

PLLP_GND

PLLD_GND

PLLD_VDD

PLLA_GND

PLLA_VDD

PLLP_VDD

GND

Figure 31. DSP56725 80-Pin Package

4.1.3

Pin Multiplexing

Many pins are multiplexed, and depending on the selected configuration, can be one of three possible signals. For more about

pin multiplexing, refer to the Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual

(DSP56724RM).

™

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Freescale Semiconductor

4.2

144-Pin Package Outline Drawing

The 144-pin package outline drawing is shown in Figure 32 and Figure 33.

Figure 32. 144-Pin Package Outline Drawing

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

41

Figure 33. 144-Pin Package Outline Drawing (continued)

FIGURE NOTES:

1

All dimensions are in millimeters.

2

3

4

5

Interpret dimensions and tolerances per ASME Y.14.5M–1994

Datums B, C and D to be determined at datum plane H.

The top package body size may be smaller than the bottom package size by a maximum of 0.1 mm.

These dimensions do not include mold protrusions. The maximum allowable protrusion is 0.25 mm per side. These dimensions

are maximum body size dimensions including mold mismatch.

6

7

This dimension does not include dam bar protrusion. Protrusions shall not cause the lead width to exceed 0.35 mm. Minimum

space between protrusion and an adjacent lead shall be 0.07 mm.

These dimensions are determined at the seating plane, datum A.

™

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4.3

80-Pin Package Outline Drawing

The 80-pin package outline drawing is shown in Figure 34 and Figure 35.

Figure 34. 80-Pin Package Outline Drawing

™

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43

Figure 35. 80-Pin Package Outline Drawing (continued)

FIGURE NOTES:

1

Dimensioning and tolerancing per ASME Y.14.5M–1994.

Controlling dimension: millimeter.

2

3

Data plane H is located at the bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom

of the parting line.

4

5

6

Datum E, F and to be determined at datum plane H.

Dimensions to be determined at seating plane C.

Dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions include mold mismatch and

are determined at datum plane H.

7

Dimension does not include dambar protrusion Dambar protrusion shall not cause the lead width to exceed 0.46 mm. Minimum

space between protrusion and adjacent lead or protrusion is 0.07mm.

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

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Freescale Semiconductor

5

Product Documentation

Table 21 lists the documents that provide a complete description of the DSP56724/DSP56725 devices and are required to design

properly with the part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor,

semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source

for the latest information).

Table 21. DSP56724 / DSP56725 Documentation

Document Name

Description

Order Number

DSP56300 Family Manual

Detailed description of the 56300-family architecture and the 24-bit DSP56300FM

core processor and instruction set

DSP56724/DSP56725 Reference Manual Detailed description of memory, peripherals, and interfaces

DSP56724RM

DSP56724PB

DSP56725PB

DSP56724 Product Brief

Brief description of the DSP56724 device

Brief description of the DSP56725 device

DSP56725 Product Brief

DSP56724/DSP56725 Data Sheet

Electrical and timing specifications; pin and package descriptions DSP56724

(this document)

6

Revision History

Table 22 summarizes revisions to this document.

Table 22. Revision History

Revision

Date

Description

1

12/2008

• Modified values and removed rows in Table 4, “DC Electrical Characteristics.”

• Removed “IO_VDD_25” from Figure 4, “Prevent High Current Conditions by Applying

IO_VDD Before Core_VDD.”

• In Table 7, “Reset, Stop, Mode Select, and Interrupt Timing,” for No. 15, changed 10 to

12, and for No. 16, changed 4 to 7.

• In Table 9, “Serial Host Interface SPI Protocol Timing,” updated values.

• In Table 10, “SHI I2C Protocol Timing,” added note 7 and changed Max values for No. 50

to 1000 and 300; in addition, updated the values for note 1.

• In Table 11, “Enhanced Serial Audio Interface Timing,” for No. 82, changed 19 to 15; for

No. 83, changed 20 to 15; for No. 86, changed 18 to 25; for No. 87, changed 21 to 25.

• Removed Section 1.2.5, “Timer Timing.”

• In Table 16, “EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2),” for

“LSYNC_IN (except LGTA/LUPWAIT),” changed 2 to 3.

• In Table 17, “EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4),” for

“LCLK to output high impedance for LAD [23:0],” changed 9 to 8.1.

• In Table 18, “EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8),” for

LCLK to output high impedance for LAD [23:0],” changed 19 to 17.1

• In Table 19, “Ordering Information,” added rows for DSPB56724CAG and

DSPB56725CAF, and changed “DSPA56724AG” to “DSPB56724AG.”

0

6/2008

• Initial public release.

™

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Freescale Semiconductor

45

THIS PAGE INTENTIONALLY BLANK

™

Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 1

Freescale Semiconductor

46

THIS PAGE INTENTIONALLY BLANK

™

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Freescale Semiconductor

47

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RoHS-compliant and/or Pb-free versions of Freescale products have the functionality

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Document Number: DSP56724EC

Rev. 1

12/2008


型号：	DSP56724
厂家：	Freescale
描述：	Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors 交响乐™ DSP56724 / DSP56725多核音频处理器
文件：	总48页 (文件大小：830K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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