HC908JL8D [FREESCALE]
Addendum to MC68HC908JL8 Technical Data; 增编MC68HC908JL8技术参数
| 型号： | HC908JL8D |
| 厂家： | 
Freescale |
| 描述： | Addendum to MC68HC908JL8 Technical Data |
| 文件： | 总8页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Addendum
HC908JL8AD/D
Rev. 0, 5/2002
Addendum to
MC68HC908JL8
Technical Data
This addendum provides update and additional information to the
MC68HC908JL8 Technical Data, Rev. 2
(Motorola document number MC68HC908JL8/D)
MC68HC08JL8
MC68HC08JK8
The MC68HC08JL8 is the ROM part equivalent to the MC68HC908JL8. The
entire MC68HC908JL8 data book apply to this ROM device, with exceptions
outlined in this addendum.
Table 1. Summary of MC68HC08JL8 and MC68HC908JL8 Differences
MC68HC08JL8
8,192 bytes ROM
MC68HC908JL8
Memory ($DC00–$FBFF)
8,192 bytes FLASH
36 bytes FLASH
User vectors ($FFDC–$FFFF)
36 bytes ROM
FLASH related registers.
$FE08 — FLCR
$FFCF — FLBPR
Not used;
locations are reserved.
Registers at $FE08 and $FFCF
Mask option register ($FFD0)
Defined by mask; read only.
Read/write FLASH register.
$FC00–$FDFF: Not used.
$FE10–$FFCE: Used for
testing purposes only.
Monitor ROM
($FC00–$FDFF and $FE10–$FFCE)
Used for testing and FLASH
programming/erasing.
20-pin PDIP (MC68HC08JK8)
20-pin SOIC (MC68HC08JK8)
28-pin PDIP
20-pin PDIP (MC68HC908JK8)
20-pin SOIC (MC68HC908JK8)
28-pin PDIP
Available Packages
28-pin SOIC
28-pin SOIC
32-pin SDIP
32-pin SDIP
32-pin LQFP
32-pin LQFP
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HC908JL8AD/D
MCU Block Diagram
Memory Map
Figure 1 shows the block diagram of the MC68HC08JL8.
The MC68HC08JL8 has 8,192 bytes of user ROM from $DC00 to $FBFF, and
36 bytes of user ROM vectors from $FFDC to $FFFF. On the MC68HC908JL8,
these memory locations are FLASH memory.
Figure 2 shows the memory map of the MC68HC08JL8.
INTERNAL BUS
M68HC08 CPU
‡
¥
#
PTA7/KBI7**
PTA6/KBI6**
PTA5/KBI5**
PTA4/KBI4**
PTA3/KBI3**
PTA2/KBI2**
PTA1/KBI1**
PTA0/KBI0**
KEYBOARD INTERRUPT
MODULE
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT (ALU)
‡
‡
‡
‡
‡
‡
8-BIT ANALOG-TO-DIGITAL
CONVERTER MODULE
##
CONTROL AND STATUS REGISTERS — 64 BYTES
USER ROM — 8,192 BYTES
2-CHANNEL TIMER INTERFACE
MODULE 1
PTB7/ADC7
PTB6/ADC6
PTB5/ADC5
PTB4/ADC4
PTB3/ADC3
PTB2/ADC2
PTB1/ADC1
PTB0/ADC0
USER RAM — 256 BYTES
2-CHANNEL TIMER INTERFACE
MODULE 2
MONITOR ROM — 447 BYTES
BREAK
MODULE
USER ROM VECTORS — 36 BYTES
#
ADC12/T2CLK
CRYSTAL OSCILLATOR
OSC1
SERIAL COMMUNICATIONS
INTERFACE MODULE
†‡
PTD7/RxD**
†‡
¥
PTD6/TxD**
PTD5/T1CH1
OSC2/RCCLK
RC OSCILLATOR
PTD4/T1CH0
‡
POWER-ON RESET
MODULE
INTERNAL OSCILLATOR
SYSTEM INTEGRATION
MODULE
PTD3/ADC8
‡
PTD2/ADC9
PTD1/ADC10
PTD0/ADC11
##
#
LOW-VOLTAGE INHIBIT
MODULE
* RST
PTE1/T2CH1
PTE0/T2CH0
EXTERNAL INTERRUPT
MODULE
* IRQ
COMPUTER OPERATING
PROPERLY MODULE
* Pin contains integrated pull-up device.
** Pin contains programmable pull-up device.
† 25mA open-drain if output pin.
VDD
POWER
VSS
‡ LED direct sink pin.
¥ Shared pin: OSC2/RCCLK/PTA6/KBI6.
# Pins available on 32-pin packages only.
## Pins available on 28-pin and 32-pin packages only.
ADC REFERENCE
Shaded blocks indicate differences to MC68HC908JL8
Figure 1. MC68HC08JL8 Block Diagram
Addendum to MC68HC908JL8 Technical Data
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HC908JL8AD/D
MC68HC08JL8 MC68HC08JK8
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$005F
RESERVED
32 BYTES
$0060
↓
$015F
RAM
256 BYTES
$0160
↓
$DBFF
UNIMPLEMENTED
55,968 BYTES
$DC00
↓
$FBFF
ROM
8,192 BYTES
$FC00
↓
$FDFF
UNIMPLEMENTED
512 BYTES
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (RSR)
RESERVED
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED
RESERVED
$FE09
↓
RESERVED
$FF0B
$FE0C
$FE0D
$FE0E
$FE0F
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
RESERVED
$FE10
↓
$FFCE
MONITOR ROM
447 BYTES
$FFCF
$FFD0
RESERVED
MASK OPTION REGISTER (MOR) — READ ONLY
$FFD1
↓
$FFDB
RESERVED
11 BYTES
$FFDC
↓
$FFFF
USER ROM VECTORS
36 BYTES
Figure 2. MC68HC08JL8 Memory Map
Addendum to MC68HC908JL8 Technical Data
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HC908JL8AD/D
Reserved Registers
The two registers at $FE08 and $FFCF are reserved locations on the
MC68HC08JL8.
On the MC68HC908JL8, these two locations are the FLASH control register
and the FLASH block protect register respectively.
Mask Option
Register
The mask option register at $FFD0 is read only. The value is defined by mask
option (hard-wired connections) specified at the time as the ROM code
submission.
On the MC68HC908JL8, the MOR is implemented as a FLASH, which can be
programmed, erased, and read.
Monitor ROM
The monitor program (monitor ROM: $FE10–$FFCE) on the MC68HC08JL8 is
for device testing only. $FC00–$FDFF are unused.
Electrical
Specifications
Electrical specifications for the MC68HC908JL8 apply to the MC68HC08JL8,
except for the parameters indicated below.
DC Electrical
Characteristics
Table 2. DC Electrical Characteristics (5V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
VDD supply current, fOP = 8MHz
RC oscillator option
Values same as, and characterized from
MC68HC908JL8, but not tested.
IDD
3.55 (3.60)(3)
3.66 (3.75)
VTRIPF
VTRIPR
Low-voltage inhibit, trip falling voltage
Low-voltage inhibit, trip rising voltage
4.02 (4.25)
4.13 (4.40)
4.48 (4.48)
4.59 (4.63)
V
V
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. The numbers in parenthesis are MC68HC908JL8 values.
Table 3. DC Electrical Characteristics (3V)
Characteristic(1)
Typ(2)
Symbol
Min
Max
Unit
VDD supply current, fOP = 4MHz
RC oscillator option
Values same as, and characterized from
MC68HC908JL8, but not tested.
IDD
Low-voltage inhibit, trip voltage
(No hysteresis implemented for 3V LVI)
2.1 (2.18)(3)
VLVI3
2.4 (2.49)
2.69 (2.68)
V
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. The numbers in parenthesis are MC68HC908JL8 values.
Addendum to MC68HC908JL8 Technical Data
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HC908JL8AD/D
MC68HC08JL8 MC68HC08JK8
14
12
10
8
)
H
C
= 10 pF
EXT
MCU
(
5V @ 25°C
OSC1
CLK
R
f
,
y
6
n
V
DD
4
REXT
CEXT
q
e
r
MC68HC908JL8
MC68HC08JL8
2
RCf
0
0
10
20
Resistor, R
30
(k
40
50
Ω)
EXT
Figure 3. RC vs. Frequency (5V @25°C)
14
12
10
8
CEXT = 10 pF
MCU
3V @ 25°C
OSC1
6
V
DD
REXT
CEXT
4
MC68HC908JL8
MC68HC08JL8
2
0
0
10
20
30
40
50
Resistor, REXT (kΩ)
Figure 4. RC vs. Frequency (3V @25°C)
Memory
Characteristics
Table 4. Memory Characteristics
Characteristic
RAM data retention voltage
Notes:
Symbol
Min
Max
Unit
VRDR
1.3
—
V
Since MC68HC08JL8 is a ROM device, FLASH memory electrical characteristics do not apply.
Addendum to MC68HC908JL8 Technical Data
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HC908JL8AD/D
MC68HC08JL8
Order Numbers
These part numbers are generic numbers only. To place an order, ROM code
must be submitted to the ROM Processing Center (RPC).
Table 5. MC68HC08JL8 Order Numbers
Operating
MC Order Number
MC68HC08JK8CP
Package
Temperature Range
–40 °C to +85 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +125 °C
–40 °C to +85 °C
–40 °C to +125 °C
20-pin PDIP
MC68HC08JK8MP
MC68HC08JK8CDW
MC68HC08JK8MDW
MC68HC08JL8CP
MC68HC08JL8MP
MC68HC08JL8CDW
MC68HC08JL8MDW
MC68HC08JL8CSP
MC68HC08JL8MSP
MC68HC08JL8CFA
MC68HC08JL8MFA
20-pin SOIC
28-pin PDIP
28-pin SOIC
32-pin SDIP
32-pin LQFP
NOTE: Temperature grade "M" is available for VDD = 5V only.
Addendum to MC68HC908JL8 Technical Data
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HC908JL8AD/D
AMENDMENTS TO MC68HC908JL8/D, REV. 2
AMENDMENTS TO MC68HC908JL8/D, REV. 2
Keyboard Interrupt
Page 243, Figure 15-2. Keyboard Interrupt Block Diagram — Replace with
the following block diagram:
INTERNAL BUS
NOTE:
To prevent false interrupts, user should use software
to debounce keyboard interrupt inputs.
VECTOR FETCH
DECODER
KBI0
ACKK
V
DD
KEYF
RESET
CLR
.
D
Q
SYNCHRONIZER
KEYBOARD
INTERRUPT
REQUEST
KBIE0
.
CK
TO PULLUP ENABLE
.
KEYBOARD
INTERRUPT FF
IMASKK
KBI7
MODEK
KBIE7
TO PULLUP ENABLE
Computer Operating
Properly (COP)
Page 254, 16.8.2 Stop Mode — Replace the two paragraphs:
From:
Stop mode turns off the ICLK input to the COP if the STOP_ICLKDIS bit is set
in configuration register 2 (CONFIG2). Service the COP immediately before
entering or after exiting stop mode to ensure a full COP timeout period after
entering or exiting stop mode.
After reset, the STOP_ICLKDIS bit is clear by default and ICLK is enabled
during stop mode.
To:
Stop mode turns off the ICLK input to the COP and clears the COP prescaler.
Service the COP immediately before entering or after exiting stop mode to
ensure a full COP timeout period after entering or exiting stop mode.
To prevent inadvertently turning off the COP with a STOP instruction, a
configuration option is available that disables the STOP instruction. When the
STOP bit in the configuration register has the STOP instruction is disabled,
execution of a STOP instruction results in an illegal opcode reset.
Addendum to MC68HC908JL8 Technical Data
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Semiconductor was negligent regarding the design or manufacture of the part.
HC908JL8AD/D
Rev. 0
5/2003
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