MAC7126CFU50 [FREESCALE]
Microcontroller Family Hardware Specifications; 单片机系列硬件规格
| 型号： | MAC7126CFU50 |
| 厂家： | 
Freescale |
| 描述： | Microcontroller Family Hardware Specifications |
| 文件： | 总56页 (文件大小：1236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAC7100EC
Rev. 1.2, 02/2006
Freescale Semiconductor
Advance Information
MAC7100 Microcontroller Family
Hardware Specifications
Covers MAC7101, MAC7106, MAC7111, MAC7116, MAC7121,
1
MAC7126, MAC7131, MAC7136, MAC7141
32-bit Embedded Controller Division
1. With preliminary information on MAC7112, MAC7122, MAC7142 devices.
Table of Contents
This document provides electrical specifications, pin
assignments, and package diagrams for MAC7100
family of microcontroller devices. For functional
characteristics, refer to the MAC7100 Microcontroller
Family Reference Manual (MAC7100RM).
1 Overview.................................................................1
2 Ordering Information...............................................2
3 Electrical Characteristics.........................................4
3.1 Parameter Classification......................................4
3.2 Absolute Maximum Ratings.................................4
3.3 ESD Protection and Latch-up Immunity ..............5
3.4 Operating Conditions...........................................6
3.5 Input/Output Characteristics................................7
3.6 Power Dissipation and Thermal Characteristics..8
3.7 Power Supply ....................................................11
3.8 Clock and Reset Generator...............................15
3.9 External Bus Timing ..........................................20
3.10 Analog-to-Digital Converter...............................24
3.11 Serial Peripheral Interface.................................29
3.12 FlexCAN Interface .............................................32
3.13 Common Flash Module .....................................32
4 Device Pin Assignments .......................................36
4.1 MAC7141 Pin Diagram......................................41
4.2 MAC7142 Pin Diagram......................................42
4.3 MAC7121 / MAC7126 Pin Diagram...................43
4.4 MAC7122 Pin Diagram......................................44
4.5 MAC7101 / MAC7106 Pin Diagram...................45
4.6 MAC7111 / MAC7116 Pin Diagram...................46
4.7 MAC7112 Pin Diagram......................................47
4.8 MAC7131 Pin Diagram......................................48
4.9 MAC7136 Pin Diagram......................................49
5 Mechanical Information.........................................50
Revision History....................................................51
1 Overview
The MAC7100 Family of microcontrollers (MCUs) are
members of a pin-compatible family of 32-bit
Flash-memory-based devices developed specifically for
embedded automotive applications. The pin-compatible
family concept enables users to select between different
memory and peripheral options for scalable designs. All
MAC7100 Family members are composed of a 32-bit
ARM7TDMI-S™ central processing unit, up to 1 Mbyte
of embedded Flash EEPROM for program storage, up to
32 Kbytes of embedded Flash for data and/or program
storage, and up to 48 Kbytes of RAM. The family is
implemented with an enhanced DMA (eDMA) controller
to improve performance for transfers between memory
and many of the on-chip peripherals. The peripheral set
includes asynchronous serial communications interfaces
(eSCI), serial peripheral interfaces (DSPI),
This document contains information on a new product under development. Freescale
Semiconductor reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2004-2006. All rights reserved.
• Preliminary
Ordering Information
2
inter-integrated circuit (I C™) bus controllers, FlexCAN interfaces, an enhanced modular I/O subsystem
(eMIOS), 10-bit analog-to-digital converter (ATD) module(s), general-purpose timers (PIT) and two
special-purpose timers (RTI and SWT). The peripherals share a large number of general purpose
input-output (GPIO) pins, all of which are bidirectional and available with interrupt capability to trigger
wake-up from low-power chip modes. Refer to Table 2 for a comparison of family members and
availability of peripheral modules on each device.
The use of a PLL allows power drain and performance to be balanced to best fit requirements. The
operating frequency of devices in the family is up to a maximum of 50 MHz. The internal data paths
between the CPU core, eDMA, memory and peripherals are all 32 bits wide, further improving
performance for 32-bit applications. The MAC7111, MAC7116, MAC7131 and MAC7136 also offer a
16-bit wide external data bus with 22 address lines. The family of devices is capable of operating over a
junction temperature range of –40° C to 150° C.
2 Ordering Information
Temperature Option
= –40° C to 85° C
= –40° C to105° C
M AC 7 1 0 1 C PV 50 xx
C
V
Qualification Status
Core Code
M = –40° C to125° C
Core Number
Generation / Family
Package Option
Package Option
FU = 100 LQFP
AF = 100 LQFP, RoHS
PV = 112 / 144 LQFP
AG = 112 / 144 LQFP, RoHS
VF = 208 MAP BGA
Device Number
Temperature Range
Package Identifier
Speed (MHz)
Optional Package Identifiers
VM= 208 MAP BGA, RoHS
Figure 1. Order Part Number Example
The mask set of a device is marked with a four-character code consisting of a letter, two numerical digits,
and a letter, for example L49P. Slight variations to the mask set identification code may result in an
optional numerical digit preceding the standard four-character code, for example 0L49P.
Table 1. MAC7100 Family Mask Set to Part Number Correspondence
Mask Set
Status
Part Number(s)
0L49P
1L49P
0L47W
1L47W
0L61W
0L38Y
1L38Y
Engineering samples
Limited production, pre-qualification
Limited production, pre-qualification
Fully-qualified, production
Engineering samples
PAC7101, PAC7111, PAC7121, PAC7131, PAC7141
PAC7101, PAC7111, PAC7121, PAC7131, PAC7141
PAC7101, PAC7111, PAC7121, PAC7131, PAC7141
MAC7101, MAC7111, MAC7121, MAC7131, MAC7141
PAC7112, PAC7122, PAC7142
Engineering samples
PAC7106, PAC7116, PAC7126, PAC7136
Fully-qualified, production
MAC7106, MAC7116, MAC7126, MAC7136
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
2
Freescale Semiconductor
OrderingInformation
Table 2. MAC7100 Family Device Derivatives
Module Options
Program Flash
Data Flash
512 KBytes
256 KBytes
32 KBytes
1 MByte
SRAM
32 KBytes
—
16 KBytes
—
48 KBytes
External Bus
ATD Modules 1
—
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
—
Yes
—
—
Yes
—
—
Yes
Yes
—
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes 2
Yes 2
Yes
A
B
A
B
C
D
A
B
C
D
A
B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
CAN Modules
eSCI Modules
DSPI Modules
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
—
Yes
Yes
—
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes 3
Yes
Yes
Yes
Yes
—
—
—
—
Yes
Yes
Yes
—
Yes
Yes
Yes
—
Yes
Yes
Yes
—
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes 3
Yes
Yes
Yes
Yes
Yes 3
I2C Module
eMIOS Module
Timer Module
Yes
16 channels, 16-bit
10 channels, 24-bit
A
B
C
D
E
F
10
16
16
16
10
15
16
16
4
16
16
16
16
16
16
16
16
—
10
15
1
4
16
—
10
16
16
16
16
16
16
16
16
—
10
15
1
16
16
16
16
16
16
16
16
16
144
12
16
1
16
—
12
10 4
16 4
11 4
16 4
10 4
11
16
16
16
—
10
16
16
10
—
10
11
16
16
16
—
16
16
16
16
16
16
16
16
16
16
16
16
G
H
I
16
16
16
16
10
16
16
—
—
16
—
16
—
—
—
—
—
—
—
—
—
—
—
Total (max.)
Package
112 4
112 4
85 4
128 4
72 4
112
144
85
112
72
100
112
144
112
144
85
112
144
144
112
208
100
208
LQFP LQFP LQFP
BGA
LQFP LQFP LQFP LQFP LQFP LQFP LQFP
BGA
NOTES:
1. 16 channels, 8/10-bit, per module.
2. Four additional chip selects available.
3. PB11 / PCS2_B not available on non-L49P-mask devices; PB10 / PCS5_B / PCSS_B not available on mask L47W devices.
4. Reduce these values by one for mask set L49P devices (PD2 is not available for general-purpose use).
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
3
Preliminary
Electrical Characteristics
3 Electrical Characteristics
This section contains electrical information for MAC7100 Family microcontrollers. The information is
preliminary and subject to change without notice.
MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any
voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done
to verify operation at intermediate supply voltage levels.
3.1 Parameter Classification
The electrical parameters shown in this appendix are derived by various methods. To provide a better
understanding to the designer, the following classification is used. Parameters are tagged accordingly in
the column labeled “C” of the parametric tables, as appropriate.
Table 3. Parametric Value Classification
P
C
Parameters guaranteed during production testing on each individual device.
Parameters derived by the design characterization and by measuring a statistically relevant sample size across
process variations.
T
Parameters derived by design characterization on a small sample size from typical devices under typical conditions
(unless otherwise noted). All values shown in the typical column are within this classification, even if not so tagged.
D
Parameters derived mainly from simulations.
3.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. Functional operation outside these maximums is not
guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device.
MAC7100 Family devices contain circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs
1
1
are tied to an appropriate logic voltage level (for example, either V 5 or V 5 ).
SS
DD
Table 4. Absolute Maximum Ratings
Num
Rating
Symbol
DDX
Min
Max
Unit
A1a I/O Drivers Supply Voltage
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+6.0
+3.0
+3.0
+6.0
+6.0
+0.3
+0.3
+6.0
V
V
V
V
V
V
V
V
A2
A3
A4
A5
A6
A7
A8
Digital Logic Supply Voltage 1
VDD2.5
1
PLL Supply Voltage
VDDPLL
Analog Supply Voltage
Analog Reference
VDD
VRH, VRL
ΔVDDX
A
Voltage difference VDDX to VDD
A
Voltage difference VSSX to VSS
A
ΔVSSX
Voltage difference VRH – VRL
VRH – VRL
1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
4
Freescale Semiconductor
ElectricalCharacteristics
Table 4. Absolute Maximum Ratings (continued)
Num
Rating
Symbol
Min
Max
Unit
A9
Voltage difference VDDA – VRH
VDDA – VRH
VIN
–0.3
–0.3
–0.3
–0.3
+6.0
+6.0
+3.0
V
V
V
V
A10 Digital I/O Input Voltage
A11 XFC, EXTAL, XTAL inputs
A12 TEST input
VILV
2
VTEST
—
Instantaneous Maximum Current 3
A13
A14
A15
A16
Single pin limit for XFC, EXTAL, XTAL 4
Single pin limit for all digital I/O pins 5
Single pin limit for all analog input pins 5
Single pin limit for TEST 2
IDL
ID
–25
–25
+25
+25
+25
0
mA
mA
mA
mA
°C
IDA
IDT
Tstg
–25
–0.25
–65
A17 Storage Temperature Range
NOTES:
+155
1. The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The
absolute maximum ratings apply when the device is powered from an external source.
2. This pin is clamped low to VSSX, but not clamped high, and must be tied low in applications.
3. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
use the larger of the calculated values using VPOSCLAMP = VDDA + 0.3V and VNEGCLAMP = –0.3 V.
4. These pins are internally clamped to VSSPLL and VDDPLL.
5. All I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
3.3 ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise.
Table 5. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Human Body
Series Resistance
R1
C
1500
100
Ohm
pF
Storage Capacitance
Number of Pulses per pin
positive
—
—
3
negative
3
Machine
Series Resistance
R1
C
0
Ohm
pF
Storage Capacitance
200
Number of Pulse per pin
positive
—
—
3
negative
3
Latch-up
Minimum input voltage limit
Maximum input voltage limit
–2.5
7.5
V
V
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
5
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
Num
C
Rating
Symbol
Min
Max
Unit
B1
B2
B3
B4
C Human Body Model (HBM)
C Machine Model (MM)
VHBM
VMM
VCDM
ILAT
2000
200
—
—
—
V
V
C Charge Device Model (CDM)
500
V
C Latch-up Current at TA = 125°C
mA
positive
negative
+100
–100
—
—
B5
C Latch-up Current at TA = 27°C
ILAT
mA
positive
negative
+200
–200
3.4 Operating Conditions
Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature
rating of the device (C, V, M) with respect to ambient temperature (T ) and junction temperature (T ). For
A
J
power dissipation calculations refer to Section 3.6, “Power Dissipation and Thermal Characteristics.”
Table 7. MAC7100 Family Device Operating Conditions
Num
Rating
Symbol
DDX
DD2.5
VDDPLL
DDA
VDDX
VSSX
Min
Typ
Max
Unit
C1 I/O Drivers Supply Voltage
C2 Digital Logic Supply Voltage 1
C3 PLL Supply Voltage 1
V
3.15
2.35
2.35
3.15
–0.1
–0.1
0.5
5
2.5
2.5
5
5.5
2.75
2.75
5.5
0.1
0.1
16
V
V
V
V
C4 Analog Supply Voltage
V
V
C5 Voltage Difference VDDX to VDD
A
Δ
0
V
C6 Voltage Difference VSSX to VSS
A
Δ
0
V
2
C7 Oscillator Frequency
fOSC
fSYS
TJ
—
—
—
25
MHz
MHz
°C
°C
2
C8 System Clock Frequency
C9a MAC71xxC Operating Junction Temperature Range 3
0.5
50
–40
–40
110
85
3
C9b
C10a MAC71xxV Operating Junction Temperature Range
C10b Operating Ambient Temperature Range
C11a MAC71xxM Operating Junction Temperature Range
Operating Ambient Temperature Range
TA
3
3
TJ
TA
–40
–40
—
130
105
°C
°C
25
3
3
TJ
TA
–40
–40
—
150
125
°C
°C
C11b
Operating Ambient Temperature Range
25
NOTES:
1. These ratings apply only when the VREG is disabled and the device is powered from an external source.
2. Throughout this document, tOSC refers to 1 ÷ fOSC, and tSYS refers to 1 ÷ fSYS
.
3. Refer to Section 3.6, “Power Dissipation and Thermal Characteristics,” for more details about the relation between
ambient temperature TA and device junction temperature TJ.
3.4.1 Input/Output Pins
The I/O pins operate at a nominal level of 3.3 V to 5 V. This class of pins is comprised of the clocks, control
and general purpose/peripheral pins. The internal structure of these pins is identical; however, some
functionality may be disabled (for example, for analog inputs the output drivers, pull-up/down resistors
are permanently disabled).
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
6
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
3.4.2 Oscillator Pins
The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5V.
3.5 Input/Output Characteristics
This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All
parameters are not always applicable; for example, not all pins feature pull up/down resistances.
Table 8. 5.0 V I/O Characteristics
Conditions shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
D1a P Input High Voltage
VIH
0.65 ×
—
—
V
VDD5 1
D1b T Input High Voltage
D2a P Input Low Voltage
D2b T Input Low Voltage
D3 C Input Hysteresis
VIH
VIL
VIL
—
—
—
—
—
VDD5 +
0.3 1
V
V
V
0.35 ×
VDD5 1
VSS5 –
0.3 1
—
VHYS
Iin
—
–1 2
250
—
—
1 2
mV
D4 P Input Leakage Current (pins in high impedance input mode)
in = VDD5 or VSS5 1
μA
V
D5 P Output High Voltage (pins in output mode)
Partial Drive I = –2mA
VOH
VDD5 –
0.8
—
—
—
V
V
OH
= –10mA
Full Drive I
OH
D6 P Output Low Voltage (pins in output mode)
Partial Drive I = +2mA
VOL
—
0.8
OL
= +10mA
Full Drive I
OL
D7 P Internal Pull Up Device Current,
tested at VIL Max.
D8 P Internal Pull Up Device Current,
tested at VIH Min.
D9 P Internal Pull Down Device Current,
tested at VIH Min.
D10 P Internal Pull Down Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
IPDL
Cin
—
–10
—
—
—
—
—
–130
—
μA
μA
μA
μA
130
—
10
D11 D Input Capacitance
—
6
—
pF
D12 T Injection current 3
Single Pin limit
—
mA
IICS
IICP
–2.5
–25
2.5
25
Total Device Limit. Sum of all injected currents
D13 P Port Interrupt Input Pulse filtered 4
D14 P Port Interrupt Input Pulse passed 4
NOTES:
tPULSE
tPULSE
—
—
—
3
μs
μs
10
—
1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half
for each 8°C to 12°C in the temperature range from 50°C to 125°C.
3. Refer to Section 3.7.1, “Current Injection,” for more details
4. Parameter only applies in STOP or Pseudo STOP mode.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
7
Preliminary
Electrical Characteristics
Table 9. 3.3 V I/O Characteristics
Conditions shown in Table 7, with VDDX = 3.3 V –5%/+10% and a temperature maximum of +140°C unless otherwise noted.
Num C
Rating
Symbol
Min
Typ
Max
Unit
E1a P Input High Voltage
VIH
0.65 ×
V
—
—
V
DD5 1
—
E1b T Input High Voltage
E2a P Input Low Voltage
E2b T Input Low Voltage
E3 C Input Hysteresis
VIH
VIL
VIL
—
—
—
VDD5 +
0.3 1
V
V
V
—
0.35 ×
VDD5 1
VSS5 –
0.3 1
—
VHYS
Iin
—
250
—
—
mV
E4
P
Input Leakage Current (pins in high impedance input mode)
in = VDD5 or VSS5 1
–1 2
1 2
μA
V
E5 P Output High Voltage (pins in output mode)
Partial Drive I = –0.75mA
VOH
VDD5 –
0.4
—
—
—
V
V
OH
= –4.5mA
Full Drive I
OH
E6 P Output Low Voltage (pins in output mode)
Partial Drive I = +0.9mA
VOL
—
0.4
OL
= +5.5mA
Full Drive I
OL
E7 P Internal Pull Up Device Current,
tested at VIL Max.
IPUL
IPUH
IPDH
IPDL
Cin
—
–6
—
6
—
—
—
—
–60
—
μA
μA
μA
μA
E8 P Internal Pull Up Device Current,
tested at VIH Min.
E9 P Internal Pull Down Device Current,
tested at VIH Min.
60
—
E10 P Internal Pull Down Device Current,
tested at VIL Max.
E11 D Input Capacitance
—
6
—
pF
E12 T Injection current 3
Single Pin limit
—
mA
IICS
IICP
–2.5
–25
2.5
25
Total Device Limit. Sum of all injected currents
E13 P Port Interrupt Input Pulse filtered 4
E14 P Port Interrupt Input Pulse passed 4
NOTES:
tPULSE
tPULSE
—
—
—
3
μs
μs
10
—
1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half
for each 8°C to 12°C in the temperature range from 50°C to 125°C.
3. Refer to Section 3.7.1, “Current Injection,” for more details
4. Parameter only applies in STOP or Pseudo STOP mode.
3.6 Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
8
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
Note that the JEDEC specification reserves the symbol R
ambient thermal resistance on a 1s test board in natural convection environment. R
or θ (Theta-JA) strictly for junction-to-
JA
θJA
or θ
θJMA
JMA
(Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for
junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the
generic name, θ , will continue to be commonly used.
JA
The average chip-junction temperature (T ) in °C is obtained from the formula:
J
TJ = TA + PD ⋅ ΘJA
Eqn. 1
where
T = Junction Temperature ( C)
°
°
J
TA = Ambient Temperature ( C)
PD = Total Chip Power Dissipation (W)
ΘJA = Package Thermal Resistance ( C/W)
°
The total power dissipation is calculated as:
PD = PINT + PIO
Eqn. 2
where
PINT = Chip Internal Power Dissipation (W)
PIO = Input / Output Power Dissipation (W)
Two cases must be considered for P
:
INT
1. Internal voltage regulator enabled:
PINT = (IDDR × VDDR) + (IDDA × VDDA)
Eqn. 3
Eqn. 4
Eqn. 5
Eqn. 6
Eqn. 7
2. Internal voltage regulator disabled (V R = V R = system ground):
DD
SS
PINT = (IDD2.5 × VDD2.5) + (IDDPLL × VDDPLL) + (IDDA × VDDA)
P
is the sum of all output currents on input/output pins associated with V X:
IO
DD
2
PIO
=
RDSON ⋅ (IIO )
i
∑
i
where
or
VOL
RDSON = --------- (for outputs driven low)
IOL
VDDX – VOH
RDSON = ------------------------------ (for outputs driven high)
IOL
Table 10. Thermal Resistance 1/8 Simulation Model Packaging Parameters
Component
Mold Compound
Leadframe (Copper)
Die Attach
Conductivity
0.9 W/m K
263 W/m K
1.7 W/m K
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
9
Electrical Characteristics
3.6.1 Thermal Resistance Simulation Details
Table 11. Thermal Resistance for Case Outline 983–02, 100 Lead 14x14 mm LQFP, 0.5 mm Pitch
Rating
Environment
Symbol
Value
Unit
Comments
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
R
44
34
37
29
18
7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
θJA
R
θJMA
R
R
R
θJMA
θJMA
θJB
θJC
Junction to Case
Junction to Package Top
R
5
6
Natural Convection
Ψ
2
JT
Table 12. Thermal Resistance for Case Outline 987–01, 112 Lead 20x20 mm LQFP, 0.65 mm Pitch
Rating
Environment
Symbol
Value
Unit
Comments
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
R
42
34
35
30
22
7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
θJA
R
θJMA
R
θJMA
R
θJMA
R
θJB
θJC
Junction to Case
Junction to Package Top
R
5
6
Natural Convection
Ψ
2
JT
Table 13. Thermal Resistance for Case Outline 918–03, 144 Lead 20x20 mm LQFP, 0.5 mm Pitch
Rating
Environment
Symbol
Value
Unit
Comments
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
R
42
34
35
30
22
7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
θJA
R
θJMA
R
θJMA
R
θJMA
R
θJB
θJC
Junction to Case
Junction to Package Top
R
5
6
Natural Convection
Ψ
2
JT
Table 14. Thermal Resistance for Case Outline 1159A-01, 208 Lead 17x17 mm MAP BGA, 1.0 mm Pitch
Rating
Environment
Symbol
Value
Unit
Comments
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
R
46
29
38
26
19
7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
θJA
R
θJMA
R
θJMA
R
θJMA
R
θJB
θJC
Junction to Case
Junction to Package Top
R
5
6
Natural Convection
Ψ
2
JT
Comments:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board at the center lead. For fused lead packages, the adjacent lead is used.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC
JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
10
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
3.7 Power Supply
The MAC71xx Family utilizes several pins to supply power to the oscillator, PLL, digital core, I/O ports
and ATD. In the context of this section, V 5 is used for V A, V R or V X; V 5 is used for V A,
DD
DD
DD
DD
SS
SS
V R or V X unless otherwise noted. I 5 denotes the sum of the currents flowing into the V A,
SS
SS
DD
DD
V
X, and V R. V is used for V 2.5, and V PLL, V is used for V 2.5 and V PLL. I is
DD
DD DD DD DD SS SS SS DD
used for the sum of the currents flowing into V 2.5 and V PLL.
DD
DD
3.7.1 Current Injection
The power supply must maintain regulation within the V 5 or V 2.5 operating range during
DD
DD
instantaneous and operating maximum current conditions. If positive injection current (V > V 5) is
in
DD
greater than I 5, the injection current may flow out of V 5 and could result in the external power supply
DD
DD
going out of regulation. It is important to ensure that the external V 5 load will shunt current greater than
DD
the maximum injection current. The greatest risk will be when the MCU is consuming very little power
(for example, if no system clock is present, or if the clock rate is very low).
3.7.2 Power Supply Pins
The V R – V R pair supplies the internal voltage regulator. The V A – V A pair supplies the A/D
DD
SS
DD
SS
converter and the reference circuit of the internal voltage regulator. The V X – V X pair supplies the
DD
SS
I/O pins. V PLL – V PLL pair supplies the oscillator and PLL.
DD
SS
All V X pins are internally connected by metal. All V X pins are internally connected by metal. All
DD
SS
V 2.5 pins are internally connected by metal. V A, V X and V R as well as V A, V X and V R
SS
DD
DD
DD
SS
SS
SS
are connected by anti-parallel diodes for ESD protection.
3.7.3 Supply Current Characteristics
Table 15 and Table 16 list supply current characteristics for MAC71x1 and MAC71x6 devices at 40 MHz
and 50 MHz operation, respectively. Characteristics for MAC71x2 devices are to be determined (TBD).
All current measurements are without output loads. Unless otherwise noted the currents are measured in
single chip mode, internal voltage regulator enabled at the specified system frequency, using a 4 MHz
oscillator in low power mode. Production testing is performed using a square wave signal at the EXTAL
input. In expanded modes, the currents are highly dependent on the load and duty cycle on the address,
data and control signals, thus no general numbers can be given. A good estimate is to take the single chip
currents and add the currents due to the external loads.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
11
Preliminary
Electrical Characteristics
Table 15. MAC71x1/6 Device Supply Current Characteristics – 40 MHz
1
Conditions shown in Table 7, with fSYS = 40 MHz.
Num Rating
C
Symbol
DDRreg
Typ
Max
Unit
F1 P Run Supply Current, Single Chip
F2 C Doze Supply Current
I
100
130
mA
IDDDreg
Run ≥ Doze ≥ Pseudo Stop
F3 P Pseudo Stop Supply Current –40° C 2
I
DDPSreg
400 / 500 3
400 / 500 3
800 / 1000 3
600 / 700 3
600 / 700 3
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
(OSC on)
P
25° C 2
85° C 2
C
2000 / 2500 3
C
105° C 2
125° C 2
–40° C 2
25° C 2
1200 / 1500 3 3500 / 4000 3
1500 / 2000 3 5500 / 6000 3
P
F4 P Stop Supply Current
IDDSreg
30
30
150
150
(TJ = TA assumed)
P
C
C
P
85° C 2
330
470
660
2500
3500
5000
105° C 2
125° C 2
NOTES:
1. MAC71x2 characteristics are to be determined (TBD).
2. 85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.
3. RTI disabled / enabled.
1
Table 16. MAC71x1/6 Device Supply Current Characteristics – 50 MHz
Conditions shown in Table 7, with fSYS = 50 MHz.
Num
C
Rating
Symbol
Typ
Max
Unit
G1 P Run Supply Current, Single Chip
G2 C Doze Supply Current
IDDRreg
120
150
mA
I
DDDreg
Run ≥ Doze ≥ Pseudo Stop
G3 P Pseudo Stop Supply Current –40° C 2
I
DDPSreg
400 / 500 3
400 / 500 3
800 / 1000 3
600 / 700 3
600 / 700 3
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
(OSC on)
P
25° C 2
85° C 2
C
2000 / 2500 3
C
105° C 2
125° C 2
–40° C 2
25° C 2
1200 / 1500 3 3500 / 4000 3
1500 / 2000 3 5500 / 6000 3
P
G4 P Stop Supply Current
IDDSreg
30
30
150
150
(TJ = TA assumed)
P
C
C
P
85° C 2
330
470
660
2500
3500
5000
105° C 2
125° C 2
NOTES:
1. MAC71x2 characteristics are to be determined (TBD).
2. 85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.
3. RTI disabled / enabled.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
12
Freescale Semiconductor
ElectricalCharacteristics
3.7.4 Voltage Regulator Characteristics
Table 17. VREG Operating Conditions
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
H1
H2
P Input Voltages
VVDDRA
3.15
—
5.5
V
P Output Voltage, Digital Logic
Full Performance Mode
Reduced Power Mode
Shutdown Mode
VDD2.5
2.45
1.60
2.5
2.5
2.75
2.75
V
V
V
1
1
1
—
—
—
H3
H4
P Output Voltage, PLL
Full Performance Mode
Reduced Power Mode 2
Reduced Power Mode 3
Shutdown Mode
VDDPLL
2.35
2.00
1.60
2.5
2.5
2.5
2.75
2.75
2.75
V
V
V
V
1
1
1
—
—
—
P Low Voltage Interrupt 4
Assert Level
VLVIA
VLVID
4.10
4.25
4.37
4.52
4.66
4.77
V
V
Negate Level
H5
H6
P Low Voltage Reset 5
Assert Level
VLVRA
2.25
2.35
—
V
P Power On Reset 6
Assert Level
VPORA
VPORD
0.97
—
—
—
—
2.05
V
V
Negate Level
NOTES:
1. High impedance output.
2. Current IDDPLL = 1 mA (Low Power Oscillator).
3. Current IDDPLL = 3 mA (Standard Oscillator).
4. Monitors VDDA, active only in full performance mode. This interrupt indicates that I/O and ATD performance may be
degraded due to low supply voltage.
5. Monitors VDD2.5, active only in full performance mode. Only POR is active in reduced performance mode.
6. Monitors VDD2.5, active in all modes.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
13
Preliminary
Electrical Characteristics
3.7.5 Chip Power Up and Voltage Drops
The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset)
handle chip power-up or drops of the supply voltage. Refer to Figure 2.
Voltage
VDDA
VLVID
VLVIA
VDD2.5
VLVRD
VLVRA
VPORD
Time
LVI Disabled
due to LVR
LVI Enabled
LVI
POR
LVR
Note: Not to scale.
Figure 2. VREG Chip Power-up and Voltage Monitoring
3.7.6 Output Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed. Capacitive loads are specified in Table 18. Capacitors with X7R dielectricum are
required.
Table 18. VREG Recommended Load Capacitances
Rating
Symbol
Min
Typ
Max
Unit
Load Capacitance per VDD2.5 pin 1
Load Capacitance on VDDPLL pin
NOTES:
CLVDD
200
90
220
220
12000
5000
nF
nF
CLVDDfcPLL
1. Refer to Table 38 for the specific number of VDD2.5 pins on various packages. Each VDD2.5 pin should have the
recommended loading as described in Section 3.7.3, “Circuit Board Layout,” of the MAC7100 Microcontroller Family
Reference Manual (MAC7100RM).
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
14
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
3.8 Clock and Reset Generator
This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and
reset generator.
3.8.1 Oscillator Characteristics
The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing
Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing
Pierce oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET
signal. Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the
oscillation is checked for each start from either power on, STOP or oscillator fail. t
specifies the
CQOUT
maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation
is not detected. The quality check also determines the minimum oscillator start-up time t . The device
UPOSC
also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock
signal is below the Clock Monitor Assert Frequency f
.
CMFA
Table 19. Oscillator Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
J1a C Crystal oscillator range (loop controlled Pierce)
J1b C Crystal oscillator range (full swing Pierce) 2 3
J2 P Startup Current
fOSC
4.0
0.5
100
—
—
—
—
3 4
—
100
—
—
—
—
—
7
16
40
—
MHz
MHz
μA
1
fOSC
IOSC
tUPOSC
tCQOUT
fCMFA
fEXT
J3 C Oscillator start-up time (loop controlled Pierce)
J4 D Clock Quality check time-out
50 5
2.5
200
50
—
ms
s
0.45
50
J5 P Clock Monitor Failure Assert Frequency
J6 P External square wave input frequency 3
J7 D External square wave pulse width low
J8 D External square wave pulse width high
J9 D External square wave rise time
J10 D External square wave fall time
J11 D Input Capacitance (EXTAL, XTAL pins)
NOTES:
KHz
MHz
ns
0.5
9.5
9.5
—
tEXTL
tEXTH
tEXTR
tEXTF
CIN
—
ns
1
ns
—
1
ns
—
—
pF
1. If CLKSEL[PLLSEL] is clear then the system clock (fSYS) is equal to fOSC, otherwise it is equal to fVCO (table
Table 20, K3). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS
.
2. Depending on the crystal; a damping series resistor might be necessary
3. XCLKS asserted (low) during reset
4. fOSC = 4 MHz, C = 22 pF (refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for circuit
board layout recommendations, including oscillator capacitor placement and values).
5. Maximum value is for extreme cases using high Q, low frequency crystals
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
15
Preliminary
Electrical Characteristics
3.8.2 PLL Filter Characteristics
The oscillator provides the reference clock for the PLL as shown in Figure 3. The voltage controlled
oscillator (VCO) of the PLL is also the system clock source in self clock mode. In order to operate reliably,
care must be taken to select proper values for external loop filter components.
VDDPLL
CS
CP
Phase
Detector
VCO
KV
R
fREF
1
fOSC
fVCO
Δ
K
φ
REFDV+1
fCMP
Loop Divider
1
1
2
SYNR+1
Figure 3. Basic PLL Functional Diagram
The procedure described below can be used to calculate the resistance and capacitance values using typical
values for K , f and i from Table 20. First, the VCO Gain at the desired VCO output frequency is
1
1
ch
approximated by:
(f1 – fVCO
-------------------------
K1 ⋅ 1V
)
KV = K1 ⋅ e
Eqn. 8
Eqn. 9
The phase detector relationship is given by:
KΦ = – ich ⋅ KV
i is the current in tracking mode. The loop bandwidth f should be chosen to fulfill the Gardner’s stability
ch
C
criteria by at least a factor of 10, a typical value for the stability factor is 50. ζ = 0.9 ensures a good transient
response.
2 ⋅ ζ ⋅ fREF
fC < ---------------------------------------- ------ → fC < ------------- ; (ζ = 0.9)
10
fREF
1
Eqn. 10
4 ⋅ 10
π ⋅ (ζ + 1 + ζ2)
And finally the frequency relationship is defined as:
fVCO
n = ---------- = 2 ⋅ (SYNR + 1)
Eqn. 11
Eqn. 12
fREF
With the above inputs the resistance can be calculated as:
2 ⋅ π ⋅ n ⋅ fC
R = ---------------------------
KΦ
The capacitance C can now be calculated as:
S
2 ⋅ ζ2
π ⋅ fC ⋅ R
0.516
fC ⋅ R
--------------------
CS
=
≈ ------------- ; (ζ = 0.9)
Eqn. 13
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
16
Freescale Semiconductor
ElectricalCharacteristics
The capacitance C should be chosen in the range of:
P
CS ÷ 20 ≤ CP ≤ CS ÷ 10
Eqn. 14
The stabilization delays shown in Table 20 are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
3.8.2.1 Jitter Information
With each transition of the clock f
, the deviation from the reference clock f
is measured and input
CMP
REF
voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will
eliminate the effect of PLL jitter to a large extent.
0
1
2
3
N–1
N
tMIN1
tNOM
tMAX1
tMIN(N)
tMAX(N)
Figure 4. Jitter Definitions
The relative deviation of t
is at its maximum for one clock period, and decreases towards zero for
NOM
larger number of clock periods (N). Thus, jitter is defined as:
tMAX(N)
-------------------
N ⋅ tNOM
tMIN(N)
N ⋅ tNOM
⎛
⎞
⎠
-------------------
J(N) = max 1 –
, 1 –
Eqn. 15
⎝
For N < 100, the following equation is a good fit for the maximum jitter:
j1
J(N) = ------- + j2
N
Eqn. 16
J(N)
0 1
5
10
15
20
N
Figure 5. Maximum Bus Clock Jitter Approximation
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
17
Electrical Characteristics
3.8.3 PLL Characteristics
Table 20. PLL Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
K1
PLL reference frequency, crystal oscillator range
fREF
fSCM
0.5
2
—
—
16
5.5
50
4
MHz
MHz
MHz
K2 P Self Clock Mode frequency
K3 D VCO locking range
1
fVCO
8
—
2
K4
D
Lock Detector transition from Acquisition to Tracking mode
|Δtrk
|ΔLock
|Δunl
|
3
—
%
2
K5 D Lock Detection
|
0
—
1.5
2.5
8
%
2
K6 D Un-Lock Detection
|
0.5
6
—
%
2
K7
D
Lock Detector transition from Tracking to Acquisition mode |Δunt
|
—
%
K8 C PLLON Total Stabilization delay (Auto Mode) 3
tstab
tacq
tal
—
—
—
—
—
—
—
—
—
0.5 4
0.3 4
0.2 4
38.5
3.5
–195
126
—
3 5
1 5
2 5
—
ms
ms
3
K9 D PLLON Acquisition mode stabilization delay
3
K10 D PLLON Tracking mode stabilization delay
ms
K11 D Charge pump current acquisition mode
K12 D Charge pump current tracking mode
K13 D Jitter fit VCO loop gain parameter
K14 D Jitter fit VCO loop frequency parameter
K15 C Jitter fit parameter 1
| ich
| ich
K1
f1
|
|
μA
—
μA
—
MHz/V
MHz
—
4
j1
1.3
0.12
%
4
K16 C Jitter fit parameter 2
j2
—
%
NOTES:
1. If CLKSEL[PLLSEL] is set then the system clock (fSYS) is equal to fVCO, otherwise it is equal to fOSC (table Table 19,
J1a or J1b). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS
.
2. Percentage deviation from target frequency
3. PLL stabilization delay is highly dependent on operational requirement and external component values (for
example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.
4. fOSC = 4 MHz, fVCO = 40 MHz (REFDV = 0x00, SYNR = 0x04), CS = 2.2 nF, CP = 220 pF, RS = 5.6 KΩ.
5. fOSC = 4 MHz, fVCO = 16 MHz (REFDV = 0x00, SYNR = 0x01), CS = 4.7 nF, CP = 470 pF, RS = 2.7 KΩ.
3.8.4 Crystal Monitor Time-out
The time-out Table 21 shows the delay for the crystal monitor to trigger when the clock stops, either at the high
or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
Table 21. Crystal Monitor Time-Outs
Min
Typ
Max
Unit
6
10
18.5
μs
3.8.5 Clock Quality Checker
The timing for the clock quality check is derived from the oscillator and the VCO frequency range in
Table 20. These numbers define the upper time limit for the individual check windows to complete.
Table 22. CRG Maximum Clock Quality Check Timings
Clock Check Windows
Check Window
Value
9.1 to 20.0
0.46 to 1.0
Unit
ms
s
Timeout Window
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
18
Freescale Semiconductor
ElectricalCharacteristics
3.8.6 Startup
Table 23 summarizes several startup characteristics. Refer to Section 4.3.6.10, “CRG Operating Mode
Details,” in the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for details.
Table 23. CRG Startup Characteristics
Num C
Rating
Symbol
Min
Typ
Max
Unit
L1 D Reset input pulse width
PWRSTL
nRST
2
—
—
—
—
196
—
tOSC
tOSC
ns
L2 D Startup from Reset
192
20
L3 D XIRQ, IRQ pulse width, edge-sensitive mode
PWIRQ
3.8.6.1 Power On and Low Voltage Reset (POR and LVR)
The V
and V
levels are derived from V 2.5. The V
level is derived from V 2.5. They
PORR
PORA
DD
LVRA DD
are also valid if the device is powered externally. After releasing a POR or LVR reset, the oscillator and
clock quality checks start. After t (Table 19, J4) if no valid oscillation is detected, the MCU will
CQOUT
start using the internal self-generated clock. The minimum startup time is given by t
(Table 19, J3).
uposc
3.8.6.2 SRAM Data Retention
SRAM content integrity is guaranteed if the CRGFLG[PORF] bit is not set following a reset operation.
3.8.6.3 External Reset
When external reset is asserted for a time greater than PW
, the CRG generates an internal reset and
RSTL
the CPU fetches the reset vector without a clock quality check, if there was stable oscillation before reset.
3.8.6.4 Stop Recovery
The MCU can return from stop to run mode in response to an external interrupt or an API. Two delays
occur before the MCU resumes execution. First, the voltage regulator must exit reduced power mode and
return to full performance mode (this assumes that the internal regulator is used rather than driving V 2.5
DD
and V PLL with an external regulator). Second, a clock quality check is performed in the same manner
DD
as for a power-on reset before releasing the clocks to the system.
3.8.6.5 Pseudo Stop Recovery
Recovery from pseudo stop mode is similar to stop mode in that the VREG must return to FPM, but since
the oscillator is not stopped there is no delay for clock stabilization. The MCU is returned to run mode by
internal or external interrupts.
3.8.6.6 Doze Recovery
Recovery from doze mode avoids both the VREG and oscillator recovery periods. The MCU is returned
to run mode by internal or external interrupts.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
19
Preliminary
Electrical Characteristics
3.9 External Bus Timing
Table 24 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay
with respect to the rising edge of a reference clock. The reference clock is the
CLKOUT output. All other timing relationships can be derived from these values.
1
Table 24. External Bus Input Timing Specifications
Num
C
Rating
Symbol Min Max Unit
M1
P CLKOUT period 2
tCYC
20
—
ns
Control Inputs
M2a P Control input valid to CLKOUT high 3
M3a P CLKOUT high to control inputs invalid 3
tCVCH
tCHCII
13
0
—
—
ns
ns
Data Inputs
M4
M5
P Data input (DATA[15:0]) valid to CLKOUT high
P CLKOUT high to data input (DATA[15:0]) invalid
tDIVCH
tCHDII
9
0
—
—
ns
ns
NOTES:
1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).
2. CLKOUT is equal to the system clock, fSYS. If CLKSEL[PLLSEL] is set then fSYS is equal to fVCO (table Table 20,
K3); if it is clear then fSYS is equal to fOSC (table Table 19, J1a or J1b). Throughout this document, tCYC is used to
specify a unit of time equal to 1 ÷ CLKOUT (which is equal to tfsys).
3. The TA pin is the only control input on MAC7100 family devices.
CLKOUT (50 MHz)
Input Setup & Hold
Input Rise Time
Input Fall Time
CLKOUT
1.5 V
tSETUP
Invalid
tHOLD
1.5 V Valid 1.5 V
Invalid
tRISE = 1.5 ns
VH = VIH
VL = VIL
tFALL = 1.5 ns
VH = VIH
VL = VIL
M4
M5
Inputs
Figure 6. General Input Timing Requirements
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
20
Freescale Semiconductor
ElectricalCharacteristics
3.9.1 Read and Write Bus Cycles
Table 25 lists processor bus output timings. Read/write bus timings listed in Table 25 are shown in
Figure 7 and Figure 8.
1
Table 25. External Bus Output Timing Specifications
Num
C
Rating
Symbol
Min
Max
Unit
Control Outputs
M6a
M6b
M6c
M6d
M7a
M7b
M7c
P CLKOUT high 2 to chip selects (CS[2:0]) valid
P CLKOUT high 2 to byte selects (BS[1:0]) valid
P CLKOUT high 2 to output select (OE) valid
P CLKOUT high 2 to address strobe (AS) valid
P CLKOUT high 2 to control output (BS[1:0], OE) invalid
P CLKOUT high 2 to chip selects (CS[2:0]) invalid
P CLKOUT high 2 to address strobe (AS) invalid
tCHCV
tCHBV
tCHOV
tCHASV
—
—
—
—
0.5tCYC + 10
0.5tCYC + 10
0.5tCYC + 10
0.5tCYC + 10
—
ns
ns
ns
ns
ns
ns
ns
tCHCOI 0.5tCYC + 2
tCHCI 0.5tCYC + 2
tCHASI 0.5tCYC + 2
Address and Attribute Outputs
—
—
M8
M9
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
tCHAV
tCHAI
—
10
—
ns
ns
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
2
Data Outputs
M10
M11
P CLKOUT high to data output (DATA[15:0]) valid
P CLKOUT high to data output (DATA[15:0]) invalid
tCHDOV
tCHDOI
—
2
13
—
9
ns
ns
ns
M12
D
CLKOUT high to data output (DATA[15:0]) high impedance tCHDOZ
—
NOTES:
1. Assumes CLKOUT, CSn, BSn, OE, AS, ADDR[21:0] and DATA[15:0] are configured for full drive strength (via the PIM).
2. The CSn, BSn, OE and AS signals are synchronous to the falling edge of CLKOUT. Therefore, changes on these
signals are triggered by the falling edge of CLKOUT, even though they are specified in relation to the rising edge.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
21
Preliminary
Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
M6d
M6a
M8
M6d
M7c
M7c
AS(1)
M6a
M8
M7b
M7a
M7a
M7b
CSn
M9
ADDR[21:0]
M1
M6c
OE
R/W
M8
M9
M6b
M6b
M7a
BS[1:0]
M10
M4
M11
M12
DATA[15:0]
M5
TA(1)
1. The TA / AS signals are multiplexed on a single pin, so only one function may be used during bus transactions.
Figure 7. Read/Write Bus Cycles, Internal Termination
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
22
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
S0
S1
S2
S3
S4
S5
S0
S1
CLKOUT
CSn
M6a
M8
M7b
M7a
M7a
M9
ADDR[21:0]
OE
M6c
R/W
M6b
BS[1:0]
DATA[15:0]
M4
M5
M2a
M3a
TA(1)
1. The TA / AS signals are multiplexed on a single pin, so AS is not available when external cycle termination is used.
Figure 8. Read Bus Cycle, External Termination
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
23
Preliminary
Electrical Characteristics
3.10 Analog-to-Digital Converter
Table 26 and Table 27 show conditions under which the ATD operates. The following constraints exist to
obtain full-scale, full range results: V A
≤
V
≤
V
≤
V
≤
V
A. This constraint exists because the
SS
RL
IN
RH
DD
sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside of
this range it will effectively be clipped.
Table 26. ATD Operating Characteristics in 5.0 V Range
Conditions shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
N1 D Reference Potential
Low
High
VRL
VRH
VSS
VDDA ÷ 2
A
—
—
V
DDA ÷ 2
VDDA
V
V
N2 C Differential Reference Voltage 1
N3 D ATD Clock Frequency
VRH – VRL
fATDCLK
4.50
0.5
5.00
—
5.50
2.0
V
MHz
N4 D ATD 10-bit Conversion PeriodfATDCLK Cycles 2
NCONV10
14
7
—
—
28
14
Cycles
μs
@ 2.0MHz fATDCLK TCONV10
N5 D ATD 8-bit Conversion PeriodfATDCLK Cycles 2
NCONV8
12
6
—
—
26
13
Cycles
μs
@ 2.0MHz fATDCLK TCONV8
N6 D Stop Recovery Time (VDDA = 5.0 V)
TREC
IREF
IREF
—
—
—
—
20
μs
N7 P Reference Supply current 1 ATD module on
N8 P Reference Supply current 2 ATD modules on
NOTES:
0.200
0.400
0.255
0.510
mA
mA
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.
Table 27. ATD Operating Characteristics in 3.3 V Range
Conditions shown in Table 7, with VDDX = 3.3 V –5/+10% and a temperature maximum of +140°C unless otherwise
noted.
Num C
Rating
Symbol
Min
Typ
Max
Unit
P1 D Reference Potential
Low
High
VRL
VRH
VSS
VDDA ÷ 2
A
—
—
V
DDA ÷ 2
VDDA
V
V
P2 C Differential Reference Voltage 1
P3 D ATD Clock Frequency
V
RH – VRL
3.15
0.5
3.3
—
3.6
2.0
V
fATDCLK
MHz
P4 D ATD 10-bit Conversion PeriodfATDCLK Cycles 2
NCONV10
14
7
—
—
28
14
Cycles
μs
@ 2.0MHz fATDCLK TCONV10
P5 D ATD 8-bit Conversion PeriodfATDCLK Cycles 2
NCONV8
12
6
—
—
26
13
Cycles
μs
@ 2.0MHz fATDCLK TCONV8
P6 D Stop Recovery Time (VDDA = 3.3 V)
TREC
IREF
IREF
—
—
—
—
20
μs
P7 P Reference Supply current 1 ATD module on
P8 P Reference Supply current 2 ATD modules on
NOTES:
0.130
0.260
0.170
0.340
mA
mA
1. Full accuracy is not guaranteed when differential voltage is less than 3.15 V
2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
24
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
3.10.1 Factors Influencing Accuracy
Three factors—source resistance, source capacitance and current injection—have an influence on the
accuracy of the ATD.
3.10.1.1 Source Resistance
Due to the input pin leakage current as specified in Table 8 in conjunction with the source resistance there
will be a voltage drop from the signal source to the ATD input. The maximum specified source resistance
R , results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If the device or
S
operating conditions are less than the worst case, or leakage-induced errors are acceptable, larger values
of source resistance are allowed.
3.10.1.2 Source Capacitance
When sampling, an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external capacitance and the pin capacitance. For a maximum sampling error of
the input voltage ≤ 1 LSB, then the external filter capacitor must be calculated as,
C
≥
1024
×
(C
–
C
).
f
INS
INN
3.10.1.3 Current Injection
There are two cases to consider:
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than V and 0x000 for values less
RH
than V unless the current is higher than specified as disruptive condition.
RL
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the
accuracy of the conversion depending on the source resistance. The additional input voltage error
on the converted channel can be calculated as V
the currents injected into the two pins adjacent to the converted channel.
= K × R × I , with I being the sum of
ERR
S INJ INJ
Table 28. ATD Electrical Characteristics
Conditions are shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
Q1 C Max input Source Resistance
RS
—
—
1
kΩ
Q2 C Total Input Capacitance
Non Sampling
CINN
CINS
—
—
10
22
—
—
pF
pF
Sampling
Q3 C Disruptive Analog Input Current
INA
Kp
Kn
–2.5
—
—
—
—
2.5
mA
Q4 C Coupling Ratio positive current injection
Q5 C Coupling Ratio negative current injection
TBD
TBD
A / A
A / A
—
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
25
Electrical Characteristics
3.10.2 ATD Accuracy
Table 29 and Table 30 specify the ATD conversion performance excluding any errors due to current
injection, input capacitance and source resistance.
Table 29. ATD Conversion Performance in 5.0 V Range
Conditions shown in Table 7 except as noted here:
fATDCLK = 2.0 MHz, 4.5 V ≤ VDDA ≤ 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
Unit
R1 P 10-bit Resolution
LSB
DNL
INL
AE
—
–1
5 1
—
—
1
mV
R2 P 10-bit Differential Nonlinearity
R3 P 10-bit Integral Nonlinearity
R4 P 10-bit Absolute Error 2
R5 P 8-bit Resolution
Counts
Counts
Counts
mV
–2.5
–3
±1.5
±2.0
20 1
—
2.5
3
LSB
DNL
INL
AE
—
—
R6 P 8-bit Differential Nonlinearity
R7 P 8-bit Integral Nonlinearity
R8 P 8-bit Absolute Error 2
NOTES:
–0.5
–1.0
–1.5
0.5
1.0
1.5
Counts
Counts
Counts
±0.5
±1.0
1. Assumes VREF = VRH – VRL = 5.12 V, other VREF conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently ½ count for any A/D converter.
Table 30. ATD Conversion Performance in 3.3 V Range
Conditions shown in Table 7 except as noted here:
fATDCLK = 2.0 MHz, 3.15 V ≤ VDDA ≤ 3.6 V
Num C
Rating
Symbol
Min
Typ
Max
Unit
S1 P 10-bit Resolution
LSB
DNL
INL
AE
—
3.25 1
—
—
1.5
3.5
5
mV
S2 P 10-bit Differential Nonlinearity
S3 P 10-bit Integral Nonlinearity
S4 P 10-bit Absolute Error 2
S5 P 8-bit Resolution
–1.5
–3.5
–5
Counts
Counts
Counts
mV
±1.5
±2.0
13 1
—
LSB
DNL
INL
AE
—
—
S6 P 8-bit Differential Nonlinearity
S7 P 8-bit Integral Nonlinearity
S8 P 8-bit Absolute Error 2
NOTES:
–0.5
–1.5
–1.5
0.5
1.5
1.5
Counts
Counts
Counts
±1.0
±1.0
1. Assumes VREF = VRH – VRL = 3.33 V, other VREF conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently ½ count for any A/D converter.
For the following definitions, see Figure 9.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps:
Vi – Vi – 1
DNL(i) = ---------------------- – 1
Eqn. 17
1 LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
Vn – V0
INL(n) =
DNL(i) = ------------------ – n
Eqn. 18
∑
1 LSB
i = 1
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
26
Freescale Semiconductor
ElectricalCharacteristics
10-bit Absolute Error Boundary
0x3FF
0x3FE
0x3FD
0x3FC
0x3FB
0x3FA
0x3F9
0x3F8
0x3F7
0x3F6
0x3F5
0x3F4
0x3F3
8-bit Absolute Error Boundary
DNL
VI–1
0xFF
0xFE
0xFD
2
LSB
VI
9
8
7
6
5
4
3
2
1
0
Ideal Transfer Curve
10-bit Transfer Curve
1
8-bit Transfer Curve
VIN
mV
0
10
20
30
40 50
5055 5065 5075 5085 5095 5105 5115
5060 5070 5080 5090 5100 5110 5120
5
15
25
35
Figure 9. ATD Accuracy Definitions
NOTE
Figure 9 shows only definitions, for specification values refer to Table 29
.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
27
Preliminary
Electrical Characteristics
3.10.3 ATD Timing Specifications
Table 31. ATD External Trigger Timing Specifications
Num C
Parameter Symbol Min
Max
Unit
1
T1 D ETRIG Period (Level-Sensitive Trigger Mode)
TPERIOD 1 + NCONVn
—
fATDCLK Cycles
fATDCLK Cycles
T2 D ETRIG Minimum Pulse Width
Edge-Sensitive Trigger Mode
tPW
1
2
—
—
Level-Sensitive Trigger Mode
T3 D ETRIG Level Recovery 2
T4 D Conversion Start Delay
NOTES:
tLR
1
—
2
fATDCLK Cycles
fATDCLK Cycles
tDLY
—
1. NCONVn denotes 8- or 10-bit conversion time (refer to specifications N4, N5, P4 and P5). In order to achieve the
minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.
2. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.
Edge Sensitive
T2
Falling Edge Active ETRIG
T4
T4
Conversion Activity ANn_x
Level Sensitive
T2
Low Active ETRIG
Sequence
Complete Flag
ASCIF
T4
T4
Conversion Activity ANn_x
T1
Level Sensitive
Low Active ETRIG
T3
Sequence
Complete Flag
ASCIF
T4
Conversion Activity ANn_x
Figure 10. ATD External Trigger Timing Diagram
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
28
Freescale Semiconductor
ElectricalCharacteristics
3.11 Serial Peripheral Interface
3.11.1 Master Mode
Master mode timing values are shown in Table 32 and illustrated in Figure 11 and Figure 12.
Table 32. SPI Master Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
2
1
U1a P Operating Frequency (baud rate)
fOP
—
½
fIPS
----------------------------
7 × 32, 678
1
U1b P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS
)
tSCK
2 2
—
—
—
—
—
—
—
—
—
—
7 × 32,768 tIPS
U2 D Enable Lead Time
tlead
tlag
twsck
tsu
thi
½
—
—
tSCK
tSCK
ns
U3 D Enable Lag Time
½
U4 D Clock (SCK) High or Low Time
U5 D Data Setup Time (Inputs)
U6 D Data Hold Time (Inputs)
U9 D Data Valid (after Enable Edge)
U10 D Data Hold Time (Outputs)
U11 D Rise Time Inputs and Outputs
U12 D Fall Time Inputs and Outputs
NOTES:
tIPS − 30
1024 tIPS
—
25
0
ns
—
ns
tv
—
0
25
ns
tho
tr
—
ns
—
—
25
ns
tf
25
ns
1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.
2. On mask set L49P and L47W devices, U1a maximum = ¼ and U1b minimum = 4.
3.11.2 Slave Mode
Slave mode timing values are shown in Table 33 and illustrated in Figure 13 and Figure 14.
Table 33. SPI Slave Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
1
V1a P Operating Frequency
fOP
—
½
fIPS
----------------------------
7 × 32, 678
V1b P SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS
)
tSCK
tlead
tlag
twsck
tsu
thi
2 1
—
—
—
—
—
—
—
—
—
—
—
—
7 × 32,768 tIPS
V2 D Enable Lead Time
1
—
—
—
—
—
1
tIPS
tIPS
ns
V3 D Enable Lag Time
1
V4 D Clock (SCK) High or Low Time
V5 D Data Setup Time (Inputs)
V6 D Data Hold Time (Inputs)
V7 D Slave Access Time
tIPS − 30
25
25
—
—
—
0
ns
ns
ta
tIPS
tIPS
ns
V8 D Slave SIN Disable Time
V9 D Data Valid (after SCK Edge)
V10 D Data Hold Time (Outputs)
V11 D Rise Time Inputs and Outputs
V12 D Fall Time Inputs and Outputs
NOTES:
tdis
tv
1
25
—
25
25
tho
tr
ns
—
—
ns
tf
ns
1. On mask set L49P and L47W devices, V1a maximum = ¼ and V1b minimum = 4.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
29
Electrical Characteristics
PCSx
(OUTPUT)
U2
U11
U12
U1b
U3
SCK
(CPOL = 0)
(OUTPUT)
U4
U4
SCK
(CPOL = 1)
(OUTPUT)
U5
U6
SIN
(INPUT)
MSB In(2)
Bit 6 ... 1
LSB In
U9
U9
U10
SOUT
(OUTPUT)
MSB Out(2)
Bit 6 ... 1
LSB Out
1. If configured as output.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 11. SPI Master Timing (CPHA = 0)
PCSx
(OUTPUT)
U2
U11
U12
U1b
U12
U3
SCK
(CPOL = 0)
(OUTPUT)
U4
U5
U11
U4
U6
SCK
(CPOL = 1)
(OUTPUT)
SIN
(INPUT)
MSB In(2)
Bit 6 ... 1
LSB In
U9
U10
SOUT
(OUTPUT)
MSB Out(2)
1. If configured as output.
Port Data
Bit 6 ... 1
Master LSB Out
Port Data
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI Master Timing (CPHA = 1)
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
30
Freescale Semiconductor
ElectricalCharacteristics
SS
(INPUT)
V2
V11
V12
V1b
V12
V11
V3
SCK
(CPOL = 0)
(INPUT)
V4
V4
SCK
(CPOL = 1)
(INPUT)
V7
V8
V10
V9
V10
SOUT
(OUTPUT)
Slave MSB Out
Bit 6 ... 1
Slave LSB Out
V5
V6
SIN
(INPUT)
MSB In
Bit 6 ... 1
LSB In
Figure 13. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
V2
V11
V12
V1b
V12
V11
V3
SCK
(CPOL = 0)
(INPUT)
V4
V4
SCK
(CPOL = 1)
(INPUT)
V9
V8
V10
V7
SOUT
Slave MSB Out
Bit 6 ... 1
Slave LSB Out
LSB In
(OUTPUT)
V5
V6
SIN
(INPUT)
MSB In
Bit 6 ... 1
Figure 14. SPI Slave Timing (CPHA = 1)
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
31
Electrical Characteristics
3.12 FlexCAN Interface
Table 34. FlexCAN Wake-up Pulse Characteristics
Conditions are shown in Table 7 unless otherwise noted
Num C Rating
Symbol
Min
Typ
Max
Unit
W1 P FlexCAN Wake-up dominant pulse filtered
W2 P FlexCAN Wake-up dominant pulse passed
tWUP
tWUP
—
5
—
—
2
μs
μs
—
3.13 Common Flash Module
NOTE
Unless otherwise noted the abbreviation NVM (Non-Volatile Memory) is
used for both program Flash and data Flash.
The time base for all program and data Flash operations, f
, is derived from the IPS bus clock, f
,
IPS
NVMOP
using the CFMCLKD register to control the divider ratio. Throughout this section, t refers to 1 ÷ f
,
IPS
IPS
and t
refers to 1 ÷ f
. An f
frequency range limit is imposed for performing program
NVMOP
NVMOP
NVMOP
or erase operations. The CFM does not monitor the frequency and will not prevent program or erase
operation at frequencies above or below the following limits:
150 KHz < fNVMOP ≤ 200 KHz
Eqn. 19
f
= 200 KHz gives the fastest program and erase performance. Setting CFMCLKD to a value such
NVMOP
that f
< 150 KHz should be avoided, as this can damage the Flash memory due to overstress. Setting
NVMOP
CFMCLKD to a value such that f
the Flash memory array cells.
> 200 KHz can result in incomplete programming or erasure of
NVMOP
3.13.1 Mass Erase Timing
The time required to erase the entire NVM array (both program and data) is calculated using the formula:
tmass ≈ 20000 ⋅ tNVMOP
Eqn. 20
The setup time can be ignored for this operation.
3.13.2 Blank Check Timing
The time it takes to perform a blank check on the program or data Flash is dependant on the location of the
first non-blank word, starting from relative address zero. One f cycle is required per word to be verified,
IPS
and the time required for the operation is calculated using the formula:
tcheck = (locations + 15) ⋅ tIPS
Eqn. 21
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
32
Freescale Semiconductor
ElectricalCharacteristics
3.13.3 Page Erase Timing
The time required to erase a 4 Kbyte program or 1 Kbyte data Flash logical page is calculated using the
formulas:
terap = 4096 ⋅ tNVMOP + 15 ⋅ tIPS
terad = 1024 ⋅ tNVMOP + 15 ⋅ tIPS
Eqn. 22
Eqn. 23
3.13.4 Page Erase Verify Timing
The time required to verify that a program Flash page is erased depends on the location of the first
non-blank word. The time required for the operation is calculated using the formula:
4 × 1024
⎛
⎝
⎞
tpevp
=
---------------------- + 15 × tIPS
Eqn. 24
⎠
4
The time required to verify that a data Flash page is erased is calculated using the formula:
1 × 1024
⎛
⎝
⎞
tpevd
=
---------------------- + 15 × tIPS
Eqn. 25
⎠
4
3.13.5 Programming Timing
Programming time is dependant on the f and f
frequencies, and is calculated for a single word
IPS
NVMOP
using the formula:
tswpgm = 9 ⋅ tNVMOP + 25 ⋅ tIPS
Eqn. 26
Burst programming can be utilized with the program Flash, where up to 32 words in a row can be
programmed consecutively by keeping the command pipeline filled. The time to program a consecutive
word is calculated using the formula:
tbwpgm = 4 ⋅ tNVMOP + 9 ⋅ tIPS
Eqn. 27
Therefore, the time to program a 32-word row is calculated using the formula:
tbrpgm = tswpgm + 31 ⋅ tbwpgm
Eqn. 28
Note that burst programming is more than 2 times faster than single word programming.
1
3.13.6 Data Signature Timing
The time required to perform a data signature command is dependant on the number of words or
half-words compressed during the operation, and is calculated using the formula:
tdsig = (Words or Half-Words + 15) ⋅ tIPS
Eqn. 29
1. This feature is not available on mask set L49P and L47W devices.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
33
Preliminary
Electrical Characteristics
3.13.7 CFM Timing Specifications
Table 35 lists the time required to execute various operations described in the Section 3.13.1 through
Section 3.13.6. For operating conditions other than those assumed below, Equation 19 through
Equation 29 must be used to calculate the timing for specific commands under those conditions.
Table 35. CFM Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
X1 D System Clock
fNVMfsys
fNVMfips
0.5
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50 1
—
MHz
MHz
kHz
μs
X2 D Bus frequency for Programming or Erase Operations
X3 D Program/Erase Operating Frequency
fNVMOP
150
47.1
48.1
20.8
21.3
693.1
706.8
21.0
21.3
5.2
200
X4 P Programming Time, 2
Single Word
fSYS = 50 MHz tswpgm
fSYS = 40 MHz
71.0
71.0
30.5
30.5
1,016.5
1,016.5
26.6
26.6
6.7
X5 D Programming Time, 2
Consecutive Word Burst
fSYS = 50 MHz tbwpgm
fSYS = 40 MHz
μs
μs
X6 D Programming Time, 2
32-word Row Burst
fSYS = 50 MHz tbrpgm
fSYS = 40 MHz
X7a P Page Erase Time, 2
Program Flash
fSYS = 50 MHz terap
fSYS = 40 MHz
ms
ms
ms
X7b P Page Erase Time, 2
Data Flash
fSYS = 50 MHz terad
fSYS = 40 MHz
5.3
6.7
X8 P Mass Erase Time 2
tmass
100
16
130
X9a D Blank Check Time, 3
Program Flash per Block
MAC71x1, MAC71x6 tbcheckp
MAC71x2
131,087 tIPS
65,551
16
X9b D Blank Check Time, 3
Data Flash per Block
tbcheckd
16
8,207
tIPS
X9c D Page Erase Verify Time 3
Program Flash tpevp
Data Flash tpevd
16
16
17
17
17
17
—
—
—
—
—
—
1,039
271
tIPS
X10 D Data Signature Time 4
MAC71x6, Program tdsig
MAC71x1, Program
MAC71x2, Program
MAC71xx, Data
262,159 tIPS
131,087
65,551
16,399
NOTES:
1. Subject to restrictions in Table 19 and Table 20 for operating characteristics of the oscillator and PLL.
2. Minimum erase and programming times are achieved with the indicated maximum fSYS (which is fIPS × 2, and subject to the
limits of Table 19 and Table 20) and corresponding maximum fNVMOP. Maximum erase and programming times are
dependent on the combination of fNVMOP and fIPS; values shown are calculated for fIPS = 2 MHz and fNVMOP = 154 KHz.
3. Minimum blank check or page erase verify time assumes the first word in the array is blank and the second is not. Maximum
blank check or page erase verify time assumes the entire block or page is blank.
4. Data signature timing is dependant on the number of words or half-words compressed for the program and data arrays,
respectively. Minimum time is for two words or half-words; maximum time is for the entire array.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
34
Freescale Semiconductor
Preliminary
ElectricalCharacteristics
3.13.8 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase
cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is
incremented every time a sector or mass erase event is executed.
Table 36. NVM Reliability Characteristics
Conditions shown in Table 7 unless otherwise noted.
Num
C
Rating
Min
Unit
X11
X12
C Program/Data Flash Program/Erase endurance (–40C to +125C)
C Program/Data Flash Data Retention Lifetime
10,000
15
Cycles
Years
NOTE
All values shown in Table 36 are target values and subject to
characterization. For Flash cycling performance, each program operation
must be preceded by an erase.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
35
Preliminary
Device Pin Assignments
4 Device Pin Assignments
The MAC7100 Family is available in 208-pin ball grid array (MAP BGA), 144-pin low profile quad flat
(LQFP), 112-pin LQFP, and 100-pin LQFP package options. The family of devices offer pin-compatible
packaged devices to assist with system development and accommodate a direct application enhancement
path. Refer to Table 2 for a comparison of the peripheral sets and package options for each device.
Most pins perform two or more functions, which are described in more detail in the MAC7100
Microcontroller Family Reference Manual (MAC7100RM). Table 37, Table 38 and Figure 15 through
Figure 22 show the pin assignments for various devices and packages.
Table 37. Signal Pin Assignments
Pin Number (by Device)
7121
Primary /
GPIO
Function
External
Bus
Function
Peripheral
Function
Debug
Function
Read on
Reset
7101 7111
7106 7116
7141
7142
1
1
7112
7122 7131 7136
1
7126
EXTAL
XTAL
XFC
RESET
TDI
—
—
—
—
—
—
—
—
—
—
—
—
MCKO 4
EVTO
EVTI
MDO0
MDO1
MSEO
RDY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PS 3
AA 3
—
—
—
—
—
—
60
61
60
60
48
48 T10
49 T11
46 T9
T10
T11
T9
45
46
43
33
93
94
95
96
—
—
—
—
—
—
—
—
65
64
63
—
—
—
—
—
48
8
—
61
58
61
58
49
46
36
102
103
104
105
—
—
—
58
—
—
48
48
48
36 T7
T7
—
—
128
129
130
131
128
129
130
131
79
128
129
130
131
102 A8
103 B8
104 A7
105 B7
A8
B8
A7
B7
TDO
TCK
TMS
—
—
—
—
—
—
—
—
TA / AS 2
DATA0 3
DATA1 3
DATA2 3
DATA3 3
DATA4 3
DATA5 3
DATA6 3
DATA7 3
DATA8 3
DATA9 3
DATA10 3
DATA11 3
DATA12 3
DATA13 3
DATA14 3
DATA15 3
—
—
—
—
M14 M14
PA0
—
138
137
136
135
134
133
132
138
137
136
135
134
133
132
98
138
137
136
135
134
133
132
98
106
—
106 B5
B5
C5
A5
C6
B6
A6
C7
PA1
—
—
—
—
—
—
—
C5
A5
C6
B6
A6
C7
PA2
—
—
PA3
—
—
PA4
—
—
PA5
—
—
PA6
—
—
PA7
—
—
74
73
72
71
70
69
53
52
51
11
12
13
14
15
16
74 H15 H15
73 H13 H13
72 H14 H14
71 H16 H16
PA8
—
—
—
—
—
—
—
97
97
PA9
—
—
96
96
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
—
—
95
95
—
—
94
94
70 J15
69 J14
J15
J14
—
—
93
93
—
—
67
67
67
53 R12 R12
52 T12 T12
51 P11 P11
—
—
66
65
15
16
17
18
19
20
66
66
—
—
65
65
SDA
SCL
SIN_A
SOUT_A
SCK_A
—
15
15
11 G1
12 H3
13 H2
14 H1
15 J3
16 J1
G1
H3
H2
H1
J3
—
—
16
16
9
—
—
17
17
10
11
12
13
—
—
18
18
—
—
19
19
PCS0_A /
SS_A
—
—
20
20
J1
PB6
PB7
PCS1_A
PCS2_A
—
—
—
—
—
—
21
22
21
22
21
22
17
18
17 J2
18 K1
J2
14
15
K1
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
36
Freescale Semiconductor
DevicePinAssignments
Table 37. Signal Pin Assignments (continued)
Pin Number (by Device)
Primary /
GPIO
Function
External
Bus
Function
Peripheral
Function
Debug
Function
Read on
Reset
7101 7111
7106 7116
7121
7126
7141
7142
1
1
7112
23
7122 7131 7136
1
PB8
PCS5_A /
PCSS_A
—
—
—
—
—
—
—
23
72
73
23
19
19 K2
56 T14
K2
16
51
52
PB9
PCS0_B /
SS_B
—
—
72
73
72
73
56
T14
PB10
PCS5_B /
PCSS_B
57 5
57 R14 R14
5
PB11
PB12
PB13
PB14
PB15
PC0
PCS2_B
PCS1_B
SCK_B
SOUT_B
SIN_B
—
—
—
—
—
—
74
75
76
77
78
9
74
75
76
77
78
9
74
75
76
77
78
9
—
—
N14 N14
58 P15 P15
59 P16 P16
60 N15 N15
61 N16 N16
53
54
55
56
57
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
49
50
58
59
60
—
86
87
88
89
90
—
—
—
—
—
66
67
—
58
59
60
61
—
—
—
—
—
—
—
—
—
ADDR0 3
ADDR1 3
ADDR2 3
ADDR3 3
ADDR4 3
ADDR5 3
ADDR6 3
ADDR7 3
ADDR8 3
ADDR9 3
ADDR10 3
ADDR11 3
ADDR12 3
ADDR13 3
ADDR14 3
ADDR15 3
BS0 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F1
F3
G2
G3
L3
F1
F3
G2
G3
L3
PC1
—
—
—
10
11
12
28
29
30
31
44
45
46
47
—
—
—
—
70
71
80
81
82
10
11
12
28
29
30
31
44
45
46
47
88
89
90
91
70
71
80
81
82
92
119
120
121
122
123
68
69
83
84
85
99
100
10
11
12
28
29
30
31
44
45
46
47
88
89
90
91
70
71
80
81
82
92
119
120
121
122
123
68
69
83
84
85
99
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PC2
—
—
—
PC3
—
—
—
PC4
—
—
—
PC5
—
—
—
M2
M3
N3
P5
R6
P6
T6
M2
M3
N3
P5
R6
P6
T6
PC6
—
—
—
PC7
—
—
—
PC8
—
—
—
PC9
—
—
—
PC10
PC11
PC12
PC13
PC14
PC15
PD0
—
—
—
—
—
—
—
—
—
K14 K14
K13 K13
K15 K15
—
—
—
—
—
—
—
—
—
67
67 J16
54 T13
J16
T13
—
—
MODB
MODA
XCLKS
—
54
55
62
63
64
68
95
96
97
98
99
PD1
PD2 6
—
BS1 3
—
55 R13 R13
62 M16 M16
63 M15 M15
—
CLKOUT
—
—
PD3
XIRQ
IRQ
—
—
PD4
—
—
—
64 L16
68 J13
L16
J13
PD5
ADDR16 3
ADDR17 3
ADDR18 3
ADDR19 3
ADDR20 3
ADDR21 3
OE 3
—
—
—
PD6
—
—
—
—
—
—
—
—
95 C10 C10
96 D10 D10
PD7
—
—
—
PD8
—
—
—
97 D9
98 B9
99 D8
D9
B9
D8
PD9
—
—
—
PD10
PD11
PD12
PD13
PD14
PD15
PE0
—
—
—
—
—
—
68
—
—
—
—
—
—
P12 P12
P13 P13
—
CS2 3
CS1 3
CS0 3
R/W 3
—
—
69
83
84
85
89
91
—
—
—
—
—
—
—
L13
L14
L15
L13
L14
L15
—
—
—
—
—
—
AN0_A
AN1_A
—
MCKO'
EVTO'
—
75
76
75 G16 G16
76 G15 G15
PE1
—
—
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
37
Device Pin Assignments
Table 37. Signal Pin Assignments (continued)
Pin Number (by Device)
7121
Primary /
External
Bus
Peripheral
Debug
Function
Read on
Reset
GPIO
7101 7111
7106 7116
7141
7142
1
1
Function
Function
7112
7122 7131 7136
1
Function
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7126
PE2
PE3
AN2_A
AN3_A
EVTI'
MDO0'
MDO1'
MSEO'
RDY'
—
—
—
93
95
97
99
101
103
105
107
113
115
117
119
121
123
43
42
41
40
39
38
37
36
35
34
33
32
27
26
25
24
141
142
143
144
1
101
102
103
104
105
106
107
108
113
114
115
116
117
118
43
101
102
103
104
105
106
107
108
113
114
115
116
117
118
43
77
77 F13
78 F14
F13
F14
68
69
70
71
72
73
74
75
80
81
82
83
84
85
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
97
98
99
100
1
78
79
80
81
82
83
84
89
90
91
92
93
94
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
109
110
111
112
1
PE4
AN4_A
—
79 E13 E13
80 E14 E14
81 D15 D15
82 C15 C15
83 C14 C14
84 D14 D14
89 B13 B13
90 C12 C12
91 A12 A12
92 B11 B11
93 A10 A10
PE5
AN5_A
—
PE6
AN6_A
—
PE7
AN7_A
—
PE8
AN8_A
—
—
PE9
AN9_A
—
—
PE10
PE11
PE12
PE13
PE14
PE15
PF0
AN10_A
AN11_A
AN12_A
AN13_A
AN14_A
AN15_A
eMIOS0
eMIOS1
eMIOS2
eMIOS3
eMIOS4
eMIOS5
eMIOS6
eMIOS7
eMIOS8
eMIOS9
eMIOS10
eMIOS11
eMIOS12
eMIOS13
eMIOS14
eMIOS15
RXD_B
—
—
—
—
—
—
—
—
—
—
—
—
94 A9
35 T5
34 R5
33 T4
32 R4
31 T3
30 P4
29 R3
28 R1
27 P2
26 P1
25 N2
24 N1
23 M1
22 L2
21 L1
20 K3
109 A3
110 C4
111 B3
112 C2
A9
T5
R5
T4
R4
T3
P4
R3
R1
P2
P1
N2
N1
M1
L2
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
—
NEXPS
NEXPR
—
PF1
42
42
PF2
41
41
PF3
—
40
40
PF4
—
39
39
PF5
—
38
38
PF6
—
37
37
PF7
—
36
36
PF8
—
35
35
PF9
—
34
34
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
—
33
33
—
32
32
—
27
27
—
26
26
—
25
25
L1
—
24
24
K3
A3
C4
B3
C2
D3
C1
E1
F2
D2
D1
E3
E2
R7
R8
—
141
142
143
144
1
141
142
143
144
1
TXD_B
—
—
RXD_A
—
—
TXD_A
—
—
CNTX_A
CNRX_A
CNTX_B
CNRX_B
CNTX_C 8
CNRX_C 8
CNTX_D 8
CNRX_D 8
RXD_D 8
TXD_D 8
—
—
1
2
7
8
3
4
5
6
D3
C1
E1
F2
D2
D1
E3
E2
—
—
2
2
2
2
2
—
—
7
7
7
7
3
—
—
8
8
8
8
4
—
—
3
3
3
3
—
—
—
—
36
37
—
—
4
4
4
4
—
—
5
5
5
5
—
—
6
6
6
6
—
—
51
52
51
51
39
40
39 R7
40 R8
—
—
52
52
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
38
Freescale Semiconductor
DevicePinAssignments
Table 37. Signal Pin Assignments (continued)
Pin Number (by Device)
Primary /
GPIO
Function
External
Bus
Peripheral
Function
Debug
Function
Read on
Reset
7101 7111
7106 7116
7121
7126
7141
7142
1
1
7112
7122 7131 7136
1
Function
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PI0
RXD_C
TXD_C
AN0_B
AN1_B
AN2_B
AN3_B
AN4_B
AN5_B
AN6_B
AN7_B
AN8_B
AN9_B
AN10_B
AN11_B
AN12_B
AN13_B
AN14_B
AN15_B
PCS3_A
PCS4_A
PCS6_A
PCS7_A
PCS3_B
PCS4_B
PCS6_B
PCS7_B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
139
140
88
139
140
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
139
140
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
107
108
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
107 A4
108 B4
A4
B4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
G13 G13
G14 G14
90
92
F16
F15
F16
F15
94
96
E16 E16
E15 E15
D16 D16
C16 C16
B16 B16
B14 B14
D13 D13
A13 A13
B12 B12
C11 C11
A11 A11
B10 B10
98
100
102
104
106
108
114
116
118
120
122
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C3
D5
PI1
—
PI2
—
D4
PI3
—
E4
PI4
—
G4
J4
PI5
—
PI6
—
K4
PI7
—
L4
PI8
—
N4
PI9
—
—
P3
PI10
PI11
PI12
PI13
PI14
PI15
NOTES:
—
—
R2
—
—
R15
N11
N12
N13
P14
—
—
—
—
—
—
—
—
1. The MAC7100 family maximum peripheral configurations are listed in these columns. Some family members do not implement the full
complement of ATD, CAN, DSPI and eSCI peripherals. Refer to Table 2 on page 3 for availability of peripheral functions on various devices.
2. AS function not available on mask set L49P devices.
3. MAC7111, MAC7116, MAC7131 and MAC7136 only.
4. The MCKO function cannot be used on MAC7121 devices (the alternate Nexus port must be used).
5. On MAC7121 mask set L49P devices, PB11 / PCS2_B is bonded out on pin 57.
6. PD2 function not available on mask set L49P devices.
7. Optional debug status port not available on mask set L49P devices.
8. CAN C, CAN D and eSCI D not available on MAC7112, MAC7122 and MAC7142 devices.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
39
Preliminary
Device Pin Assignments
Table 38. Power Supply, Voltage Regulator and Reference Pin Assignments
Pin Number (by Device)
Pin Name
7101 / 7106 /
7121 / 7122 / 7126
7131 / 7136
7141 / 7142
7111 / 7112 / 7116
VDD
X
14, 50, 64, 87, 124
13, 49, 63, 86, 125
10, 38, 66
9, 37, 65
C9, H4, K16, P7, P10
6, 35, 62
5, 34, 61
VSSX
A1, A2, B1, B2, F4, G7,
G8, G9, G10, H7, H8, H9,
H10, J7, J8, J9, J10, K7,
K8, K9, K10, M4, M13,
R9, R10, R16, T1, T2,
T15, T16
7101 / 7106 / 7112 only:
79
7131 only:
C3, D4, D5, E4, G4, J4,
K4, L4, N4, N11, N12,
N13, P3, P14, R9, R10
VDD
VSS
DD2.5
R
56
55
44
43
P9
N5, N6
C8, P8
D6, D7, N7, N8
T8
41
40
R
V
53, 127
54, 126
57
41, 101
42, 100
45
38, 92
39, 91
42
VSS2.5
VDDPLL
V
SSPLL
VDD
VSS
59
47
N9, N10
A16, B15, C13
D11, D12
A15
44
A
109
112
110
111
62
85
76
A
88
79
VRH
86
77
VRL
87
A14
78
TEST 1
N/C
50
R11
47
—
—
—
7
NOTES:
1. This pin is reserved for Freescale factory testing, and must be tied to system ground in all applications.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
40
Freescale Semiconductor
Preliminary
DevicePinAssignments
4.1 MAC7141 Pin Diagram
CNTX_A / PG4
CNRX_A / PG5
CNTX_B / PG6
CNRX_B / PG7
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
V
V
X
SS
DD
X
N/C
/ PB0
SDA
SCL
SIN_A
/ PB1
/ PB2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SOUT_A / PB3
SCK_A / PB4
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PA8
PA9
MAC7141
100 LQFP
SS_A
V
V
X
X
DD
SS
PCSS_A / PCS5_A / PB8
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
PD4 / IRQ
PD3 / XIRQ
(1)
PD2 / CLKOUT/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
PB9 / PCS0_B / SS_B
eMIOS8 / PF8
eMIOS7 / PF7
1. PD2 function not available on L49P mask set devices.
Figure 15. Pin Assignments for MAC7141 in 100-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
41
Device Pin Assignments
4.2 MAC7142 Pin Diagram
CNTX_A / PG4
CNRX_A / PG5
CNTX_B / PG6
CNRX_B / PG7
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
V
V
X
SS
DD
X
N/C
/ PB0
SDA
SCL
SIN_A
/ PB1
/ PB2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SOUT_A / PB3
SCK_A / PB4
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PA8
PA9
MAC7142
100 LQFP
SS_A
V
V
X
X
DD
SS
PCSS_A / PCS5_A / PB8
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
PD4 / IRQ
PD3 / XIRQ
PD2 / CLKOUT/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
PB9 / PCS0_B / SS_B
eMIOS8 / PF8
eMIOS7 / PF7
Figure 16. Pin Assignments for MAC7142 in 100-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
42
Freescale Semiconductor
DevicePinAssignments
4.3 MAC7121 / MAC7126 Pin Diagram
CNTX_A / PG4
CNRX_A / PG5
CNTX_C / PG8
CNRX_C / PG9
CNTX_D / PG10
CNRX_D / PG11
CNTX_B / PG6
CNRX_B / PG7
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
1
2
3
4
5
6
7
8
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
V
X
X
9
SS
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DD
SDA
SCL
SIN_A
/ PB0
/ PB1
/ PB2
PA9
SOUT_A / PB3
SCK_A / PB4
MAC7121 / MAC7126
112 LQFP
PA10
PA11
PA12
PD5
PC15
SS_A
/ PCS0
/ PB5
PCS1_A / PB6
PCS2_A / PB7
PCSS_A / PCS5_A / PB8
V
X
X
DD
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
V
SS
PD4 / IRQ
PD3 / XIRQ
(1)
PD2
/ CLKOUT/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB10 / PCS5_B/ PCSS_B
(2)
1. PD2 function not available on L49P mask set devices.
On L49P mask set devices, PB11 / PCS2_B is bonded out on pin 57.
2
Figure 17. Pin Assignments for MAC7121 / MAC7126 in 112-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
43
Preliminary
Device Pin Assignments
4.4 MAC7122 Pin Diagram
CNTX_A / PG4
CNRX_A / PG5
PG8
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
PA9
PA10
PA11
PA12
PD5
PC15
1
2
3
4
5
6
7
8
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PG9
PG10
PG11
CNTX_B / PG6
CNRX_B / PG7
V
X
X
9
SS
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DD
SDA
SCL
SIN_A
/ PB0
/ PB1
/ PB2
SOUT_A / PB3
SCK_A / PB4
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
MAC7122
112 LQFP
SS_A
PCSS_A / PCS5_A / PB8
V
X
X
DD
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
V
SS
PD4 / IRQ
PD3 / XIRQ
PD2 / CLKOUT/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB10 / PCS5_B/ PCSS_B
Figure 18. Pin Assignments for MAC7122 in 112-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
44
Freescale Semiconductor
DevicePinAssignments
4.5 MAC7101 / MAC7106 Pin Diagram
CNTX_A /PG4
CNRX_A /PG5
CNTX_C /PG8
PH10 / AN10_B
1
108
107
106
105
104
103
102
101
100
99
PE9 / AN9_A
2
PH9 / AN9_B
3
/
PE8 / AN8_A
CNRX_C PG9
4
/
PH8 / AN8_B
CNTX_D PG10
5
/
PE7 / AN7_A
CNRX_D PG11
6
/
PH7 / AN7_B
CNTX_B PG6
7
/
PE6 / AN6_A / RDY'
PH6 / AN6_B
CNRX_B PG7
8
PC0
PC1
PC2
PC3
9
PE5 / AN5_A / MSEO'
PH5 / AN5_B
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
PE4 / AN4_A / MDO1'
PH4 / AN4_B
97
V
DD
X
96
SS
V
X
PE3 / AN3_A / MDO0'
PH3 / AN3_B
95
/
/
/
SDA
PB0
PB1
PB2
94
SCL
PE2 / AN2_A / EVTI'
PH2 / AN2_B
PE1 / AN1_A / EVTO'
PH1 / AN1_B
PE0 / AN0_A / MCKO'
PH0 / AN0_B
93
SIN_A
92
/
SOUT_A PB3
MAC7101 / MAC7106
144 LQFP
91
/
SCK_A
PB4
90
SS_A
PCS0_A PB5
/
/
89
PCS1_A PB6
/
88
PCS2_A PB7
/
V
V
X
87
DD
PCSS_A PCS5_A PB8
/
/
X
SS
86
eMIOS15 PF15
/
PD15
85
eMIOS14 PF14
/
PD14
PD13
84
eMIOS13 PF13
/
83
eMIOS12 PF12
/
PD4 / IRQ
82
PC4
PC5
PC6
PC7
81
PD3 / XIRQ
(1)
PD2
80
/ CLKOUT/ XCLKS
79
V
X
SS
78
PB15 / SIN_B
eMIOS11 PF11
/
77
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
eMIOS10 PF10
/
76
eMIOS9 /PF9
eMIOS8 /PF8
eMIOS7 /PF7
75
74
73
1. PD2 function not available on L49P mask set devices.
Figure 19. Pin Assignments for MAC7101 / MAC7106 in 144-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
45
Preliminary
Device Pin Assignments
4.6 MAC7111 / MAC7116 Pin Diagram
CNTX_A / PG4
CNRX_A / PG5
CNTX_C / PG8
CNRX_C / PG9
CNTX_D / PG10
CNRX_D / PG11
CNTX_B / PG6
CNRX_B / PG7
ADDR0 / PC0
ADDR1 / PC1
ADDR2 / PC2
ADDR3 / PC3
PE9 / AN9_A
1
108
107
106
105
104
103
102
101
100
99
PE8 / AN8_A
2
PE7 / AN7_A
3
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7 / DATA7
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
PA8 / DATA8
97
V
V
X
X
PA9 / DATA9
96
SS
PA10 / DATA10
DD
/ PB0
/ PB1
95
SDA
SCL
PA11 / DATA11
94
PA12 / DATA12
93
SIN_A / PB2
SOUT_A / PB3
SCK_A / PB4
PD5 / ADDR16
92
MAC7111 / MAC7116
144 LQFP
PC15 / ADDR15
91
PC14 / ADDR14
90
SS_A
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PC13 / ADDR13
89
PC12 / ADDR12
88
V
V
X
87
DD
SS
PCSS_A / PCS5_A / PB8
eMIOS15/ PF15
eMIOS14/ PF14
eMIOS13/ PF13
eMIOS12/ PF12
ADDR4 / PC4
ADDR5 / PC5
ADDR6 / PC6
ADDR7 / PC7
eMIOS11/ PF11
eMIOS10/ PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
X
86
PD15 / R/W
PD14 / CS0
PD13 / CS1
PD4 / IRQ
PD3 / XIRQ
85
84
83
82
81
(1)
80
PD2 / CLKOUT/ XCLKS
79
TA / AS
PB15 / SIN_B
78
77
PB14 / SOUT_B
PB13 / SCK_B
76
75
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
74
73
1. PD2 function not available on L49P mask set devices.
Figure 20. Pin Assignments for MAC7111 / MAC7116 in 144-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
46
Freescale Semiconductor
Preliminary
DevicePinAssignments
4.7 MAC7112 Pin Diagram
CNTX_A / PG4
CNRX_A / PG5
PG8
PE9 / AN9_A
1
108
107
106
105
104
103
102
101
100
99
PE8 / AN8_A
2
PE7 / AN7_A
3
PG9
PE6 / AN6_A / RDY'
4
PG10
PG11
PE5 / AN5_A / MSEO'
5
PE4 / AN4_A / MDO1'
6
CNTX_B / PG6
CNRX_B / PG7
PC0
PE3 / AN3_A / MDO0'
7
PE2 / AN2_A / EVTI'
8
PE1 / AN1_A / EVTO'
9
PC1
PE0 / AN0_A / MCKO'
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PC2
PA7
98
PC3
PA8
97
V
V
/ PB0
/ PB1
X
X
PA9
96
SS
DD
PA10
PA11
PA12
PD5
95
SDA
SCL
94
93
SIN_A / PB2
SOUT_A / PB3
SCK_A / PB4
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
92
MAC7112
144 LQFP
PC15
PC14
PC13
PC12
91
90
SS_A
89
88
V
V
X
87
DD
SS
PCSS_A / PCS5_A / PB8
eMIOS15/ PF15
eMIOS14/ PF14
eMIOS13/ PF13
eMIOS12/ PF12
PC4
X
86
PD15
85
PD14
PD13
84
83
PD4 / IRQ
PD3 / XIRQ
PD2 / CLKOUT/ XCLKS
82
81
PC5
80
PC6
79
V
X
SS
PC7
78
PB15 / SIN_B
eMIOS11/ PF11
eMIOS10/ PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
77
PB14 / SOUT_B
PB13 / SCK_B
76
75
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
74
73
Figure 21. Pin Assignments for MAC7112 in 144-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
47
Device Pin Assignments
4.8 MAC7131 Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V A
A
B
C
D
E
F
V X V X PG0 PG14 PA2
PA5
TCK
TDI PE15 PE14 PH14 PE12 PH11
V
V
RH
SS
SS
RL
DD
V X V X PG2 PG15 PA0
PA4
PA3
TMS TDO PD9 PH15 PE13 PH12 PE10 PH9 VDDA PH8
SS
SS
PG5
PG3 V X PG1
PA1
PA6 VDD2.5 V X PD6 PH13 PE11 V A PE8
PE7
PE6
PH5
PH3
PE1
PH7
PH6
PH4
PH2
PE0
SS
DD
DD
PG9
PG8
PG4 V X V X V 2.5 V 2.5 PD10 PD8
PD7 V A V A PH10 PE9
SS SS
SS
SS
SS
SS
PG6 PG11 PG10 V X
PE4
PE2
PH0
PA8
PE5
PE3
PH1
PA9
SS
PC0
PB0
PB3
PB5
PB7
PG7
PC2
PB2
PB6
PC1 V X
SS
G
H
J
PC3 V X
V X V X V X V X
SS SS SS SS
SS
PB1 V X
V X V X V X V X
PA7 PA10
DD
SS
SS
SS
SS
PB4 V X
V X V X V X V X
PD5 PA12 PA11 PC15
SS
SS
SS
SS
SS
K
L
PB8 PF15 V X
V X V X V X V X
PC13 PC12 PC14 V X
SS
SS
SS
SS
SS
DD
PF14 PF13 PC4 V X
PD13 PD14 PD15 PD4
SS
M
N
P
R
T
(1)
PF12 PC5
PC6 V X
V X TA/AS
PD3 PD2(1)
SS
SS
PF11 PF10 PC7 V X V R V R V 2.5 V 2.5 V PLL V PLL V X V X V X PB11 PB14 PB15
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
PF9
PF8 V X PF5
PC8 PC10 V X V 2.5 V R V X PA15 PD11 PD12 V X PB12 PB13
DD DD DD DD SS
SS
PF7 V X PF6
PF3
PF2
PF1
PC9 PG12 PG13 V X V X TEST PA13 PD1 PB10 V X V X
SS SS SS SS
SS
V X V X PF4
PF0 PC11 RESET V PLL XFC EXTAL XTAL PA14 PD0
PB9 V X V X
SS SS
SS
SS
DD
1. AS and PD2 functions not available on L49P mask set devices.
Figure 22. Pin Assignments for MAC7131 in 208-pin MAP BGA
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
48
Freescale Semiconductor
DevicePinAssignments
4.9 MAC7136 Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V A
A
B
C
D
E
F
V X V X PG0 PG14 PA2
PA5
TCK
TDI PE15 PE14 PH14 PE12 PH11
V
V
RH
SS
SS
RL
DD
V X V X PG2 PG15 PA0
PA4
PA3
TMS TDO PD9 PH15 PE13 PH12 PE10 PH9 VDDA PH8
SS
SS
PG5
PG3
PI0
PG1
PI2
PA1
PA6 VDD2.5 V X PD6 PH13 PE11 V A PE8
PE7
PE6
PH5
PH3
PE1
PH7
PH6
PH4
PH2
PE0
DD
DD
PG9
PG8
PG4
PI1 V 2.5 V 2.5 PD10 PD8
PD7 V A V A PH10 PE9
SS SS
SS
SS
PG6 PG11 PG10 PI3
PE4
PE2
PH0
PA8
PE5
PE3
PH1
PA9
PC0
PB0
PB3
PB5
PB7
PG7
PC2
PB2
PB6
PC1 V X
SS
G
H
J
PC3
PI4
V X V X V X V X
SS SS SS SS
PB1 V X
V X V X V X V X
PA7 PA10
DD
SS
SS
SS
SS
PB4
PI5
PI6
PI7
V X V X V X V X
PD5 PA12 PA11 PC15
SS
SS
SS
SS
K
L
PB8 PF15
V X V X V X V X
PC13 PC12 PC14 V X
SS
SS
SS
SS
DD
PF14 PF13 PC4
PD13 PD14 PD15 PD4
M
N
P
R
T
PF12 PC5
PC6 V X
V X TA/ AS PD3
PD2
SS
SS
PF11 PF10 PC7
PI8
PF5
PF3
PF2
V R V R V 2.5 V 2.5 V PLL V PLL PI12 PI13 PI14 PB11 PB14 PB15
SS SS SS SS SS SS
PF9
PF7
PF8
PI9
PC8 PC10 VDDX V 2.5 V R V X PA15 PD11 PD12 PI15 PB12 PB13
DD DD DD
PI10
PF6
PF1
PC9 PG12 PG13 V X V X TEST PA13 PD1 PB10 PI11 V X
SS SS SS
V X V X PF4
PF0 PC11 RESET V PLL XFC EXTAL XTAL PA14 PD0
PB9 V X V X
SS SS
SS
SS
DD
Figure 23. Pin Assignments for MAC7136 in 208-pin MAP BGA
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
Freescale Semiconductor
49
Mechanical Information
5 Mechanical Information
As indicated in Table 2, MAC7100 Family devices are available in several packages. Please refer to the
freescale.com web site for the most up-to-date package availability and mechanical information. The table
below lists available package identifiers and Freescale document numbers for reference.
Table 39. Package Identifiers and Mechanical Specifications
Mechanical Specification
Package Type
Case Identifier
Document
100-lead LQFP
112-lead LQFP
983-02
987-02
98ASS23308W
98ASS23330W
98ASS23177W
98ARS23882W
144-lead LQFP
918-03
208-lead MAP BGA
1159A-01
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
50
Freescale Semiconductor
MechanicalInformation
Revision History
Revision History
Version No.
Release Date
Page
Numbers
Description of Changes
v0.1
First public customer release (preliminary).
29-Oct-03
v1.0
General
14-Sep-04
• Converted to Freescale identity, with blue cross-reference highlights for enhanced PDF
navigation, and miscellaneous updates for presentation consistency.
• The order of Section 3.5 and Section 3.6 were reversed for better content flow. This has
caused specification numbering to change as detailed below.
7, 8
Note: Content consolidation and reorganization has resulted in the following table and
specification number changes (the first spec number of each table is shown):
Table Title
Rev. 1.0
Rev. 0.1
5.0 V I/O Characteristics
3.3 V I/O Characteristics
Section 3.6, “Power Dissipation and Thermal Characteristics”
Table 8
Table 9
Table 10 to
Table 14
D1a Table 15 F1
E1a Table 16 G1
Table 7 to
Table 11
MAC71x1/6 Device Supply Current Characteristics – 40 MHz
MAC71x1/6 Device Supply Current Characteristics – 50 MHz
VREG Operating Conditions
VREG Recommended Load Capacitances
Oscillator Characteristics
Table 15 F1
Table 16 G1
Table 17 H1 Table 13 E1
Table 18 Table 14
Table 19 J1a Table 17 H1a
Table 12 D1a
N/A
PLL Characteristics
Crystal Monitor Time-Outs
Table 20 K1
Table 21
Table 18 J1
Table 19
CRG Maximum Clock Quality Check Timings
CRG Startup Characteristics
Table 22
Table 23 L1
Table 20
Table 21 K1
External Bus Input Timing Specifications
External Bus Output Timing Specifications
ATD Operating Characteristics in 5.0 V Range
ATD Operating Characteristics in 3.3 V Range
ATD Electrical Characteristics
ATD Conversion Performance in 5.0 V Range
ATD Conversion Performance in 3.3 V Range
ATD Electrical Characteristics (Operating)
ATD Performance Specifications
Table 24 M1 Table 22 L1
Table 25 M6a Table 23 L6a
Table 26 N1 Table 24 M1
Table 27 P1
Table 25 N1
Table 28 Q1 Table 26 P1
Table 29 R1 Table 27 Q1
Table 30 S1
N/A
N/A
N/A
Table 31 T1
Table 28 R1
Table 29 S1
Table 30 T1
Table 31 U1
Table 32 V1
ATD Timing Specifications
ATD External Trigger Timing Specifications
SPI Master Mode Timing Characteristics
SPI Slave Mode Timing Characteristics
FlexCAN Wake-up Pulse Characteristics
CFM Timing Characteristics
Table 32 U1a Table 33 W1a
Table 33 V1a Table 34 X1a
Table 34 W1 Table 35 Y1
Table 35 X1 Table 36 Z1
Table 36 X9b Table 37 Z10
NVM Reliability Characteristics
Section 2, “Ordering Information”
• Added Table 1, mask set information
• Updated Table 2 with expanded port pin counts, MAC71x2 and MAC71x6 family members
• Pin assignment changes for mask set L47W devices:
2
3
— In Table 37, PB10 / PCS5_B / PCSS_B changed to pin 57, footnote for L49P
36
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
51
Preliminary
Mechanical Information
Revision History (continued)
Version No.
Release Date
Page
Numbers
Description of Changes
v1.0
14-Sep-04
(continued)
Section 3, “Electrical Characteristics”
• Section 3.2, “Absolute Maximum Ratings”
— A1a renamed to VDD
X
4
4
5
— A4 “rating” changed to Analog (from ATD)
— A9 minimum changed to –0.3
— A12 maximum value removed, footnote reference added
5
— Table 8, Table 9 footnotes added regarding VDD5/VSS
5
7, 8
• Section 3.4, “Operating Conditions”
— C1 renamed to VDD
X
6
6
6
— C4 added (C5 to C11b renumbered)
— C8 maximum changed from 40 MHz to 50 MHz
• Section 3.5, “Input/Output Characteristics”
— Table 8 spec D4 updated (from TBD)
7
8
— Table 9 spec E4 changed to 1 μA to match D4
• Section 3.6, “Power Dissipation and Thermal Characteristics”
— Reworked Equation 1 through Equation 4 and supporting text
— Section 3.6.1 and Table 10 name changed from “Power Dissipation...”
• Section 3.7, “Power Supply”
9
10
— Added MAC71x1 designation and footnotes to Table 15 / Table 16
— Table 15 designated for 40 MHz, and
12
– Numerous TBD entries replaced with values
– Run Supply Current collapsed from fifteen spec items to one
– Removed separate Core/Regulator/Pins specs for Run/Pseudo Stop/Stop modes
– F1 and F3 descriptions changed
– F1, F2, F3 and F4 values updated
— Table 16 added for 50 MHz specifications
12
13
14
— Table 17, deleted IREG spec (Regulator Current in Reduced Power, Shutdown Modes)
— Table 18, VDD2.5 load capacitance typical changed, with clarification footnote
• Section 3.8, “Clock and Reset Generator”
— Table 19 updates
15
– Changed specs J1b and J6 maximum from 40 MHz to 50 MHz
– Reversed polarity of XCLKS reference in footnote (3)
– J1b maximum changed to 40 MHz
– VDCBIAS removed
– Added footnote to define tfsys as 1 ÷ fSYS for use elsewhere in the document
— Updated Section 3.8.2, “PLL Filter Characteristics”
— Table 20 updates
16
18
– Changed spec K3 maximum from 40 MHz to 50 MHz
– Added footnote to define tfsys as 1 ÷ fSYS for use elsewhere in the document
— Table 23 updates
– Removed VPORR and VPORA, as they duplicated H6
– Removed tWRS
• Section 3.9, “External Bus Timing”
19
20
21
— Table 24 updates
– M1 minimum changed from 25 ns to 20 ns (Figure 6 also updated)
– Reworded footnote (1)
– Added footnote (2) to define tCYC as 1 ÷ CLKOUT
— Table 25 updates
– Added footnote (1)
– Consolidated previous NOTES into footnote (2), (Figure 7, Figure 8 also updated)
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
52
Freescale Semiconductor
Preliminary
MechanicalInformation
Revision History (continued)
Version No.
Release Date
Page
Numbers
Description of Changes
v1.0
Section 3, “Electrical Characteristics” (continued)
14-Sep-04
(continued)
• Section 3.10, “Analog-to-Digital Converter”
— Rev. 0.1 redundant and superfluous content deleted
24
– Section 3.10.3, “ATD Electrical Specifications,” (included Table 29 and Table 30)
– Table 31, “ATD Performance Specifications” (redundant with v0.1 Table 27 and
Table 28, now Table 29 and Table 30)
— Table 26 updates
24
24
– Deleted previous spec M6
– Changed spec N7 and N8 values
— Table 27 updates
– Deleted previous spec N6
– Changed spec P7 and P8 values
– Changed spec P2 and footnote (1) to specify 3.15 V
— Table 28 updates
– Changed spec Q2 parameter classification from T to C and 10 pF and 22 pF values
moved from maximum to typical
— Table 29 updates
– Operating conditions VDDA minimum changed to 4.5 V
– VREF description moved from “conditions” header to new footnote (1)
— Table 30 updates
– Operating conditions VDDA minimum changed to 3.15 V
– VREF description moved from “conditions” header to new footnote (1)
— Table 31 updates
– Spec T1 description clarified, max removed, min added with footnote
– Spec T2 modified to show both edge- and level-sensitive modes
— Figure 10 modified to remove “Max Frequency” label and clearly separate edge- and
level-sensitive mode timing examples
25
26
26
28
28
29
• Section 3.11, “Serial Peripheral Interface”
— Table 32 updates
– Changed specs U1a, U1b and U4 to use fIPS and tIPS for clarity and consistency with
MAC7100RM
– Changed U1a max to ½ and U1b min to 2 to account for the DBR bit
— Table 33 updates
29
– Changed specs V1a, V1b, V2, V3, V4, V7, V8 to use fIPS and tIPS for clarity and
consistency with MAC7100RM
– Changed V1a max to ½ and V1b min to 2 to account for the DBR bit
• Section 3.13, “Common Flash Module”
— Significant rework to match MAC7100RM clock naming, references and timing
calculations for clarity and consistency
— Changed X1 maximum from 40 MHz to 50 MHz (Table 35)
32 to 35
34
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
53
Preliminary
Mechanical Information
Revision History (continued)
Version No.
Release Date
Page
Numbers
Description of Changes
v1.0
14-Sep-04
(continued)
Section 4, “Device Pin Assignments”
• Table 37 and Table 38 added
• Added PD2 label / footnote to Figure 15, Figure 17, Figure 19, Figure 20 and Figure 22 41, 43, 45, 46, 48
36, 40
• Section 4.2, “MAC7142 Pin Diagram” / Figure 16 added
• Section 4.3, “MAC7121 / MAC7126 Pin Diagram” / Figure 17 updated
— PB10 / PCS5_B / PCSS_B bonded out on pin 57, footnote for L49P
— Added MAC71x6 device information
42
43
• Section 4.4, “MAC7122 Pin Diagram” / Figure 18 added
• Section 4.5, “MAC7101 / MAC7106 Pin Diagram” / Figure 19 updated
— Added MAC71x6 device information
44
45
• Section 4.6, “MAC7111 / MAC7116 Pin Diagram” / Figure 20 updated
— Added AS to TA pin
46
— Added MAC71x6 device information
• Section 4.7, “MAC7112 Pin Diagram” / Figure 21 added
• Section 4.8, “MAC7131 Pin Diagram” / Figure 22 corrected, updated
— Changed pins C8 & P8 from VSS2.5 to VDD2.5
— Changed pin T8 from VSSPLL to VDDPLL
47
48
— Added AS to TA pin
• Section 4.9, “MAC7136 Pin Diagram” / Figure 23 added
49
v1.1
Section 3, “Electrical Characteristics”
1-Dec-04
• Section 3.7, “Power Supply”
— Table 15 spec F4 –40° C and 25° C max value changed
— Table 16 spec G4 –40° C and 25° C max value changed
• Section 3.8, “Clock and Reset Generator”
12
12
— Table 19 spec J3 typical TBD entry replaced with value
— Table 20 specs K15 and K16 maximum TBD entries replaced with values
15
18
v1.1.1
Section 3, “Electrical Characteristics”
3-Dec-04
• Section 3.7, “Power Supply”
— Table 15 spec F3 –40° C, 25° C and 125° C typ and max values and unit changed
— Table 16 spec G3 –40° C, 25° C and 125° C typ and max value and unit changed
12
12
v1.2
Section 1, “Overview”
10-Feb--06
• Moved 71x6 device numbers from footnote to “covered” list
1
Section 2, “Ordering Information”
• Added AF, AG and VM package identifiers to Figure 1
• Added 1L38Y to Table 1
2
2
Section 3, “Electrical Characteristics”
• Replaced TBD values in Table 15 and Table 16 with final qualification data, changed table
titles and footnotes to reflect 71x6 inclusion.
12
50
Section 5, “Mechanical Information”
• Removed obsolete package diagrams, replaced with document IDs available on web site.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
54
Freescale Semiconductor
Preliminary
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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Preliminary
55
Freescale Semiconductor
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MAC7100EC
Rev. 1.2, 02/2006
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