MC145027P [FREESCALE]
Encoder and Decoder Pairs CMOS; 编码器和译码器对CMOS
| 型号： | MC145027P |
| 厂家： | 
Freescale |
| 描述： | Encoder and Decoder Pairs CMOS |
| 文件： | 总20页 (文件大小：698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC145026/D
Rev. 4, 1/2005
Freescale Semiconductor
Technical Data
MC145026, MC145027
MC145028
16
16
1
1
MC145026, MC145027,
MC145028
Encoder and Decoder Pairs
CMOS
P Suffix
Plastic DIP
Case 648
D Suffix
SOG Package
Case751B
16
1
DW Suffix
SOG Package
Case 751G
1 Introduction
Ordering Information
These devices are designed to be used as
encoder/decoder pairs in remote control applications.
Device
Package
MC145026P
MC145026D
MC145027P
MC145027DW
MC145028P
MC145028DW
Plastic DIP
SOG Package
Plastic DIP
The MC145026 encodes nine lines of information and
serially sends this information upon receipt of a transmit
enable (TE) signal. The nine lines may be encoded with
trinary data (low, high, or open) or binary data (low or
high). The words are transmitted twice per encoding
sequence to increase security.
SOG Package
Plastic DIP
SOG Package
Contents
The MC145027 decoder receives the serial stream and
interprets five of the trinary digits as an address code.
Thus, 243 addresses are possible. If binary data is used at
the encoder, 32 addresses are possible. The remaining
serial information is interpreted as four bits of binary
data. The valid transmission (VT) output goes high on
the MC145027 when two conditions are met. First, two
addresses must be consecutively received (in one
encoding sequence) which both match the local address.
Second, the 4 bits of data must match the last valid data
received. The active VT indicates that the information at
the Data output pins has been updated.
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Electrical Specifications . . . . . . . . . . . . . . . . 4
3 Operating Characteristics . . . . . . . . . . . . . . . 8
4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . 9
5 MC145027 and MC145028 Timing . . . . . . . . 16
6 Package Dimensions . . . . . . . . . . . . . . . . . . 18
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Introduction
The MC145028 decoder treats all nine trinary digits as an address which allows 19,683 codes. If binary
data is encoded, 512 codes are possible. The VT output goes high on the MC145028 when two addresses
are consecutively received (in one encoding sequence) which both match the local address.
•
•
•
•
•
•
•
Operating Temperature Range: - 40 to + 85°C
Very-Low Standby Current for the Encoder: 300 nA Maximum @ 25°C
Interfaces with RF, Ultrasonic, or Infrared Modulators and Demodulators
RC Oscillator, No Crystal Required
High External Component Tolerance; Can Use ± 5% Components
Internal Power-On Reset Forces All Decoder Outputs Low
Operating Voltage Range:
MC145026 = 2.5 to 18 V
MC145027, MC145028 = 4.5 to 18 V
MC145026
ENCODER
MC145027
DECODERS
MC145028
DECODERS
A1
A2
A3
VDD
A6
A1
A2
A3
VDD
D6
A1
A2
A3
VDD
Dout
A7
D7
TE
A4
A5
A8
A4
A5
D8
A4
A5
RTC
CTC
RS
A9
D9
R1
VT
R1
VT
A6/D6
A7/D7
VSS
C1
R2/C2
Din
C1
R2/C2
Din
A9/D9
A8/D8
VSS
VSS
Figure 1. Pin Assignments
MC145026, MC145027, MC145028 Technical Data, Rev. 4
2
Freescale Semiconductor
Introduction
RS
RTC
CTC
13
11
14
12
3-PIN
TE
DATA SELECT
AND
15
÷ 4
DIVIDER
OSCILLATOR
AND
DOUT
BUFFER
ENABLE
RING COUNTER AND 1-OF-9 DECODER
9
8
7
6
5
4
3
2
1
1
2
A1
A2
A3
3
4
A4
5
TRINARY
DETECTOR
A5
6
A6/D6
A7/D7
A8/D8
A9/D9
7
VDD = PIN 16
VSS = PIN 8
9
10
Figure 2. MC145026 Encoder Block Diagram
11
VT
15
14
D6
CONTROL
LOGIC
D7
13
12
D8
D9
SEQUENCER CIRCUIT
5
4
3
2
1
1
2
3
4
A1
A2
DATA
EXTRACTOR
9
A3
A4
Din
C2
R2
C
1 7
6
10
VDD = PIN 16
VSS = PIN 8
5
A5
R1
Figure 3. MC145027 Decoder Block Diagram
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
3
Electrical Specifications
11
CONTROL
LOGIC
VT
SEQUENCER CIRCUIT
9
8
7
6
5
4
3
2
1
1
2
3
4
5
A1
9-BIT
SHIFT
REGISTER
A2
A3
A4
9
DATA
EXTRACTOR
A5
A6
A7
A8
Din
15
14
13
12
C2
VDD = PIN 16
VSS = PIN 8
C
1 7
6
R1
10
R2
A9
Figure 4. MC145028 Decoder Block Diagram
2 Electrical Specifications
Table 1. Maximum Ratings* (Voltages Referenced to V
)
SS
Ratings
Symbol
Value
- 0.5 to + 18
Unit
DC Supply Voltage
VDD
Vin
Vout
Iin
V
V
DC Input Voltage
- 0.5 to VDD + 0.5
DC Output Voltage
- 0.5 to VDD + 0.5
V
DC Input Current, per Pin
DC Output Current, per Pin
Power Dissipation, per Package
Storage Temperature
± 10
± 10
mA
mA
mW
°C
°C
Iout
PD
500
Tstg
TL
- 65 to + 150
260
Lead Temperature, 1 mm from Case for 10 Seconds
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum
rated voltages to this high-impedance circuit. For proper operation, V and V should be constrained to
in
out
the range VSS ≤ (V or V ) ≤ VDD.
in
out
MC145026, MC145027, MC145028 Technical Data, Rev. 4
4
Freescale Semiconductor
Electrical Specifications
Table 2. Electrical Characteristics - MC145026 , MC145027, and MC145028
1
(Voltage Referenced to V
)
SS
Guaranteed Limit
VDD
V
Symbol
Characteristic
- 40°C
25°C
85°C
Max
Unit
Min
Max
Min
Max
Min
VOL
VOH
VIL
Low-Level Output Voltage
(Vin = VDD or 0) 5.0
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
V
V
V
10
15
High-Level Output Voltage
(Vin = 0 or VDD
)
5.0
10
15
4.95
9.95
14.95
-
-
-
4.95
9.95
14.95
-
-
-
4.95
9.95
14.95
-
-
-
Low-Level Input Voltage
(Vout = 4.5 or 0.5 V) 5.0
(Vout = 9.0 or 1.0 V) 10
(Vout = 13.5 or 1.5 V) 15
-
-
-
1.5
3.0
4.0
-
-
-
1.5
3.0
4.0
-
-
-
1.5
3.0
4.0
VIH
High-Level Input Voltage
V
(Vout = 0.5 or 4.5 V) 5.0
(Vout = 1.0 or 9.0 V) 10
(Vout = 1.5 or 13.5 V) 15
3.5
7.0
11
-
-
-
3.5
7.0
11
-
-
-
3.5
7.0
11
-
-
-
IOH
High-Level Output Current
mA
(Vout = 2.5 V) 5.0
(Vout = 4.6 V) 5.0
(Vout = 9.5 V) 10
(Vout = 13.5 V) 15
- 2.5
- 0.52
- 1.3
-
-
-
-
- 2.1
- 0.44
- 1.1
-
-
-
-
- 1.7
- 0.36
- 0.9
-
-
-
-
- 3.6
- 3.0
- 2.4
IOL
Low-Level Output Current
Input Current - TE
mA
(Vout = 0.4 V) 5.0
(Vout = 0.5 V) 10
(Vout = 1.5 V) 15
0.52
1.3
3.6
-
-
-
0.44
1.1
3.0
-
-
-
0.36
0.9
2.4
-
-
-
Iin
5.0
10
15
-
-
-
-
-
-
3.0
16
35
11
60
120
-
-
-
-
-
-
µA
(MC145026, Pull-Up Device)
Iin
Input Current
RS (MC145026), Din (MC145027, MC145028)
15
-
± 0.3
-
± 0.3
-
± 1.0
µA
µA
Iin
Input Current
A1 - A5, A6/D6 - A9/D9 (MC145026),
A1 - A5 (MC145027),
A1 - A9 (MC145028)
5.0
10
15
-
-
-
-
-
-
-
-
-
± 110
± 500
± 1000
-
-
-
-
-
-
Cin
IDD
Input Capacitance (Vin = 0)
-
-
-
-
7.5
-
-
pF
Quiescent Current - MC145026
5.0
10
15
-
-
-
-
-
-
-
-
-
0.1
0.2
0.3
-
-
-
-
-
-
µA
IDD
Quiescent Current - MC145027, MC145028
5.0
10
15
-
-
-
-
-
-
-
-
-
50
100
150
-
-
-
-
-
-
µA
1
Also see next Electrical Characteristics table for 2.5 V specifications.
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
5
Electrical Specifications
Table 2. Electrical Characteristics - MC145026 , MC145027, and MC145028 (continued)
1
(Voltage Referenced to V
)
SS
Guaranteed Limit
VDD
V
Symbol
Characteristic
- 40°C
25°C
85°C
Max
Unit
Min
Max
Min
Max
Min
5.0
10
15
-
-
-
-
-
-
-
-
-
200
400
600
-
-
-
-
-
-
µA
µA
Idd
Dynamic Supply Current - MC145026
(fc = 20 kHz)
5.0
10
15
-
-
-
-
-
-
-
-
-
400
800
1200
-
-
-
-
-
-
Idd
Dynamic Supply Current - MC145027,
MC145028 (fc = 20 kHz)
1
Also see next Electrical Characteristics table for 2.5 V specifications.
Table 3. Electrical Characteristics - MC145026 (Voltage Referenced to V
)
SS
Guaranteed Limit
25°C
Max
VDD
V
Symbol
Characteristic
- 40°C
85°C
Unit
Min
Max
Min
Min
Max
VOL
VOH
VIL
VIH
IOH
IOL
Iin
Low-Level Output Voltage
(Vin = 0 V or VDD
)
2.5
2.5
-
0.05
-
2.45
-
0.05
-
-
0.05
V
V
High-Level Output Voltage (Vin = 0 V or VDD
)
2.45
-
2.45
-
Low-Level Input Voltage (Vout = 0.5 V or 2.0 V) 2.5
High-Level Input Voltage (Vout = 0.5 V or 2.0 V) 2.5
-
0.3
0.3
-
-
0.3
V
2.2
-
-
-
-
-
-
-
2.2
0.25
0.2
0.09
-
2.2
-
-
-
-
-
-
-
V
High-Level Output Current
Low-Level Output Current
(Vout = 1.25 V) 2.5
(Vout = 0.4 V) 2.5
0.28
-
0.2
mA
mA
µA
µA
µA
µA
0.22
-
0.16
Input Current (TE - Pull-Up Device)
Input Current (A1-A5, A6/D6-A9/D9)
Quiescent Current
2.5
2.5
2.5
2.5
-
-
-
-
1.8
± 25
0.05
40
-
-
-
-
Iin
IDD
Idd
-
Dynamic Supply Current (fc = 20 kHz)
-
MC145026, MC145027, MC145028 Technical Data, Rev. 4
6
Freescale Semiconductor
Electrical Specifications
Table 4. Switching Characteristics - MC145026 , MC145027, and MC145028 (C = 50 pF, T = 25°C)
1
L
A
Guaranteed Limit
Figure
No.
Symbol
Characteristic
Output Transition Time
VDD
Unit
Min
Max
tTLH, tTHL
5, 9
5.0
10
15
-
-
-
200
100
80
ns
tr
tf
Din Rise Time - Decoders
6
5.0
10
15
-
-
-
15
15
15
µs
µs
Din Fall Time - Decoders
6
5.0
10
15
-
-
-
15
5.0
4.0
fosc
Encoder Clock Frequency
7
5.0
10
15
0.001
0.001
0.001
2.0
5.0
10
MHz
kHz
ns
f
Decoder Frequency - Referenced to Encoder Clock
TE Pulse Width - Encoders
13
8
5.0
10
15
1.0
1.0
1.0
240
410
450
tw
5.0
10
15
65
30
20
-
-
-
1
Also see next Electrical Characteristics table for 2.5 V specifications.
Table 5. Switching Characteristics - MC145026 (C = 50 pF, T = 25°C)
L
A
Guaranteed Limit
Figure
No.
Symbol
Characteristic
Output Transition Time
VDD
Unit
Min
Max
tTLH, tTHL
5, 9
7
2.5
2.5
2.5
-
450
250
-
ns
kHz
µs
fosc
tw
Encoder Clock Frequency
TE Pulse Width
1.0
1.5
8
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
7
Operating Characteristics
tf
tf
90%
ANY OUTPUT
VDD
VSS
90%
10%
Din
10%
tTLH
tTHL
Figure 5. Output Transition Time
Figure 6. D Rise and Fall Time
in
t/fOSC
VDD
TE
50%
tW
VSS
50%
RTC
Figure 7. Encoder Clock Frequency
Figure 8. TE Pulse Width
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and fixture capacitance.
Figure 9. Test Circuit
3 Operating Characteristics
3.1
MC145026
The encoder serially transmits trinary data as defined by the state of the A1 - A5 and A6/D6 - A9/D9 input
pins. These pins may be in either of three states (low, high, or open) allowing 19,683 possible codes. The
transmit sequence is initiated by a low level on the TE input pin. Upon power-up, the MC145026 can
continuously transmit as long as TE remains low (also, the device can transmit two-word sequences by
pulsing TE low). However, no MC145026 application should be designed to rely upon the first data word
transmitted immediately after power-up because this word may be invalid. Between the two data words,
no signal is sent for three data periods (see Figure 11).
Each transmitted trinary digit is encoded into pulses (see Figure 12). A logic 0 (low) is encoded as two
consecutive short pulses, a logic 1 (high) as two consecutive long pulses, and an open (high impedance)
as a long pulse followed by a short pulse. The input state is determined by using a weak “output” device
to try to force each input high then low. If only a high state results from the two tests, the input is assumed
to be hardwired to V . If only a low state is obtained, the input is assumed to be hardwired to V . If both
DD
SS
a high and a low can be forced at an input, an open is assumed and is encoded as such. The “high” and
MC145026, MC145027, MC145028 Technical Data, Rev. 4
8
Freescale Semiconductor
Pin Descriptions
“low” levels are 70% and 30% of the supply voltage as shown in the Electrical Characteristics table. The
weak “output” device sinks/sources up to 110 µA at a 5 V supply level, 500 µA at 10 V, and 1 mA at 15 V.
The TE input has an internal pull-up device so that a simple switch may be used to force the input low.
While TE is high, the encoder is completely disabled, the oscillator is inhibited, and the current drain is
reduced to quiescent current. When TE is brought low, the oscillator is started and the transmit sequence
begins. The inputs are then sequentially selected, and determinations are made as to the input logic states.
This information is serially transmitted via the D pin.
out
3.2
MC145027
This decoder receives the serial data from the encoder and outputs the data, if it is valid. The transmitted
data, consisting of two identical words, is examined bit by bit during reception. The first five trinary digits
are assumed to be the address. If the received address matches the local address, the next four (data) bits
are internally stored, but are not transferred to the output data latch. As the second encoded word is
received, the address must again match. If a match occurs, the new data bits are checked against the
previously stored data bits. If the two nibbles of data (four bits each) match, the data is transferred to the
output data latch by VT and remains until new data replaces it. At the same time, the VT output pin is
brought high and remains high until an error is received or until no input signal is received for four data
periods (see Figure 11).
Although the address information may be encoded in trinary, the data information must be either a 1 or 0.
A trinary (open) data line is decoded as a logic 1.
3.3
MC145028
This decoder operates in the same manner as the MC145027 except that nine address lines are used and
no data output is available. The VT output is used to indicate that a valid address has been received. For
transmission security, two identical transmitted words must be consecutively received before a VT output
signal is issued.
The MC145028 allows 19,683 addresses when trinary levels are used. 512 addresses are possible when
binary levels are used.
4 Pin Descriptions
4.1
MC145026 Encoder
A1 - A5, A6/D6 - A9/D9
Address, Address/Data Inputs (Pins 1 - 7, 9, and 10)
These address/data inputs are encoded and the data is sent serially from the encoder via the D pin.
out
R , C , R
TC
S
TC
(Pins 11, 12, and 13)
These pins are part of the oscillator section of the encoder (see Figure 10).
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
9
Pin Descriptions
If an external signal source is used instead of the internal oscillator, it should be connected to the R input
S
and the R and C pins should be left open.
TC
TC
TE
Transmit Enable (Pin 14)
This active-low transmit enable input initiates transmission when forced low. An internal pull-up device
keeps this input normally high. The pull-up current is specified in the Electrical Characteristics table.
D
out
Data Out (Pin 15)
This is the output of the encoder that serially presents the encoded data word.
V
SS
Negative Power Supply (Pin 8)
The most-negative supply potential. This pin is usually ground.
V
DD
Positive Power Supply (Pin 16)
The most-positive power supply pin.
4.2
MC145027 and MC145028 Decoders
A1 - A5, A1 - A9
Address Inputs (Pins 1 - 5)-MC145027,
Address Inputs (Pins 1 - 5, 15, 14, 13, 12)-MC145028
These are the local address inputs. The states of these pins must match the appropriate encoder inputs for
the VT pin to go high. The local address may be encoded with trinary or binary data.
D6 - D9
Data Outputs (Pins 15, 14, 13, 12)-MC145027 Only
These outputs present the binary information that is on encoder inputs A6/D6 through A9/D9. Only binary
data is acknowledged; a trinary open at the MC145026 encoder is decoded as a high level (logic 1).
D
in
Data In (Pin 9)
This pin is the serial data input to the decoder. The input voltage must be at CMOS logic levels. The signal
source driving this pin must be dc coupled.
MC145026, MC145027, MC145028 Technical Data, Rev. 4
10
Freescale Semiconductor
Pin Descriptions
R , C
1
1
Resistor 1, Capacitor 1 (Pins 6, 7)
As shown in Figure 3 and Figure 4, these pins accept a resistor and capacitor that are used to determine
whether a narrow pulse or wide pulse has been received. The time constant R × C should be set to
1
1
1.72 encoder clock periods:
R C = 3.95 R C
TC TC
1
1
R /C
2
2
Resistor 2/Capacitor 2 (Pin 10)
As shown in Figure 3 and Figure 4, this pin accepts a resistor and capacitor that are used to detect both the
end of a received word and the end of a transmission. The time constant R x C should be 33.5 encoder
2
2
clock periods (four data periods per Figure 12): R C = 77 R C . This time constant is used to
2
2
TC TC
determine whether the D pin has remained low for four data periods (end of transmission). A separate
in
on-chip comparator looks at the voltage-equivalent two data periods (0.4 R C ) to detect the dead time
2
2
between received words within a transmission.
VT
Valid Transmission Output (Pin 11)
This valid transmission output goes high after the second word of an encoding sequence when the
following conditions are satisfied:
1. the received addresses of both words match the local decoder address, and
2. the received data bits of both words match.
VT remains high until either a mismatch is received or no input signal is received for four data periods.
V
SS
Negative Power Supply (Pin 8)
The most-negative supply potential. This pin is usually ground.
V
DD
Positive Power Supply (Pin 16)
The most-positive power supply pin.
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
11
Pin Descriptions
RS
CTC
RTC
11
12
13
INTERNAL
ENABLE
This oscillator operates at a frequency determined by the
external RC network; i.e.,
1
(Hz)
f ≈
The value for RS should be chosen to be ≥ 2 times RTC. This range ensures that
current through RS is insignificant compared to current through RTC. The upper
limit for RS must ensure that RS x 5 pF (input capacitance) is small compared to
2.3 RTC CTC
′
for 1 kHz ≤ f ≤ 400 kHz
RTC x CTC
.
where: CTC′ = CTC + Clayout + 12 pF
RS ≈ 2 RTC
For frequencies outside the indicated range, the formula is less accurate. The
minimum recommended oscillation frequency of this circuit is 1 kHz. Susceptibility
to externally induced noise signals may occur for frequencies below 1 kHz and/or
when resistors utilized are greater than 1 MΩ.
RS ≥ 20 k
RTC ≥ 10 k
400 pF < CTC < 15 µF
Figure 10. Encoder Oscillator Information
ENCODER
PWmin
2 WORD
TRANSMISSION
TE
CONTINUOUS
TRANSMISSION
ENCODER
OSCILLATOR
(PIN 12)
1ST
9TH
1ST
9TH
DIGIT
DIGIT
DIGIT
DIGIT
Dout
(PIN 15)
HIGH
OPEN
LOW
1ST WORD
2ND WORD
ENCODING SEQUENCE
1.1 (R2C2)
DECODER
VT
(PIN 11)
DATA OUTPUTS
Figure 11. Timing Diagram
MC145026, MC145027, MC145028 Technical Data, Rev. 4
12
Freescale Semiconductor
Pin Descriptions
ENCODER
OSCILLATOR
(PIN 12)
ENCODED
“ONE”
Dout
(PIN 15)
ENCODED
“ZERO”
ENCODED
“OPEN”
DATA PERIOD
Figure 12. Encoder Data Waveforms
500
400
V
DD = 15 V
VDD = 10 V
300
200
100
VDD = 5 V
10
20
30
40
50
Clayout (pF) ON PINS 1 - 5 (MC145027);
PINS 1 - 5 AND 12 - 15 (MC145028)
Figure 13. f
vs C
- Decoders Only
layout
max
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
13
Pin Descriptions
HAS THE
TRANSMISSION
BEGUN?
NO
YES
DOES
THE 5-BIT
ADDRESS MATCH
THE ADDRESS
PINS?
DISABLE VT
ON THE 1ST
ADDRESS MISMATCH
NO
YES
STORE
THE
4-BIT
DATA
DOES
THIS DATA
MATCH THE
PREVIOUSLY
STORED
DISABLE VT
ON THE 1ST
DATA MISMATCH
NO
NO
DATA?
YES
IS THIS
AT LEAST THE
2ND CONSECUTIVE
MATCH SINCE VT
DISABLE?
YES
LATCH DATA
ONTO OUTPUT
PINS AND
ACTIVATE VT
HAVE
4-BIT TIMES
PASSED?
YES
DISABLE
VT
NO
HAS
A NEW
NO
TRANSMISSION
BEGUN?
YES
Figure 14. MC145027 Flowchart
MC145026, MC145027, MC145028 Technical Data, Rev. 4
14
Freescale Semiconductor
Pin Descriptions
HAS THE
TRANSMISSION
BEGUN?
NO
YES
DOES
THE ADDRESS
MATCH THE
ADDRESS
PINS?
DISABLE VT ON THE
1ST ADDRESS
MISMATCH AND IGNORE
THE REST OF
NO
THIS WORD
YES
IS THIS
AT LEAST THE
2ND CONSECUTIVE
MATCH SINCE VT
DISABLE?
NO
YES
ACTIVATE VT
HAVE
4-BIT TIMES
PASSED?
YES
DISABLE VT
NO
HAS A
NEW TRANSMISSION
BEGUN?
NO
YES
Figure 15. MC145028 Flowchart
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
15
MC145027 and MC145028 Timing
5 MC145027 and MC145028 Timing
To verify the MC145027 or MC145028 timing, check the waveforms on C1 (Pin 7) and R2/C2 (Pin 10) as
compared to the incoming data waveform on D (Pin 9).
in
The R-C decay seen on C1 discharges down to 1/3 V before being reset to V . This point of reset
DD
DD
(labelled “DOS” in Figure 16) is the point in time where the decision is made whether the data seen on D
in
is a 1 or 0. DOS should not be too close to the D data edges or intermittent operation may occur.
in
The other timing to be checked on the MC145027 and MC145028 is on R2/C2 (see Figure 17). The R-C
decay is continually reset to V as data is being transmitted. Only between words and after the
DD
end-of-transmission (EOT) does R2/C2 decay significantly from V . R2/C2 can be used to identify the
DD
internal end-of-word (EOW) timing edge which is generated when R2/C2 decays to 2/3 V . The internal
DD
EOT timing edge occurs when R2/C2 decays to 1/3 V . When the waveform is being observed, the R-C
DD
decay should go down between the 2/3 and 1/3 V levels, but not too close to either level before data
DD
transmission on D resumes.
in
Verification of the timing described above should ensure a good match between the MC145026 transmitter
and the MC145027 and MC145028 receivers.
VDD
Din
0 V
VDD
2/3
C1
1/3
0 V
DOS
DOS
Figure 16. R-C Decay on Pin 7 (C1)
EOW
VDD
2/3
1/3
0 V
R2/C2
EOT
Figure 17. R-C Decay on Pin 10 (R2/C2)
MC145026, MC145027, MC145028 Technical Data, Rev. 4
16
Freescale Semiconductor
MC145027 and MC145028 Timing
VDD
VDD
VDD
TE
14
VDD
A1
0.1 µF
0.1 µF
A1
16
16
5
A2
A3
A4
A5
A2
1
Din
Dout
9
6
15
1
2
3
TRINARY
ADDRESSES
5
2
A3
A4
A5
TRINARY
ADDRESSES
3
4
5
R1
C1
4
5
6
7
9
7
MC145027
MC145026
RTC
13
12
11
15
14
13
12
11
D6
D7
D8
D9
D6
D7
D8
D9
CTC
4-BIT
BINARY
DATA
10
10
RS
VT
R2
8
C2
8
CTC′ = CTC + Clayout + 12 pF
100 pF ≤ CTC ≤ 15 µF
RTC ≥ 10 kΩ; RS ≈ 2 RTC
R1 ≥ 10 kΩ
1
REPEAT OF ABOVE
REPEAT OF ABOVE
fosc
=
2.3 RTCCTC
′
R1C1 = 3.95 RTCCTC
R2C2 = 77 RTCCTC
C1 ≥ 400 pF
R2 ≥ 100 kΩ
C2 ≥ 700 pF
Example R/C Values (All Resistors and Capacitors are ± 5%)
(CTC′ = CTC + 20 pF)
fosc (kHz)
RTC
CTC′
RS
R1
C1
R2
C2
362
181
10 k
10 k
10 k
10 k
10 k
10 k
50 k
120 pF
240 pF
490 pF
1020 pF
2020 pF
5100 pF
5100 pF
20 k
20 k
20 k
20 k
20 k
20 k
100 k
10 k
10 k
10 k
10 k
10 k
10 k
50 k
470 pF
910 pF
100 k
100 k
100 k
100 k
100 k
200 k
200 k
910 pF
1800 pF
3900 pF
7500 pF
0.015 µF
0.02 µF
0.1 µF
88.7
42.6
21.5
8.53
1.71
2000 pF
3900 pF
8200 pF
0.02 µF
0.02 µF
Figure 18. Typical Application
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
17
Package Dimensions
6 Package Dimensions
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-A-
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
16
1
9
B
S
8
INCHES
MILLIMETERS
DIM MIN
MAX MIN MAX
0.770 18.80 19.55
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
C
L
0.270
0.175
0.021
0.70
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
-T-
G
H
J
K
L
0.100 BSC
0.050 BSC
2.54 BSC
1.27 BSC
M
K
0.008
0.015
0.130
0.305
10˚
0.21
0.38
3.30
7.74
10˚
H
J
0.110
0.295
0˚
2.80
7.50
0˚
G
D 16 PL
M
S
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T
A
Figure 19. Outline Dimensions for P SUFFIX
PLASTIC DIP (DUAL IN-LINE PACKAGE)
(Case Outline 648-08, Issue R)
M
0.25
B
1.75
A
6.2
1.35
0.25
0.10
8X 5.8
PIN'S
NUMBER
0.49
0.35
0.25
16X
6
1
16
M
T A B
14X
1.27
PIN 1 INDEX
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
10.0
9.8
4
A
A
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15mm PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.25mm PER SIDE.THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
8
9
SEATING
T
16X
PLANE
4.0
B
3.8
0.1 T
5
6. THIS DIMENSION DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT CAUSE
THE LEAD WIDTH TO EXCEED 0.62mm.
0.50
0.25 X45˚
0.25
0.19
1.25
0.40
7˚
0˚
SECTION A-A
Figure 20. Outline Dimensions for D SUFFIX
SOG (SMALL OUTLINE GULL-WING) PACKAGE
(Case Outline 751B-05, Issue K)
MC145026, MC145027, MC145028 Technical Data, Rev. 4
18
Freescale Semiconductor
Package Dimensions
M
0.25
B
2.65
2.35
A
0.25
0.10
10.55
10.05
8X
PIN'S
NUMBER
0.49
16X 0.35
0.25
6
M
16
T A B
1
PIN 1 INDEX
14X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
10.45
10.15
1.27
4
A
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS A AND B TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
A
8
9
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15mm PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSIONS.
INTER-LEAD FLASH AND PROTRUSIONS
SHALL NOT EXCEED 0.25mm PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT
THE PLASTIC BODY.
SEATING
PLANE
T
16X
7.6
7.4
B
0.1 T
5
0.75
˚
0.25 X45
0.32
0.23
6. THIS DIMENSION DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL NOT CAUSE
THE LEAD WIDTH TO EXCEED 0.62mm.
1.0
0.4
7˚
0˚
SECTION A-A
Figure 21. Outline Dimensions for DW SUFFIX
SOG (SMALL OUTLINE GULL-WING) PACKAGE
(Case Outline 751G-04, Issue D)
MC145026, MC145027, MC145028 Technical Data, Rev. 4
Freescale Semiconductor
19
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MC145026/D
Rev. 4
1/2005
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