MC145151DW2 [FREESCALE]
PLL Frequency Synthesizers (CMOS); PLL频率合成器（ CMOS ）
| 型号： | MC145151DW2 |
| 厂家： | 
Freescale |
| 描述： | PLL Frequency Synthesizers (CMOS) |
| 文件： | 总24页 (文件大小：590K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC145151-2/D
Rev. 5, 12/2004
Freescale Semiconductor
Technical Data
MC145151-2
MC145152-2
28
28
1
1
MC145151-2 and
MC145152-2
PLL Frequency Synthesizers
(CMOS)
Package Information
DW Suffix
SOG Package
Case 751F
P Suffix
Plastic DIP
Case 710
Ordering Information
Device
Package
MC145151P2
MC145151DW2
MC145152P2
MC145152DW2
Plastic DIP
SOG Package
Plastic DIP
The devices described in this document are typically
used as low-power, phase-locked loop frequency
synthesizers. When combined with an external low-pass
filter and voltage-controlled oscillator, these devices can
provide all the remaining functions for a PLL frequency
synthesizer operating up to the device's frequency limit.
For higher VCO frequency operation, a down mixer or a
prescaler can be used between the VCO and the
synthesizer IC.
SOG Package
Contents
1 MC145151-2 Parallel-Input (Interfaces with
Single-Modulus Prescalers) . . . . . . . . . . . . . 2
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . 6
2 MC145152-2 Parallel-Input (Interfaces with
Dual-Modulus Prescalers) . . . . . . . . . . . . . . . 7
2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Typical Applications . . . . . . . . . . . . . . . . . . 10
These frequency synthesizer chips can be found in the
following and other applications:
CATV
TV Tuning
AM/FM Radios
Two-Way Radios
Scanning Receivers
Amateur Radio
3 MC145151-2 and MC145152-2
Electrical Characteristics . . . . . . . . . . . . . . 12
4 Design Considerations . . . . . . . . . . . . . . . . 18
OSC
÷ R
÷ N
4.1 Phase-Locked Loop — Low-Pass Filter
Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CONTROL
LOGIC
φ
4.2 Crystal Oscillator Considerations . . . . . . . . 19
4.3 Dual-Modulus Prescaling . . . . . . . . . . . . . . 21
5 Package Dimensions . . . . . . . . . . . . . . . . . . 23
÷ A
÷ P/P + 1
VCO
OUTPUT FREQUENCY
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its
products.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
1 MC145151-2 Parallel-Input (Interfaces with
Single-Modulus Prescalers)
The MC145151-2 is programmed by 14 parallel-input data lines for the N counter and three input lines for
the R counter. The device features consist of a reference oscillator, selectable-reference divider,
digital-phase detector, and 14-bit programmable divide-by-N counter.
The MC145151-2 is an improved-performance drop-in replacement for the MC145151-1. The power
consumption has decreased and ESD and latch-up performance have improved.
1.1
Features
•
Operating Temperature Range: - 40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
•
•
•
•
•
•
•
•
•
•
•
On- or Off-Chip Reference Oscillator Operation
Lock Detect Signal
÷ N Counter Output Available
Single Modulus/Parallel Programming
8 User-Selectable ÷ R Values: 8, 128, 256, 512, 1024, 2048, 2410, 8192
÷ N Range = 3 to 16383
“Linearized” Digital Phase Detector Enhances Transfer Function Linearity
Two Error Signal Options: Single-Ended (Three-State) or Double-Ended
Chip Complexity: 8000 FETs or 2000 Equivalent Gates
1
2
3
4
fin
28 LD
•
VSS
27 OSCin
VDD
26 OSCout
25 N11
24 N10
23 N13
22 N12
21 T/R
20 N9
PDout
RA0 5
RA1 6
RA2
φR
7
8
9
φV
fV 10
N0 11
N1 12
19 N8
18 N7
17 N6
N2 13
N3 14
16 N5
15 N4
Figure 1. MC145151-2 Pin Assignment
MC145151-2 and MC145152-2 Technical Data, Rev. 5
2
Freescale Semiconductor
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
RA2
RA1
RA0
14 x 8 ROM REFERENCE DECODER
OSCout
OSCin
LOCK
DETECT
14
LD
14-BIT ÷ R COUNTER
PHASE
DETECTOR
A
PDout
fin
14-BIT ÷ N COUNTER
VDD
PHASE
DETECTOR
B
φV
φR
14
TRANSMIT OFFSET ADDER
T/R
fV
N13
N11 N9
N7 N6
N4
N2
N0
NOTE: N0 - N13 inputs and inputs RA0, RA1, and RA2 have pull-up resistors that are not shown.
Figure 2. MC145151-2 Block Diagram
1.2
Pin Descriptions
1.2.1
Input Pins
f
in
Frequency Input (Pin 1)
Input to the ÷N portion of the synthesizer. f is typically derived from loop VCO and is ac coupled into
in
the device. For larger amplitude signals (standard CMOS logic levels) dc coupling may be used.
RA0 - RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight possible divide values for the total reference
divider, as defined by the table below.
Pull-up resistors ensure that inputs left open remain at a logic 1 and require only a SPST switch to alter
data to the zero state.
Reference Address Code
Total
Divide
Value
RA2
RA1
RA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
128
256
512
1024
2048
2410
8192
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
3
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
N0 - N11
N Counter Programming Inputs (Pins 11 - 20, 22 - 25)
These inputs provide the data that is preset into the ÷N counter when it reaches the count of zero. N0 is
the least significant and N13 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only an SPST switch to alter data to the zero state.
T/R
Transmit/Receive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided at the N inputs. This is normally used for offsetting
the VCO frequency by an amount equal to the IF frequency of the transceiver. This offset is fixed at 856
when T/R is low and gives no offset when T/R is high. A pull-up resistor ensures that no connection will
appear as a logic 1 causing no offset addition.
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC to
in
ground and OSC to ground. OSC may also serve as the input for an externally-generated reference
out
in
signal. This signal is typically ac coupled to OSC , but for larger amplitude signals (standard CMOS logic
in
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC .
out
1.2.2
Output Pins
PD
out
Phase Detector A Output (Pin 4)
Three-state output of phase detector for use as loop-error signal. Double-ended outputs are also available
for this purpose (see φ and φ ).
V
R
Frequency f > f or f Leading: Negative Pulses
V
R
V
Frequency f < f or f Lagging: Positive Pulses
V
R
V
Frequency f = f and Phase Coincidence: High-Impedance State
V
R
φ , φ
R
V
Phase Detector B Outputs (Pins 8, 9)
These phase detector outputs can be combined externally for a loop-error signal. A single-ended output is
also available for this purpose (see PD ).
out
If frequency f is greater than f or if the phase of f is leading, then error information is provided by φ
V
V
R
V
pulsing low. φ remains essentially high.
R
If the frequency f is less than f or if the phase of f is lagging, then error information is provided by φ
V
R
V
R
pulsing low. φ remains essentially high.
V
If the frequency of f = f and both are in phase, then both φ and φ remain high except for a small
V
R
V
R
minimum time period when both pulse low in phase.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
4
Freescale Semiconductor
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
f
V
N Counter Output (Pin 10)
This is the buffered output of the ÷ N counter that is internally connected to the phase detector input. With
this output available, the ÷ N counter can be used independently.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (f , f of same phase and frequency). Pulses low when loop
R
V
is out of lock.
1.2.3
Power Supply
V
DD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range from + 3 to + 9 V with respect to V .
SS
V
SS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually ground.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
5
MC145151-2 Parallel-Input (Interfaces with Single-Modulus Prescalers)
1.3
Typical Applications
2.048 MHz
NC
NC
OSCin
OSCout
fin
RA2 RA1
RA0
PDout
VOLTAGE
CONTROLLED
OSCILLATOR
MC145151-2
N13 N12 N11 N10
N9 N8 N7 N6 N5 N4 N3 N2 N1 N0
5 - 5.5 MHz
0 1 1 1 0 0 0 1 0 0 0 = 5 MHz
1 0 1 0 1 1 1 1 1 0 0 = 5.5 MHz
Figure 3. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing = 1 kHz
LOCK DETECT SIGNAL
TRANSMIT: 440.0 - 470.0 MHz
RECEIVE: 418.6 - 448.6 MHz
(25 kHz STEPS)
“1"
“1"
“0"
CHOICE OF
DETECTOR
ERROR
SIGNALS
OSCoutRA2
RA1
RA0
LD
fV
PDout
OSCin
VDD
VSS
LOOP
FILTER
φR
fV
VCO
X6
+ V
MC145151-2
REF. OSC.
10.0417 MHz
(ON-CHIP OSC.
OPTIONAL)
fin
T: 73.3333 - 78.3333 MHz
R: 69.7667 - 74.7667 MHz
T/R
T: 13.0833 - 18.0833 MHz
R: 9.5167 - 14.5167 MHz
DOWN
“0" “0"“1"
MIXER
CHANNEL PROGRAMMING
RECEIVE
÷ N = 2284 TO 3484
TRANSMIT
(ADDS 856 TO
÷ N VALUE)
X6
60.2500 MHz
NOTES:
1. fR = 4.1667 kHz; ÷ R = 2410; 21.4 MHz low side injection during receive.
2. Frequency values shown are for the 440 - 470 MHz band. Similar implementation applies to the 406 - 440 MHz band.
For 470 - 512 MHz, consider reference oscillator frequency X9 for mixer injection signal (90.3750 MHz).
Figure 4. Synthesizer for Land Mobile Radio UHF Bands
MC145151-2 and MC145152-2 Technical Data, Rev. 5
6
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
2 MC145152-2 Parallel-Input (Interfaces with
Dual-Modulus Prescalers)
The MC145152-2 is programmed by sixteen parallel inputs for the N and A counters and three input lines
for the R counter. The device features consist of a reference oscillator, selectable-reference divider,
two-output phase detector, 10-bit programmable divide-by-N counter, and 6-bit programmable
divide-by-A counter.
The MC145152-2 is an improved-performance drop-in replacement for the MC145152-1. Power
consumption has decreased and ESD and latch-up performance have improved.
2.1
Features
•
Operating Temperature Range: -40 to 85°C
Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
•
•
•
•
•
•
•
•
On- or Off-Chip Reference Oscillator Operation
Lock Detect Signal
Dual Modulus/Parallel Programming
8 User-Selectable ÷ R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048
÷ N Range = 3 to 1023, ÷ A Range = 0 to 63
Chip Complexity: 8000 FETs or 2000 Equivalent Gates
1 •
fin
28 LD
VSS
2
27 OSCin
VDD
3
26 OSCout
25 A4
24 A3
23 A0
22 A2
21 A1
20 N9
RA0 4
RA1 5
RA2 6
φR
φV
7
8
9
MC
A5 10
N0 11
N1 12
19 N8
18 N7
17 N6
N2 13
N3 14
16 N5
15 N4
Figure 5. MC145152-2 Pin Assignment
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
7
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
RA2
RA1
RA0
12 x 8 ROM REFERENCE DECODER
12
OSCout
OSCin
LOCK
DETECT
LD
12-BIT ÷ R COUNTER
MC
φV
φR
CONTROL
LOGIC
PHASE
DETECTOR
fin
6-BIT ÷ A COUNTER
10-BIT ÷ N COUNTER
A5
A3 A2
A0
N0
N2
N4 N5
N7
N9
NOTE: N0 - N9, A0 - A5, and RA0 - RA2 have pull-up resistors that are not shown.
Figure 6. MC145152-2 Block Diagram
2.2
Pin Descriptions
Input Pins
2.2.1
f
in
Frequency Input (Pin 1)
Input to the positive edge triggered ÷ N and ÷ A counters. f is typically derived from a dual-modulus
in
prescaler and is AC coupled into the device. For larger amplitude signals (standard CMOS logic levels)
DC coupling may be used.
RA0, RA1, RA2
Reference Address Inputs (Pins 4, 5, 6)
These three inputs establish a code defining one of eight possible divide values for the total reference
divider. The total reference divide values are as follows:
Reference Address Code
Total
Divide
Value
RA2
RA1
RA0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8
64
128
256
512
1024
1160
2048
MC145151-2 and MC145152-2 Technical Data, Rev. 5
8
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
N0 - N9
N Counter Programming Inputs (Pins 11 - 20)
The N inputs provide the data that is preset into the ÷ N counter when it reaches the count of 0. N0 is the
least significant digit and N9 is the most significant. Pull-up resistors ensure that inputs left open remain
at a logic 1 and require only a SPST switch to alter data to the zero state.
A0 - A5
A Counter Programming Inputs
(Pins 23, 21, 22, 24, 25, 10)
The A inputs define the number of clock cycles of f that require a logic 0 on the MC output (see
in
Section 4.3, “Dual-Modulus Prescaling,” on page 21). The A inputs all have internal pull-up resistors that
ensure that inputs left open will remain at a logic 1.
OSC , OSC
in
out
Reference Oscillator Input/Output (Pins 27, 26)
These pins form an on-chip reference oscillator when connected to terminals of an external parallel
resonant crystal. Frequency setting capacitors of appropriate value must be connected from OSC to
in
ground and OSC to ground. OSC may also serve as the input for an externally-generated reference
out
in
signal. This signal is typically ac coupled to OSC , but for larger amplitude signals (standard CMOS logic
in
levels) dc coupling may also be used. In the external reference mode, no connection is required to OSC .
out
2.2.2
Output Pins
φ , φ
R
V
Phase Detector B Outputs (Pins 7, 8)
These phase detector outputs can be combined externally for a loop-error signal.
If the frequency f is greater than f or if the phase of f is leading, then error information is provided by
V
R
V
φ pulsing low. φ remains essentially high.
V
R
If the frequency f is less than f or if the phase of f is lagging, then error information is provided by φ
R
V
R
V
pulsing low. φ remains essentially high.
V
If the frequency of f = f and both are in phase, then both φ and φ remain high except for a small
V
R
V
R
minimum time period when both pulse low in phase.
MC
Dual-Modulus Prescale Control Output (Pin 9)
Signal generated by the on-chip control logic circuitry for controlling an external dual-modulus prescaler.
The MC level will be low at the beginning of a count cycle and will remain low until the ÷ A counter has
counted down from its programmed value. At this time, MC goes high and remains high until the ÷ N
counter has counted the rest of the way down from its programmed value (N - A additional counts since
both ÷ N and ÷ A are counting down during the first portion of the cycle). MC is then set back low, the
counters preset to their respective programmed values, and the above sequence repeated. This provides for
a total programmable divide value (N )= N•P+A where P and P + 1 represent the dual-modulus prescaler
T
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
9
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
divide values respectively for high and low MC levels, N the number programmed into the ÷ N counter,
and A the number programmed into the ÷ A counter.
LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (f , f of same phase and frequency). Pulses low when loop
R
V
is out of lock.
2.2.3
Power Supply
V
DD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range from + 3 to + 9 V with respect to V .
SS
V
SS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually ground.
2.3
Typical Applications
NO CONNECTS
“1" “1" “1"
150 - 175 MHz
5 kHz STEPS
LOCK DETECT SIGNAL
R2
10.24 MHz
NOTE 1
C
OSCout
OSCin
RA2 RA1 RA0
LD
φR
R1
R1
-
+
VCO
φV
NOTE 2
MC145152-2
R2
C
MC
fin
VDD
VSS
+ V
N9
N0 A5
A0
CHANNEL PROGRAMMING
÷ 64/65 PRESCALER
NOTES:
1. Off-chip oscillator optional.
2. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop - Low-Pass Filter Design page
for additional information. The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the com-
mon mode input range of the op amp used in the combiner/loop filter.
Figure 7. Synthesizer for Land Mobile Radio VHF Bands
MC145151-2 and MC145152-2 Technical Data, Rev. 5
10
Freescale Semiconductor
MC145152-2 Parallel-Input (Interfaces with Dual-Modulus Prescalers)
RECEIVER 2ND L.O.
30.720 MHz
REF. OSC.
15.360 MHz
(ON-CHIP OSC.
OPTIONAL)
NO CONNECTS
“1" “1" “1"
RECEIVER FIRST L.O.
LOCK DETECT SIGNAL
X2
825.030 → 844.980 MHz
R2
C
(30 kHz STEPS)
OSCout
RA2 RA1 RA0
LD
R1
R1
φR
φV
-
OSCin
X4
NOTE 5
VCO
+
MC145152-2
NOTE 6
VDD
VSS
+ V
R2
MC
fin
C
X4
NOTE 5
TRANSMITTER
MODULATION
N9
N0A5
A0
÷ 64/65 PRESCALER
TRANSMITTER SIGNAL
825.030 → 844.980 MHz
(30 kHz STEPS)
NOTE 5
CHANNEL PROGRAMMING
NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receiver/transmit separation.
3. fR = 7.5 kHz; ÷ R = 2048.
4. Ntotal = N • 64 + A = 27501 to 28166; N = 429 to 440; A = 0 to 63.
5. High frequency prescalers may be used for higher frequency VCO and fref
implementations.
6. The φR and φV outputs are fed to an external combiner/loop filter. See the Phase-Locked Loop - Low-Pass Filter Design page for
additional information. The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode
input range of the op amp used in the combiner/loop filter.
Figure 8. 666-Channel Computer-Controlled, Mobile Radiotelephone Synthesizer
for 800 MHz Cellular Radio Systems
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
11
MC145151-2 and MC145152-2 Electrical Characteristics
3 MC145151-2 and MC145152-2 Electrical Characteristics
These devices contain protection circuitry to protect against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum
rated voltages to these high-impedance circuits. For proper operation, V and V should be constrained
in
out
to the range V ≤ (V or V ) ≤ V except for SW1 and SW2.
SS
in
out
DD
SW1 and SW2 can be tied through external resistors to voltages as high as 15 V, independent of the supply
voltage.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V or V ), except
SS
DD
for inputs with pull-up devices. Unused outputs must be left open.
1
Table 1. Maximum Ratings
(Voltages Referenced to VSS)
Ratings
Symbol
Value
Unit
DC Supply Voltage
VDD
Vin, Vout
Vout
- 0.5 to + 10.0
- 0.5 to VDD + 0.5
- 0.5 to + 15
V
V
V
Input or Output Voltage (DC or Transient) except SW1, SW2
Output Voltage (DC or Transient),
SW1, SW2 (Rpull-up = 4.7 kΩ)
Input or Output Current (DC or Transient), per Pin
Supply Current, VDD or VSS Pins
Iin, Iout
IDD, ISS
PD
± 10
± 30
mA
mA
mW
°C
Power Dissipation, per Package†
500
Storage Temperature
Tstg
-65 to + 150
260
Lead Temperature, 1 mm from Case for 10 seconds
TL
°C
1
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be
restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
† Power Dissipation Temperature Derating:
Plastic DIP: - 12 mW/°C from 65 to 85°C
SOG Package: - 7 mW/°C from 65 to 85°C
MC145151-2 and MC145152-2 Technical Data, Rev. 5
12
Freescale Semiconductor
MC145151-2 and MC145152-2 Electrical Characteristics
Table 2. Electrical Characteristics
(Voltages Referenced to V
)
SS
- 40°C
25°C
85°C
VDD
Symbol
Parameter
Test Condition
V
Unit
Min Max Min Max Min Max
VDD
Power Supply Voltage
Range
-
3
9
3
9
3
9
V
Iss
Dynamic Supply
Current
fin = OSCin = 10 MHz,
1 V p-p ac coupled sine wave
R = 128, A = 32, N = 128
3
5
9
-
-
-
3.5
10
30
-
-
-
3
7.5
24
-
-
-
3
7.5
24
mA
ISS
Quiescent Supply
Current (not including Iout = 0 µA
pull-up current
Vin = VDD or VSS
3
5
9
-
-
-
800
1200
1600
-
-
-
800
1200
1600
-
-
-
1600
2400
3200
µA
component)
Vin
VIL
Input Voltage - fin,
OSCin
Input ac coupled sine wave
-
500
-
500
-
500
-
mV p-p
V
Low-Level Input
Voltage - fin, OSCin
Vout ≥ 2.1 V
Vout ≥ 3.5 V
Vout ≥ 6.3 V
Input dc
coupled
square wave
3
5
9
-
-
-
0
0
0
-
-
-
0
0
0
-
-
-
0
0
0
VIH
VIL
VIH
High-Level Input
Voltage - fin, OSCin
Vout ≤ 0.9 V
Vout ≤ 1.5 V
Vout ≤ 2.7 V
Input dc
coupled
square wave
3
5
9
3.0
5.0
9.0
-
-
-
3.0
5.0
9.0
-
-
-
3.0
5.0
9.0
-
-
-
V
V
V
Low-Level Input
Voltage - except fin,
OSCin
3
5
9
-
-
-
0.9
1.5
2.7
-
-
-
0.9
1.5
2.7
-
-
-
0.9
1.5
2.7
High-Level Input
Voltage - except fin,
OSCin
3
5
9
2.1
3.5
6.3
-
-
-
2.1
3.5
6.3
-
-
-
2.1
3.5
6.3
-
-
-
Iin
Input Current
(fin, OSCin)
Vin = VDD or VSS
9
± 2
± 50
± 2
± 25
± 2
± 22
µA
µA
IIL
Input Leakage
Current (Data, CLK,
ENB - without
pull-ups)
Vin = VSS
9
-
- 0.3
-
- 0.1
-
- 1.0
IIH
Input Leakage
Vin = VDD
9
-
0.3
-
0.1
-
1.0
µA
Current (all inputs
except fin, OSCin)
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
13
MC145151-2 and MC145152-2 Electrical Characteristics
Table 3. DC Electrical Characteristics
- 40°C
25°C
85°C
VDD
V
Symbol
Parameter
Test Condition
Unit
Min
Max
Min
Max
Min
Max
IIL
Pull-up Current (all inputs Vin = VSS
with pull-ups)
9
- 20
- 400
- 20
- 200
- 20
- 170
µA
Cin
Input Capacitance
-
-
10
-
10
-
10
pF
V
VOL
Low-Level Output
Voltage - OSCout
Iout ≈ 0 µA
Vin = VDD
3
5
9
-
-
-
0.9
1.5
2.7
-
-
-
0.9
1.5
2.7
-
-
-
0.9
1.5
2.7
VOH
VOL
VOH
High-Level Output
Voltage - OSCout
Iout ≈ 0 µA
3
5
9
2.1
3.5
6.3
-
-
-
2.1
3.5
6.3
-
-
-
2.1
3.5
6.3
-
-
-
V
Vin = VSS
Low-Level Output
Voltage - Other Outputs
Iout ≈ 0 µA
3
5
9
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
-
-
-
0.05
0.05
0.05
V
High-Level Output
Voltage - Other Outputs
Iout ≈ 0 µA
3
5
9
2.95
4.95
8.95
-
-
-
2.95
4.95
8.95
-
-
-
2.95
4.95
8.95
-
-
-
V
V(BR)DSS Drain-to-Source
Breakdown Voltage -
SW1, SW2
Rpull-up = 4.7 kΩ
-
15
-
15
-
15
-
V
IOL
IOH
IOL
IOH
IOL
IOL
IOH
Low-Level Sinking
Current - MC
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
1.30
1.90
3.80
-
-
-
1.10
1.70
3.30
-
-
-
0.66
1.08
2.10
-
-
-
mA
mA
mA
mA
mA
mA
mA
High-Level Sourcing
Current - MC
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
- 0.60
- 0.90
- 1.50
-
-
-
- 0.50
- 0.75
- 1.25
-
-
-
- 0.30
- 0.50
- 0.80
-
-
-
Low-Level Sinking
Current - LD
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.25
0.64
1.30
-
-
-
0.20
0.51
1.00
-
-
-
0.15
0.36
0.70
-
-
-
High-Level Sourcing
Current - LD
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
- 0.25
- 0.64
- 1.30
-
-
-
- 0.20
- 0.51
- 1.00
-
-
-
- 0.15
- 0.36
- 0.70
-
-
-
Low-Level Sinking
Current - SW1, SW2
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.80
1.50
3.50
-
-
-
0.48
0.90
2.10
-
-
-
0.24
0.45
1.05
-
-
-
Low-Level Sinking
Current - Other Outputs
Vout = 0.3 V
Vout = 0.4 V
Vout = 0.5 V
3
5
9
0.44
0.64
1.30
-
-
-
0.35
0.51
1.00
-
-
-
0.22
0.36
0.70
-
-
-
High-Level Sourcing
Current - Other Outputs
Vout = 2.7 V
Vout = 4.6 V
Vout = 8.5 V
3
5
9
- 0.44
- 0.64
- 1.30
-
-
-
- 0.35
- 0.51
- 1.00
-
-
-
- 0.22
- 0.36
- 0.70
-
-
-
IOZ
IOZ
Output Leakage Current - Vout = VDD or VSS
PDout Output in Off State
9
9
-
-
-
-
± 0.3
± 0.3
10
-
-
-
± 0.1
± 0.1
10
-
-
-
± 1.0
± 3.0
10
µA
µA
pF
Output Leakage Current - Vout = VDD or VSS
SW1, SW2
Output in Off State
Cout
Output Capacitance -
PDout
PDout - Three-State
MC145151-2 and MC145152-2 Technical Data, Rev. 5
14
Freescale Semiconductor
MC145151-2 and MC145152-2 Electrical Characteristics
Table 4. AC Electrical Characteristics
(C = 50 pF, Input t = t = 10 ns)
L
r
f
VDD Guaranteed Limit Guaranteed Limit
Symbol
Parameter
Unit
V
25°C
-40 to 85°C
tPLH, tPHL Maximum Propagation Delay, fin to MC
(Figure 9a and Figure 9d)
3
5
9
110
60
35
120
70
40
ns
tPHL
Maximum Propagation Delay, ENB to SW1, SW2
(Figure 9a and Figure 9e)
3
5
9
160
80
50
180
95
60
ns
ns
ns
ns
ns
ns
tw
Output Pulse Width, φR, φV, and LD with fR in Phase with fV
(Figure 9b and Figure 9d)
3
5
9
25 to 200
20 to 100
10 to 70
25 to 260
20 to 125
10 to 80
tTLH
Maximum Output Transition Time, MC
(Figure 9c and Figure 9d)
3
5
9
115
60
40
115
75
60
tTHL
Maximum Output Transition Time, MC
(Figure 9c and Figure 9d)
3
5
9
60
34
30
70
45
38
tTLH, tTHL Maximum Output Transition Time, LD
(Figure 9c and Figure 9d)
3
5
9
180
90
70
200
120
90
tTLH, tTHL Maximum Output Transition Time, Other Outputs
(Figure 9c and Figure 9d)
3
5
9
160
80
60
175
100
65
VDD
50%
tPLH
INPUT
- VSS
tw
tPHL
φR, φV, LD*
50%
50%
*fR in phase with fV.
OUTPUT
Figure 9a. Maximum Propagation Delay
Figure 9b. Output Pulse Width
tTLH
tTHL
ANY
OUTPUT
90%
10%
Figure 9c. Maximum Output Transition Time
TEST
POINT
TEST
POINT
VDD
15 kΩ
OUTPUT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
CL*
*Includes all probe and fixture capacitance.
*Includes all probe and fixture capacitance.
Figure 9d. Test Circuit
Figure 9e. Test Circuit
Figure 9. Switching Waveforms
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
15
MC145151-2 and MC145152-2 Electrical Characteristics
Table 5. Timing Requirements
(Input t = t = 10 ns unless otherwise indicated)
r
f
VDD Guaranteed Limit Guaranteed Limit
Symbol
Parameter
Unit
V
25°C
- 40 to 85°C
fclk
Serial Data Clock Frequency, Assuming 25% Duty Cycle
NOTE: Refer to CLK tw(H) below
(Figure 10a)
3
5
9
dc to 5.0
dc to 7.1
dc to 10
dc to 3.5
dc to 7.1
dc to 10
MHz
tsu
Minimum Setup Time, Data to CLK
(Figure 10b)
3
5
9
30
20
18
30
20
18
ns
ns
ns
ns
ns
µs
th
Minimum Hold Time, CLK to Data
(Figure 10b)
3
5
9
40
20
15
40
20
15
tsu
Minimum Setup Time, CLK to ENB
(Figure 10b)
3
5
9
70
32
25
70
32
25
trec
tw(H)
tr, tf
Minimum Recovery Time, ENB to CLK
(Figure 10b)
3
5
9
5
10
20
5
10
20
Minimum Pulse Width, CLK and ENB
(Figure 10a)
3
5
9
50
35
25
70
35
25
Maximum Input Rise and Fall Times - Any Input
(Figure 10c)
3
5
9
5
4
2
5
4
2
tw(H)
- VDD
VSS
50%
DATA
tsu
- VDD
VSS
CLK,
ENB
50%
th
*
1
- VDD
VSS
4 fclk
LAST
CLK
FIRST
CLK
50%
CLK
ENB
*Assumes 25% Duty Cycle.
tsu
trec
- VDD
VSS
Figure 10a. Serial Data Clock
Frequency and Minimum Pulse Width
50%
PREVIOUS
DATA
LATCHED
tt
tf
ANY
OUTPUT
- VDD
VSS
90%
10%
Figure 10b. Minimum Setup, Hold,
and Recovery Times
Figure 10c. Maximum Input Rise and Fall Times
Figure 10. Switching Waveforms
MC145151-2 and MC145152-2 Technical Data, Rev. 5
16
Freescale Semiconductor
MC145151-2 and MC145152-2 Electrical Characteristics
Table 6. Frequency Characteristics
(Voltages References to V , C = 50 pF, Input t = t =10 ns unless otherwise indicated)
SS
L
r
f
- 40°C
25°C
85°C
VDD
Symbol
Parameter
Test Condition
Unit
V
Min
Max
Min
Max
Min
Max
fi
Input Frequency R ≥ 8, A ≥ 0, N ≥ 8
(fin, OSCin) Vin = 500 mV p-p ac coupled
3
5
9
-
-
-
6
15
15
-
-
-
6
15
15
-
-
-
6
15
15
MHz
sine wave
R ≥ 8, A ≥ 0, N ≥ 8
Vin = 1 V p-p ac coupled
sine wave
3
5
9
-
-
-
12
22
25
-
-
-
12
20
22
-
-
-
7
20
22
MHz
MHz
R ≥ 8, A ≥ 0, N ≥ 8
Vin = VDD to VSS dc coupled
square wave
3
5
9
-
-
-
13
25
25
-
-
-
12
22
25
-
-
-
8
22
25
Note: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency
limit of the system. The upper frequency limit is found with the following formula: f = P/(tP + tset) where f is the upper frequency
in Hz, P is the lower of the dual modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler
setup time in seconds. For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup
time is 16 ns. Thus, if the 64/65 ratio is utilized, the upper frequency limit is f = P/(tP + tset) = 64/(70 + 16) = 744 MHz.
fR
VH
REFERENCE
OSC ÷ R
VL
VH
fV
FEEDBACK
VL
(fin ÷ N)
VH
*
HIGH IMPEDANCE
PDout
VL
VH
φR
φV
VL
VH
VL
VH
LD
VL
VH=High Voltage Level.
VL=Low Voltage Level.
*At this point, when both fR and fV are in phase, the output is forced to near mid-supply.
NOTE: The PDout generates error pulses during out-of-lock conditions. When locked in phase and frequency the output is high
and the voltage at this pin is determined by the low-pass filter capacitor.
Figure 11. Phase Detector/Lock Detector Output Waveforms
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
17
Design Considerations
4 Design Considerations
4.1
Phase-Locked Loop — Low-Pass Filter Design
KφKVCO
NR1C
A)
PDout
VCO
ωn =
ζ =
R1
φR
φV
-
-
C
Nωn
2KφKVCO
1
F(s) =
R1sC + 1
PDout
B)
VCO
KφKVCO
NC(R1 + R2)
R1
ωn =
φR
φV
-
R2
C
N
-
ζ = 0.5 ωn R2C+
)
(
KφKVCO
R2sC+1
F(s) =
(R1+R2)sC+1
R2
KφKVCO
NCR1
PDout
-
C)
ωn =
ζ =
C
R1
_
φR
φV
ωnR2C
A
VCO
+
2
R1
Assuming gain A is very large, then:
R2
C
R2sC + 1
F(s) =
R1sC
NOTE: Sometimes R1 is split into two series resistors, each R1 ÷ 2. A capacitor CC is then placed from the midpoint to ground to further
filter φV and φR. The value of CC should be such that the corner frequency of this network does not significantly affect ωn.
The φR and φV outputs swing rail-to-rail. Therefore, the user should be careful not to exceed the common mode input range of the
op amp used in the combiner/loop filter.
Definitions:
N = Total Division Ratio in feedback loop
Kφ (Phase Detector Gain) = VDD/4π for PDout
Kφ (Phase Detector Gain) = VDD/2π for φV and φR
2π∆fVCO
KVCO (VCO Gain) =
∆VVCO
2πfr
10
for a typical design wn (Natural Frequency) ≈
Damping Factor: ζ ≅ 1
(at phase detector input).
Figure 12. Phase-Locked Loop — Low-Pass Filter Design
MC145151-2 and MC145152-2 Technical Data, Rev. 5
18
Freescale Semiconductor
Design Considerations
4.2
Crystal Oscillator Considerations
The following options may be considered to provide a reference frequency to Freescale's CMOS frequency
synthesizers.
4.2.1
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal oscillators (TCXOs) or crystal-controlled data
clock oscillators provide very stable reference frequencies. An oscillator capable of sinking and sourcing
50 µA at CMOS logic levels may be direct or dc coupled to OSC . In general, the highest frequency
in
capability is obtained utilizing a direct-coupled square wave having a rail-to-rail (V to V ) voltage
DD
SS
swing. If the oscillator does not have CMOS logic levels on the outputs, capacitive or ac coupling to OSC
in
may be used. OSC , an unbuffered output, should be left floating.
out
4.2.2
Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using ICs specifically developed for crystal oscillator
applications, or using discrete transistors. The reference signal from the oscillator is ac coupled to OSC .
in
For large amplitude signals (standard CMOS logic levels), dc coupling is used. OSC , an unbuffered
out
output, should be left floating. In general, the highest frequency capability is obtained with a
direct-coupled square wave having rail-to-rail voltage swing.
4.2.3
Use of the On-Chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a
reference source frequency. A fundamental mode crystal, parallel resonant at the desired operating
frequency, should be connected as shown in Figure 13.
FREQUENCY
SYNTHESIZER
Rf
OSCin
C1
OSCout
R1*
C2
*
May be deleted in certain cases. See text.
Figure 13. Pierce Crystal Oscillator Circuit
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
19
Design Considerations
For V = 5.0 V, the crystal should be specified for a loading capacitance, C , which does not exceed
DD
L
32 pF for frequencies to approximately 8.0 MHz, 20 pF for frequencies in the area of 8.0 to 15 MHz, and
10 pF for higher frequencies. These are guidelines that provide a reasonable compromise between IC
capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
C values. The shunt load capacitance, C , presented across the crystal can be estimated to be:
L
L
CinCout
C1•C2
C1+C2
CL =
+ Ca + Co +
Cin + Cout
where
C
C
C
C
= 5 pF (see Figure 14)
= 6 pF (see Figure 14)
= 1 pF (see Figure 14)
in
out
a
= the crystal's holder capacitance (see Figure 15)
O
C1 and C2= external capacitors (see Figure 13)
Ca
Cin
Cout
Figure 14. Parasitic Capacitances of the Amplifier
RS
LS
CS
1
2
1
2
CO
Xe
2
Re
1
NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 15. Equivalent Crystal Networks
The oscillator can be “trimmed” on-frequency by making a portion or all of C1 variable. The crystal and
associated components must be located as close as possible to the OSC and OSC pins to minimize
in
out
distortion, stray capacitance, stray inductance, and startup stabilization time. In some cases, stray
capacitance should be added to the value for C and C .
in
out
Power is dissipated in the effective series resistance of the crystal, R , in Figure 15. The drive level
e
specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage
or excessive shift in frequency. R1 in Figure 13 limits the drive level. The use of R1 may not be necessary
in some cases (i.e., R1 = 0 Ω).
MC145151-2 and MC145152-2 Technical Data, Rev. 5
20
Freescale Semiconductor
Design Considerations
To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency
as a function of voltage at OSC . (Care should be taken to minimize loading.) The frequency should
out
increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply voltage. The operating supply voltage must be
reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with crystals. Discussions with such manufacturers can
prove very helpful.
4.3
Dual-Modulus Prescaling
Overview
4.3.1
The technique of dual-modulus prescaling is well established as a method of achieving high performance
frequency synthesizer operation at high frequencies. Basically, the approach allows relatively
low-frequency programmable counters to be used as high-frequency programmable counters with speed
capability of several hundred MHz. This is possible without the sacrifice in system resolution and
performance that results if a fixed (single-modulus) divider is used for the prescaler.
In dual-modulus prescaling, the lower speed counters must be uniquely configured. Special control logic
is necessary to select the divide value P or P + 1 in the prescaler for the required amount of time (see
modulus control definition).
4.3.2
Design Guidelines
The system total divide value, N
(N ) will be dictated by the application:
total
T
frequency into the prescaler
NT=
= N • P + A
frequency into the phase detector
N is the number programmed into the ÷ N counter, A is the number programmed into the ÷ A counter, P
and P + 1 are the two selectable divide ratios available in the dual-modulus prescalers. To have a range of
N values in sequence, the ÷ A counter is programmed from zero through P - 1 for a particular value N in
T
the ÷ N counter. N is then incremented to N + 1 and the ÷ A is sequenced from 0 through P - 1 again.
There are minimum and maximum values that can be achieved for N . These values are a function of P
T
and the size of the ÷ N and ÷ A counters.
The constraint N ≥ A always applies. If A
= P - 1, then N ≥ P - 1. Then N
= (P - 1) P + A or
Tmin
max
min
(P - 1) P since A is free to assume the value of 0.
N
= N
• P + A
max max
Tmax
To maximize system frequency capability, the dual-modulus prescaler output must go from low to high
after each group of P or P + 1 input cycles. The prescaler should divide by P when its modulus control line
is high and by P + 1 when its MC is low.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
21
Design Considerations
For the maximum frequency into the prescaler (f
that:
), the value used for P must be large enough such
VCOmax
1. f
divided by P may not exceed the frequency capability of f (input to the ÷ N and ÷ A
in
VCOmax
counters).
2. The period of f
divided by P must be greater than the sum of the times:
VCO
a) Propagation delay through the dual-modulus prescaler.
b) Prescaler setup or release time relative to its MC signal.
c) Propagation time from f to the MC output for the frequency synthesizer device.
in
A sometimes useful simplification in the programming code can be achieved by choosing the values for P
of 8, 16, 32, or 64. For these cases, the desired value of N results when N in binary is used as the program
T
T
code to the ÷ N and ÷ A counters treated in the following manner:
a
1. Assume the ÷ A counter contains “a” bits where 2 ≥ P.
2. Always program all higher order ÷ A counter bits above “a” to 0.
3. Assume the ÷ N counter and the ÷ A counter (with all the higher order bits above “a” ignored)
combined into a single binary counter of n + a bits in length (n = number of divider stages in the
÷ N counter). The MSB of this “hypothetical” counter is to correspond to the MSB of ÷ N and the
LSB is to correspond to the LSB of ÷ A. The system divide value, N , now results when the value
T
of N in binary is used to program the “new” n + a bit counter.
T
By using the two devices, several dual-modulus values are achievable.
MC145151-2 and MC145152-2 Technical Data, Rev. 5
22
Freescale Semiconductor
Package Dimensions
5 Package Dimensions
P SUFFIX
PLASTIC DIP
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. CONTROLLING DIMENSION: INCH.
28
15
14
B
INCHES
DIM MIN MAX
MILLIMETERS
MIN
36.45
13.72
3.94
MAX
37.21
14.22
5.08
1
A
B
C
D
F
1.435
0.540
0.155
0.014
0.040
1.465
0.560
0.200
0.022
0.060
L
A
C
N
0.36
1.02
0.56
1.52
G
H
J
K
L
0.100 BSC
2.54 BSC
0.065
0.008
0.115
0.085
0.015
0.135
1.65
0.20
2.92
2.16
0.38
3.43
J
H
F
M
K
0.600 BSC
15.24 BSC
D
G
SEATING
PLANE
M
N
0˚
0.020
15˚
0.040
0˚
0.51
15˚
1.02
Figure 16. Outline Dimensions for Plastic DIP
(Case Outline 710-02, Issue B)
DW SUFFIX
SOG PACKAGE
D
NOTES:
A
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
28
15
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
14
MILLIMETERS
B
PIN 1 IDENT
DIM MIN
MAX
2.65
0.29
0.49
0.32
18.05
7.60
A
A1
B
C
D
E
2.35
0.13
0.35
0.23
17.80
7.40
L
0.10
e
1.27 BSC
H
L
θ
10.05
0.41
0˚
10.55
0.90
8˚
e
C
SEATING
PLANE
B
C
θ
M
S
S
B
0.025
C A
Figure 17. Outline Dimensions for SOG Package
(Case Outline 751F-05, Issue F)
MC145151-2 and MC145152-2 Technical Data, Rev. 5
Freescale Semiconductor
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MC145151-2/D
Rev. 5
12/2004
/
相关型号：
MC145151P2
Parallel-Input PLL Frequency Synthesizer Interfaces with Single-Modulus Prescalers
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