MC33596_10_技术文档

MC33596

Rev. 5, 02/2010

Freescale Semiconductor

Data Sheet

MC33596

PLL Tuned UHF Receiver for Data Transfer Applications

1 Overview

The MC33596 is a highly integrated receiver

designed for low-voltage applications. It includes a

programmable PLL for multi-channel applications,

an RSSI circuit, a strobe oscillator that periodically

wakes up the receiver while a data manager checks

the content of incoming messages. A configuration

switching feature allows automatic changing of the

configuration between two programmable settings

without the need of an MCU.

LQFP32

QFN32

2 Features

24

23

22

21

20

19

18

17

RSSIOUT

VCC2RF

RFIN

1

2

3

4

5

6

7

8

SEB

General:

SCLK

•

304 MHz, 315 MHz, 426 MHz, 434 MHz,

868 MHz, and 915 MHz ISM bands

MOSI

GNDLNA

VCC2VCO

MISO

•

Choice of temperature ranges:

— –40°C to +85°C

CONFB

DATACLK

RSSIC

GNDDIG

GND

NC

— –20°C to +85°C

•

OOK and FSK reception

GND

20 kbps maximum data rate using

Manchester coding

•

2.1 V to 3.6 V or 5 V supply voltage

Programmable via SPI

6 kHz PLL frequency step

Features

•

Frequency hopping capability with PLL toggle time below 30 µs

Current consumption:

— 10.3 mA in RX mode

— Less then 1 mA in RX mode with strobe ratio = 1/10

— 260 nA standby and 24 μA off currents

Configuration switching — allows fast switching of two register banks

•

Receiver:

•

–106.5 dBm sensitivity, up to –108 dBm in FSK 2.4 kbps

Digital and analog RSSI (received signal strength indicator)

Automatic wakeup function (strobe oscillator)

Embedded data processor with programmable word recognition

Image cancelling mixer

380 kHz IF filter bandwidth

Fast wakeup time

Ordering information

Temperature Range

QFN Package

LQFP Package

–40°C to +85°C

–20°C to +85°C

MC33596FCE/R2

MC33596FCAE/R2

MC33596FJE/R2

MC33596FJAE/R2

MC33596 Data Sheet, Rev. 4

2

Freescale Semiconductor

Features

D N B A

Figure 1. Block Diagram

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

3

Pin Functions

3 Pin Functions

Table 1. Pin Functions

Name

Description

1

RSSIOUT

VCC2RF

RFIN

RSSI analog output

2

2.1 V to 2.7 V internal supply for LNA

RF input

3

4

GNDLNA

VCC2VCO

GND

Ground for LNA (low noise amplifier)

5

2.1 V to 2.7 V internal supply for VCO

Ground

6

7

NC

Not connected

8

GND

Ground

9

XTALIN

XTALOUT

VCCINOUT

VCC2OUT

VCCDIG

VCCDIG2

RBGAP

GND

Crystal oscillator input

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Crystal oscillator output

2.1 V to 3.6 V power supply/regulator output

2.1 V to 2.7 V voltage regulator output for analog and RF modules

2.1 V to 3.6 V power supply for voltage limiter

1.5 V voltage limiter output for digital module

Reference voltage load resistance

General ground

GNDDIG

RSSIC

Digital module ground

RSSI control input

DATACLK

CONFB

MISO

Data clock output to microcontroller

Configuration mode selection input

Digital interface I/O

MOSI

Digital interface I/O

SCLK

Digital interface clock I/O

SEB

Digital interface enable input

Digital I/O ground

GNDIO

VCCIN

NC

2.1 V to 3.6 V or 5.5 V input

No connection

STROBE

GNDSUBD

VCC2IN

SWITCH

GND

Strobe oscillator capacitor or external control input

Ground

2.1 V to 2.7 V power supply for analog modules for decoupling capacitor

RF switch control output

General ground

MC33596 Data Sheet, Rev. 4

4

Freescale Semiconductor

Maximum Ratings

4 Maximum Ratings

Table 2. Maximum Ratings

Parameter

Symbol

Value

Unit

Supply voltage on pin: VCCIN

V_CCIN

V_CC

V_GND–0.3 to 5.5

V_GND–0.3 to 3.6

V_GND–0.3 to 2.7

V

Supply voltage on pins: VCCINOUT, VCCDIG

Supply voltage on pins: VCC2IN, VCC2RF, VCC2VCO

Voltage allowed on each pin (except digital pins)

V_CC2

—

V_GND–0.3 to V_CC2

Voltage allowed on digital pins: SEB, SCLK, MISO, MOSI, CONFB,

DATACLK, RSSIC, STROBE

V_CCIO

V_GND–0.3 to V_CC+0.3

ESD HBM voltage capability on each pin¹

ESD MM voltage capability on each pin²

Solder heat resistance test (10 s)

Storage temperature

—

T_S

T_J

±2000

±200

V

260

°C

–65 to +150

150

Junction temperature

N₁OTES:

Human body model, AEC-Q100-002 rev. C.

Machine model, AEC-Q100-003 rev. C.

2

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

5

Power Supply

5 Power Supply

Table 3. Supply Voltage Range Versus Ambient Temperature

Temperature Range¹

Parameter

Symbol

Unit

–40°C to +85°C

–20°C to +85°C

Supply voltage on VCCIN, VCCINOUT, VCCDIG for 3 V operation

Supply voltage on VCCIN for 5 V operation

V_CC3V

V_CC5V

2.7 to 3.6

4.5 to 5.5

2.1 to 3.6

4.5 to 5.5

V

N₁OTES:

–40°C to +85°C: MC33596FCE/FJE.

–20°C to +85°C: MC33596FCAE/FJAE.

The circuit can be supplied from a 3 V voltage regulator or battery cell by connecting VCCIN,

VCCINOUT, and VCCDIG (See Figure 43 or Figure 44). It is also possible to use a 5 V power supply

connected to VCCIN; in this case VCCINOUT and VCCDIG should not be connected to VCCIN (See

Figure 41 or Figure 42).

An on-chip low drop-out voltage regulator supplies the RF and analog modules (except the strobe

oscillator and the low voltage detector, which are directly supplied from VCCINOUT). This voltage

regulator is supplied from pin VCCINOUT and its output is connected to VCC2OUT. An external

capacitor (C8 = 100 nF) must be inserted between VCC2OUT and GND for stabilization and decoupling.

The analog and RF modules must be supplied by VCC2 by externally wiring VCC2OUT to VCC2IN,

VCC2RF, and VCC2VCO.

A second voltage regulator supplies the digital part. This regulator is powered from pin VCCDIG and its

output is connected to VCCDIG2. An external capacitor (C10 = 100 nF) must be inserted between

VCCDIG2 and GNDDIG, for decoupling. The supply voltage VCCDIG2 is equal to 1.6 V. In standby

mode, this voltage regulator goes into an ultra-low-power mode, but VCCDIG2 = 0.7 × V

CCDIG.

This enables the internal registers to be supplied, allowing configuration data to be saved.

6 Supply Voltage Monitoring and Reset

At power-on, an internal reset signal (Power-on Reset, POR) is generated when supply voltage is around

1.3 V. All registers are reset.

When the LVDE bit is set, the low-voltage detection module is enabled. This block compares the supply

voltage on VCCINOUT with a reference level of about 1.8 V. If the voltage on VCCINOUT drops below

1.8 V, status bit LVDS is set. The information in status bit LVDS is latched and reset after a read access.

NOTE

If LVDE = 1, the LVD module remains enabled. The circuit cannot be put

in standby mode, but remains in LVD mode with a higher quiescent current,

due to the monitoring circuitry. LVD function is not accurate in standby

mode.

MC33596 Data Sheet, Rev. 4

6

Freescale Semiconductor

Receiver Functional Description

7 Receiver Functional Description

The receiver is based on a superheterodyne architecture with an intermediate frequency IF (see Figure 1).

Its input is connected to the RFIN pin. Frequency down conversion is done by a high-side injection I/Q

mixer driven by the frequency synthesizer. An integrated poly-phase filter performs rejection of the image

frequency.

The low intermediate frequency allows integration of the IF filter providing the selectivity. The IF Filter

center frequency is tuned by automatic frequency control (AFC) referenced to the crystal oscillator

frequency.

Sensitivity is met by an overall amplification of approximately 96 dB, distributed over the reception chain,

comprising low-noise amplifier (LNA), mixer, post-mixer amplifier, and IF amplifier. Automatic gain

control (AGC), on the LNA and the IF amplifier, maintains linearity and prevents internal saturation.

Sensitivity can be reduced using four programmable steps on the LNA gain.

Amplitude demodulation is achieved by peak detection. Frequency demodulation is achieved in two steps:

the IF amplifier AGC is disabled and acts as an amplitude limiter; a filter performs a frequency-to-voltage

conversion. The resulting signal is then amplitude demodulated in the same way as in the case of amplitude

modulation with an adaptive voltage reference.

A low-pass filter improves the signal-to-noise ratio of demodulated data. A data slicer compares

demodulated data with a fixed or adaptive voltage reference and provides digital level data.

This digital data is available if the integrated data manager is not used.

If used, the data manager performs clock recovery and decoding of Manchester coded data. Data and clock

are then available on the serial peripheral interface (SPI). The configuration sets the data rate range

managed by the data manager and the bandwidth of the low-pass filter.

An internal low-frequency oscillator can be used as a strobe oscillator to perform an automatic wakeup

sequence.

It is also possible to define two different configurations for the receiver (frequency, data rate, data manager,

modulation, etc.) that are automatically loaded during wakeup or under MCU control.

If the PLL goes out of lock, received data is ignored.

8 Frequency Planning

8.1 Clock Generator

All clocks running in the circuit are derived from the reference frequency provided by the crystal oscillator

(frequency f , period t ). The crystal frequency is chosen in relation to the band in which the MC33596

ref

has to operate. Table 4 shows the value of the CF bits.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

7

Frequency Planning

RF

Table 4. Crystal Frequency and CF Values Versus Frequency Band

F_REF(Crystal

Frequency)

(MHz)

F_IF(IF

Frequency)

(MHz)

Dataclk F_dataclk

Digclk

Divider

F_digclk

(kHz)

T_digclk

(µs)

Frequency

(MHz)

CF1

CF0

LOF1

LOF0

Divider

(kHz)

304

315

0

1

0

1

0

1

0

1

0

1

16.96745

17.58140

23.74913

24.19066

24.16139

25.50261

1.414

1.465

1.484

1.512

1.510

1.594

60

80

282.791

293.023

296.864

302.383

302.017

318.783

30

40

565.582

586.047

593.728

604.767

604.035

637.565

1.77

1.71

1.68

1.65

1.66

1.57

426

433.92

868.3

916.5

8.2 Intermediate Frequency

The IF filter is controlled by the crystal oscillator to guarantee the frequency over temperature and voltage

range. The IF filter center frequency, FIF, can be computed using the crystal frequency f and the value

ref

of the CF bits:

•

If CF[0] = 0 : FIF = f /9×1.5/2

ref

If CF[0] = 1 : FIF = f /12×1.5/2

ref

The cut-off frequency given in the parametric section can be computed by scaling to the FIF.

Example 1. Cut-off Frequency Computation

Compute the low cut-off frequency of the IF filter for a 16.9683 MHz crystal oscillator. For this

reference frequency, FIF = 1.414 MHz.

1

So, the 1.387 MHz low cut-off frequency specified for a 1.5 MHz IF frequency becomes

1.387 × 1.414/1.5 = 1.307 MHz.

8.3 Frequency Synthesizer Description

The frequency synthesizer consists of a local oscillator (LO) driven by a fractional N phase locked loop

(PLL).

The LO is an integrated LC voltage controlled oscillator (VCO) operating at twice the RF frequency (for

the 868 MHz frequency band) or four times the RF frequency (for the 434 MHz and 315 MHz frequency

bands). This allows the I/Q signals driving the mixer to be generated by division.

The fractional divider offers high flexibility in the frequency generation for:

•

Performing multi-channel links.

Trimming the RF carrier.

Frequencies are controlled by means of registers. To allow for user preference, two programming access

methods are offered (see Section 16.3, “Frequency Register”).

•

In friendly access, all frequencies are computed internally from the contents of the carrier

frequency and deviation frequency registers.

1. Refer to parameter 3.3 found in Section 19.3, “Receiver Parameters.”

MC33596 Data Sheet, Rev. 4

8

Freescale Semiconductor

MCU Interface

•

In direct access, the user programs direct all three frequency registers.

9 MCU Interface

The MC33596 and the MCU communicate via a serial peripheral interface (SPI). According to the selected

mode, the MC33596 or the MCU manages the data transfer. The MC33596’s digital interface can be used

as a standard SPI (master/slave) or as a simple interface (SPI deselected). In the following case, the

interface’s pins are used as standard I/O pins. However, the MCU has the highest priority, as it can control

the MC33596 by setting CONFB pin to the low level. During an SPI access, the STROBE pin must remain

at high level to prevent the MC33596 from entering standby mode.

The interface is operated by six I/O pins.

•

CONFB — Configuration control input

The configuration mode is reached by setting CONFB to low level.

STROBE — Wakeup control input

•

The STROBE pin controls the ON/OFF sequence of the MC33596. When STROBE is set to low

level, the receiver is off—when STROBE is set to high level, the receiver is on. The current

consumption in receive mode can be reduced by strobing the receiver. The periodic wakeup can be

done by MCU only or by an internal oscillator thanks to an external capacitor (strobe oscillator

must be previously enabled by setting SOE bit to 1). Refer to Section 11.3, “Receiver On/Off

Control,” for more details.

•

SEB — Serial interface enable control input

When SEB is set high, pins SCLK, MOSI, and MISO are set to high impedance, and the SPI bus

is disabled. When SEB is set low, SPI bus is enabled. This allows individual selection in a multiple

device system, where all devices are connected via the same bus. The rest of the circuit remains in

the current state, enabling fast recovery times.

If the MCU shares the SPI access with the MC33596 only, SEB control by the MCU is optional.

If not used, it could be hardwired to 0.

•

SCLK — Serial clock input/output

Synchronizes data movement in and out of the device through its MOSI and MISO lines. The

master and slave devices can exchange a byte of information during a sequence of eight clock

cycles. Since SCLK is generated by the master device, this line is an input on the slave device.

MOSI — Master output slave input/output

In configuration mode, MOSI is an input.

In receive mode, MOSI is an output. Received data is sent on MOSI (see Table 5).

When no data are output, SCLK and MOSI force a low level.

MISO — Master input/slave output

•

In configuration mode only, data read from registers is sent to the MCU with the MSB first. There

is no master function. Data are valid on falling edges of SCLK. This means that the clock phase

and polarity control bits of the microcontroller SPI have to be CPOL = 0 and CPHA = 1 (using

Freescale acronyms).

Table 5 summarizes the serial digital interface feature versus the selected mode.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

9

State Machine

Table 5. Serial Digital Interface Feature versus Selected Mode

Selected Mode

Configuration

MC33596 Digital Interface Use

SPI slave, data received on MOSI, SCLK from MCU, MISO is output (SEB=0)

SPI master, data sent on MOSI with clock on SCLK (SEB=0)

SPI deselected, received data are directly sent to MOSI (SEB=0)

SPI deselected, all I/O are high impedance (SEB =1)

Receive DME = 1

DME = 0

Standby / LVD

Refer to Section 10, “State Machine,” and to Figure 2 for more details about all the conditions that must

be complied with in order to change between two selected modes.

The data transfer protocol for each mode is described in the following section.

10 State Machine

This section describes how the MC33596 controller executes sequences of operations, relative to the

selected mode. The controller is a finite state machine, clocked at T

. An overview is presented in

digclk

Figure 2 (note that some branches refer to other diagrams that provide more detailed information).

There are three different modes: configuration, receive, and standby/LVD. Each mode is exclusive and can

be entered in different ways, as follows.

•

External signal: CONFB for configuration mode

External signal and configuration bits: CONFB and TRXE for all other modes,

External signal and internal conditions: see Figure 3 and Figure 12 for information on how to

enter standby/LVD mode

After a Power-on Reset (POR), the circuit is in standby mode (see Figure 2) and the configuration register

contents are set to the reset value.

At any time, a low level applied to CONFB forces the finite state machine into configuration mode,

whatever the current state. This is not always shown in state diagrams, but must always be considered.

Refer to (Section 14, “Power-On Reset and MC33596 Startup”) for timing sequence between standy mode

and configuration mode.

MC33596 Data Sheet, Rev. 4

10

Freescale Semiconductor

State Machine

CONFB = 1,

Power-on Reset

and STROBE = 0

State 60

SPI Deselected

SPI Slave

Standby/LVD Mode

SPI Master

CONFB = 0,

and STROBE = 1

Refer to Table 5 for pins direction

CONFB = 0,

and STROBE = 1

Activate Bank Change,

(A to B or B to A)

State 1

CONFB = 1,

TRXE = 1

State 30

Transmit Mode

ConnffiigguurraatitoionnMModoede

Transmit Mode

CONFB = 1,

TRXE = 1

Receive Mode

… and DME = 0

… and DME = 1

… and SOE = 0

… and SOE = 1

… and SOE = 0

Figure4

Figure11

Figure12

See

Figure3

Figure 2. State Machine Overview

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

11

Receive Mode

11 Receive Mode

The receiver is either waiting for an RF transmission or is receiving one. Two different processes are

possible, as determined by the values of the DME bit. A state diagram describes the sequence of operations

in each case.

NOTE

If the STROBE pin is tied to a high level before switching to receive mode,

the receiver does not go through an off or standby state.

11.1 Data Manager Disabled (DME=0)

Data manager disabled means that the SPI is deselected and raw data is sent directly on the MOSI line,

while SCLK remains at low level.

Two different processes are possible, as determined by the values of the SOE bit.

11.1.1 Data Manager Disabled and Strobe Pin Control

Raw received data is sent directly on the MOSI line. Figure 3 shows the state diagram.

SPI Deselected

STROBE = 0

State 5

STROBE = 1

Standby/LVD

STROBE = 1

STROBE = 0

State 5b

On

Raw Data on MOSI

Figure 3. Receive Mode, DME = 0, SOE = 0

•

State 5:

The receiver is in standby/LVD mode. For further information, see Section 12, “Standby: LVD

Mode.” A high level applied to STROBE forces the circuit to state 5b.

State 5b:

The receiver is kept on by the STROBE pin. Raw data is output on the MOSI line.

For all states: At any time, a low level applied to CONFB forces the state machine to state 1, configuration

mode.

MC33596 Data Sheet, Rev. 4

12

Freescale Semiconductor

Receive Mode

11.1.2 Data Manager Disabled and Strobe Oscillator Enabled

Raw received data is sent directly on the MOSI line. Figure 4 shows the state diagram.

SPI Deselected

STROBE = 0

State 0

Off

STROBE = 1

Off Counter = ROFF[2:0]

or STROBE = 1

On Counter = RON[3:0]

and STROBE different than 1

State 0b

On

Raw Data on MOSI

Figure 4. Receive Mode, DME = 0, SOE = 1

•

State 0:

The receiver is off, but the strobe oscillator and the off counter are running. Forcing the STROBE

pin low freezes the strobe oscillator and maintains the system in this state.

State 0b:

If STROBE pin is set to high level or the off counter reaches the ROFF value, the receiver is on.

Raw data is output on the MOSI line.

For all states: At any time, a low level applied to CONFB forces the state machine to state 1, configuration

mode.

11.2 Data Manager Enabled (DME=1)

The data manager is enabled. The SPI is master. The MC33596 sends the recovered clock on SCLK and

the received data on the MOSI line. Data is valid on falling edges of SCLK.

If an even number of bytes is received, the data manager may add an extra byte. The content of this extra

byte is random. If the data received do not fill an even number of bytes, the data manager will fill the last

byte randomly. Figure 5 shows a typical transfer.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

13

Receive Mode

1

0

STROBE

CONFB

1

0

*Refer to

(Section 10)

SEB

1

0

SCLK

(Output)

1

0

Recovered Clock Updated to Incoming Signal Data Rate

MOSI

(Output)

1

0

D7 D6 D5 D4 D3 D2

D0 D7 D6 D5 D4 D3 D2

D0

D1

D0

D1

Figure 5. Typical Transfer in Receive mode with Data Manager

11.2.1 Data Manager Functions

In receive mode, Manchester coded data can be processed internally by the data manager. After decoding,

the data is available on the digital interface, in SPI format. This minimizes the load on the MCU.

The data manager, when enabled (DME = 1), has five purposes:

•

First ID detection: the received data are compared with the identifier stored in the ID register.

Then the HEADER recognition: the received data is compared with the data stored in the

HEADER register.

•

Clock recovery: the clock is recovered during reception of the preamble and is computed from the

shortest received pulse. While this signal is being received, the recovered clock is constantly

updated to the data rate of the incoming signal.

•

Output data and recovered clock on digital interface: see Figure 5.

End-of-message detection: an EOM consists of two consecutive NRZ ones or zeroes.

Table 6 details some MC33596 features versus DME values.

Table 6. the MC33596 Features versus DME

DME

Digital Interface Use

Data Format

Output

0

SPI deselected, received data

are directly sent to MOSI

when CONFB = 1

Bit stream

No clock

MOSI

—

1

SPI master, data sent on

MOSI with clock on SCLK

when CONFB = 1

Data bytes

Recovered clock

MOSI

SCLK

11.2.2 Manchester Coding Description

The MC33596 data manager is able to decode Manchester-coded messages. For other codings, the data

manager should be disabled (DME=0) for raw data to be available on MOSI.

MC33596 Data Sheet, Rev. 4

14

Freescale Semiconductor

Receive Mode

DME = 0: The data manager is disabled. The SPI is deselected. Raw data is sent directly on the MOSI line,

while SCLK remains at the low level.

Manchester coding is defined as follows: data is sent during the first half-bit; and the complement of the

data is sent during the second half-bit. The signal average value is constant.

0

1

0

1

0

ORIGINAL

DATA

MANCHESTER

CODED DATA

Figure 6. Example of Manchester Coding

Clock recovery can be extracted from the data stream itself. To achieve correct clock recovery,

Manchester-coded data must have a duty cycle between 47% and 53%.

11.2.3 Frame Format

A complete telegram includes the following sequences: a preamble, an identifier (ID), a header, the

message, and an end-of-message (EOM).

PREAMBLE ID ID ID ID HEADER DATA ………… EOM

Figure 7. Example of Frame Format

These bit sequences are described below.

11.2.3.1 Preamble

A preamble is required before the first ID detected. It enables:

— In the case of OOK modulation, the AGC to settle, and the data slicer reference voltage to

settle if DSREF = 1

— In the case of FSK modulation, the data slicer reference voltage to settle

— The data manager to start clock recovery

No preamble is needed in case of several IDs are sent as shown in Figure 8. The ID field must be greater

than two IDs. The first ID will have the same function as the preamble, and the second ID will have the

same function as the single ID.

... ID ID ID ID ID ID HEADER DATA …………

Figure 8. Example of Frame with Several IDs, No Preamble Needed

For both cases, the preamble content must be defined carefully, to ensure that it will not be decoded as the

ID or the header. Figure 9 defines the different preamble in OOK and FSK modulation.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

15

Receive Mode

OOK MODULATION (DSREF = 0)

AGC Settling Time

Clock Recovery

ID

1 NRZ > 200 μs (1)

1 Manchester

‘0’ Symbol

at Data Rate

OOK MODULATION (DSREF = 1)

AGC Settling Time

Data Slicer Reference Settling Time

Clock Recovery

ID

1 NRZ > 200 μs (1)

At Least 3 Manchester

0 Symbols

1 Manchester

0 Symbol

at Data Rate (2 and 3)

at Data Rate (3)

FSK MODULATION (DSREF = 1)

Data Slicer Reference Settling Time

Clock Recovery

ID

At Least 3 Manchester

0 Symbols

at Data Rate (2 and 3)

1 Manchester

0 Symbol

at Data Rate (3)

NOTES:

1. The AGC settling time pulse can be split over different pulses as long as the overall duration is at least 200 μs.

The 200 μs pulse may be replaced by : (1 bit @ 2400 bps or 2 bits @ 4800 bps or 4 bits @ 9600 bps or 8 bits @ 19200 bps).

2. Table 13 defines the minimum number of Manchester symbols required for the data slicer operation versus the data and average filter cut-off

frequencies.

3. The Manchester 0 symbol can be replaced by a 1.

Figure 9. Preamble Definition

11.2.3.2 ID

When clock recovery is done, the data manager verifies if an ID is received. The ID is used to identify a

useful frame to receive. It is also necessary, when the receiver is strobed, to detect an ID in order to stay

in run mode and not miss the frame.

The ID allows selection of the correct device in an RF transmission, as the content has been loaded

previously in the ID register. Its length is variable, defined by the IDL[1:0] bits. The complement of the

ID is also recognized as the identifier.

It is possible to build a tone to form the detection sequence by programming the ID register with a full

sequence of ones or zeroes.

Once the ID is detected, a HEADER will be searched to detect the beginning of the useful data to send on

the SPI port.

See Section 11.2.4, “State Machine in Receive Mode When DME=1” for more details when ID is not

detected when SOE=1 or SOE=0.

MC33596 Data Sheet, Rev. 4

16

Freescale Semiconductor

Receive Mode

11.2.3.3 HEADER

The HEADER defines the beginning of the message, as it is compared with the HEADER register. Its

length is variable, defined by the HDL[1:0] bits. The complement of the header is also recognized as the

header—in this case, output data is complemented. The header and its complement should not be part of

the ID.

The ID and the header are sent at the same data rate as data.

11.2.3.4 Data and EOM

The data must follow the header, with no delay.

The message is completed with an end-of-message (EOM), consisting of two consecutive NRZ ones or

zeroes (i.e., a Manchester code violation). Even in the case of FSK modulation, data must conclude with

an EOM, and not simply by stopping the RF transmission.

11.2.4 State Machine in Receive Mode When DME=1

When the strobe oscillator is enabled (SOE = 1), the receiver is continuously cycling on/off. The ID must

be recognized for the receiver to stay on. Consequently, the transmitted ID burst must be long enough to

include two consecutive receiver-on cycles.

When the strobe oscillator is not enabled (SOE = 0), these timing constraints must be respected by the

external control applied to pin STROBE.

Figure 11 shows the correct detection of an ID when STROBE is controled internally using the strobe

oscillator (SOE=1) or externally by the MCU (SOE=0).

RF

Signal

ID

Header

Data

Preamble

ID

EOM

ID Field

Receiver

Status

On

On Time

Off

On

Off

Off Time

ID

Detected

SPI

Output

Data

Figure 10. Complete Transmission with ID Detection

Two different processes are possible, as determined by the values of the SOE bit.

11.2.4.1 Data Manager Enabled and Strobe Oscillator Enabled

Figure 11 shows the state diagram when the data manager and the strobe oscillator are enabled. In this

configuration, the receiver is controlled internally by the strobe oscillator. However, external control via

the STROBE pin is still possible, and overrides the strobe oscillator command.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

17

Receive Mode

•

State 10:

The receiver is off, but the strobe oscillator and the off counter are running. Forcing STROBE pin

to the low level maintains the system in this state.

•

State 11:

The receiver is waiting for a valid ID. If an ID, or its complement, is detected, the state machine

advances to state 12; otherwise, the circuit goes back to state 10 at the end of the RON time, if

STROBE ≠ 1.

•

State 12:

An ID or its complement has been detected. The data manager is now waiting for a header or its

complement. If neither a header, nor its complement, has been received before a time-out of 256

bits at data rate, the system returns to state 10.

State 13:

A header, or its complement, has been received. Data and clock signals are output on the SPI port

until EOM indicates the end of the data sequence. If the complement of the header has been

received, output data are complemented also.

For all states: At any time, a low level applied to STROBE forces the circuit to state 10, and a low level

applied on CONFB forces the state machine to state 1, configuration mode.

When an EOM occurs before the current byte is fully shifted out, dummy bits are inserted until the number

of shifted bits is a multiple of 8.

MC33596 Data Sheet, Rev. 4

18

Freescale Semiconductor

Receive Mode

SPI Master

STROBE = 0

State 10

Off

STROBE = 1

Off Counter = ROFF[2:0]

or STROBE = 1

On Counter = RON[3:0]

State 11

On

and STROBE ≠ 1

Waiting For a Valid ID

ID Detected

State 12

On

Waiting for a Valid Header

Time Out

EOM Received

and STROBE = 1

Header Received

State 13

On

Output Data and Clock

Waiting for End of Message

EOM Received

and STROBE ≠ 1

Figure 11. Receive Mode, DME = 1, SOE = 1

11.2.4.2 Data Manager Enabled and Receiver Controlled by Strobe Pin

Figure 12 shows the state diagram when the data manager is enabled and the strobe oscillator is disabled.

In this configuration, the receiver is controlled only externally by the MCU.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

19

Receive Mode

SPI Master

STROBE = 0

SPI Deselected

State 20

Standby/LVD

STROBE = 1

State 21

On

STROBE = 0

Waiting For a Valid ID

ID Detected

State 22

On

Waiting for a Valid Header

STROBE = 0

EOM Received

and STROBE = 1

Header Received

State 23

On

Output Data and Clock

Waiting for End of Message

EOM Received

and STROBE = 0

Figure 12. Receive Mode, DME = 1, SOE = 0

•

State 20:

The receiver is in standby/LVD mode. For further information, see Section 12, “Standby: LVD

Mode.” A high level applied to STROBE forces the circuit to state 21.

State 21:

The circuit is waiting for a valid ID. If an ID, or its complement, is detected, the state machine

advances to state 22; if not, the state machine will remain in state 21, as long as STROBE is high.

State 22:

If a header, or its complement, is detected, the state machine advances to state 23. If not, the state

machine will remain in state 22, as long as STROBE is high.

State 23:

A header or its complement has been received; data and clock signals are output on the SPI port

until an EOM indicates the end of the data sequence. If the complement of the header has been

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

20

Receive Mode

received, output data are complemented also. When an EOM occurs before the current byte is fully

shifted out, dummy bits are inserted until the number of shifted bits is a multiple of 8.

For all states: At any time, a low level applied to STROBE puts the circuit into state 20, and a low level

applied to CONFB forces the state machine to state 1, configuration mode.

11.2.4.3 Timing Definition

As shown in Figure 13, a settling time is required when entering the on state.

Receiver

Status

Off

On

Off

On

Setting

Time

Ton

Toff

RF

Signal

ID ID ID

ID ID ID ID ID

ID

Data

Header

EOM

ID

Detected

Figure 13. Receiver Usable Window

The goal for the receiver is to recognize at least one ID during Ton time. Many IDs are transmitted during

that time.

During Ton, the receiver should be able to detect an ID, but as receiver and transmitter are not

synchronized, an ID may already be transmitted when Ton time begins. That is the reason why Ton should

be sized to receive two IDs: to be sure to recognize one, no matter what the time difference between

beginning of transmission of the ID and beginning of run time for the receiver.

Ton should also include the setting time of the receiver. Setting time is composed of the crystal oscillator

1

2

3

wakeup time , the PLL lock time , and setup of all analog parameters (AGC and demodulator need some

time to settle).

Toff should be sized to allow the positioning of an on state during the transmission of the ID field.

During the setting time, no reception is possible.

11.3 Receiver On/Off Control

In receive mode, on/off sequencing can be controlled internally using the strobe oscillator, or managed

externally by the MCU through the input pin STROBE.

If the strobe oscillator is selected (SOE = 1):

•

Off time is clocked by the strobe oscillator

On time is clocked by the crystal oscillator, enabling accurate control of the on time, and therefore

of the current consumption of the whole system

1. Refer to parameter 5.10 found in Section 19.4, “PLL & Crystal Oscillator.”

2. Refer to parameter 5.9 found in Section 19.4, “PLL & Crystal Oscillator.”

3. Refer to preamble definition found in Figure 9.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

21

Receive Mode

Each time is defined with the associated value found in the RXONOFF register.

•

On time = RON[3:0] × 512 × T

(see Table 16; begins after the crystal oscillator has started)

digclk

Off time = receiver off time = N × T

from ROFF[2:0] (see Table 17)

+ MIN (T

/ 2, receiver on time), with N decoded

Strobe

The strobe oscillator is a relaxation oscillator in which an external capacitor C13 is charged by an internal

current source (see Figure 46). When the threshold is reached, C13 is discharged and the cycle restarts.

6

The strobe frequency is F

= 1/T

with T

= 10 × C13.

Strobe

In receive mode, setting the STROBE pin to V

at any time forces the circuit on. As V

is above

CCIO

the oscillator threshold voltage, the condition on which the STROBE pin is set to V

is detected

CCIO

internally, and the oscillator pulldown circuitry is disabled. This limits the current consumption. After the

STROBE pin is forced to high level, the external driver should pass via a “0” state to discharge the

capacitor before going to high impedance state (otherwise, the on time would last a long time after the

driver release).

When the strobe oscillator is running (i.e., during an off time), forcing the STROBE pin to V

strobe clock, and therefore keeps the circuit off.

stops the

GND

Figure 14 shows the associated timings.

Threshold

STROBE

SET TO V_CCIO

STROBE

Clock

t_Strobe

Off

0

Counter

ROFF-1ROFF

Digital

Clock

On

Counter

0

RON

Receiver

Status

Off

On

Off

On

Cycling Period

Crystal Oscillator Startup

Figure 14. Receiver On/Off Sequence

11.4 Received Signal Strength Indicator (RSSI)

11.4.1 Module Description

In receive mode, a received signal strength indicator can be activated by setting bit RSSIE.

The input signal is measured at two different points in the receiver chain by two different means, as

follows.

•

At the IF filter output, a progressive compression logarithmic amplifier measures the input signal,

ranging from the sensitivity level up to –50 dBm.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

22

Receive Mode

•

At the LNA output, the LNA AGC control voltage is used to monitor input signals in the range

–50 dBm to –20 dBm.

Therefore, the logarithmic amplifier provides information relative to the in-band signal, whereas the LNA

AGC voltage senses the input signal over a wider band.

The RSSI information given by the logarithmic amplifier is available in:

•

Analog form on pin RSSIOUT

Digital form in the four least significant bits of the status register RSSI

The information from the LNA AGC is available in digital form in the four most significant bits of status

register RSSI.

The whole content of status register RSSI provides 2 ¥ 4 bits of RSSI information about the incoming

signal (see Section 16.6, “RSSI Register”).

Figure 15 shows a simplified block diagram of the RSSI function.

The quasi peak detector (D1, R1, C1) has a charge time of about 20 μs to avoid sensitivity to spikes.

R2 controls the decay time constant of about 5 ms to allow efficient smoothing of the OOK modulated

signal at low data rates. This time constant is useful in continuous mode when S2 is permanently closed.

To allow high-speed RSSI updating in peak pulse measurement, a discharge circuit (S1) is required to reset

the measured voltage and to allow new peak detection.

RSSI Register

LNA AGC Out

IF Filter Output

ADC

MSB

S2

LSB

D1

R1

Σ

RSSIOUT

C1

R2

S1

C2

Figure 15. RSSI Simplified Block Diagram

S2 is used to sample the RSSI voltage to allow peak pulse measurement (S2 used as sample and hold), or

to allow continuous transparent measurement (S2 continuously closed).

The 4-bit analog-to-digital convertor (ADC) is based on a flash architecture. The conversion time is

16 × T

on a 32 × T

. As a single convertor is used for the two analog signals, the RSSI register content is updated

diglck

timebase.

digclk

If RSSIE is reset, the whole RSSI module is switched off, reducing the current consumption. The output

buffer connected to RSSIOUT is set to high impedance.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

23

Receive Mode

11.4.2 Operation

Two modes of operation are available: sample mode and continuous mode.

11.4.2.1 Sample Mode

Sample mode allows the peak power of a specific pulse in an incoming frame to be measured.

The quasi peak detector is reset by closing S1. After 7 × T

, S1 is released. S2 is closed when RSSIC

digclk

is set high. On the falling edge of RSSIC, S2 is opened. The voltage on RSSIOUT is sampled and held.

The last RSSI conversion results are stored in the RSSI register and no further conversion is done.

The RSSI register is updated every 32 × T

. Therefore, the minimum duration of the high pulse on

digclk

RSSIC is 32 × T

.

digclk

RSSIC

7 x t_digclk

Closed

Open

Closed

S1

S2

Open

Closed

Open

Frozen

Updated

Frozen

RSSI Register

Sampled and Hold RSSI Voltage

RSSIOUT

Peak Detector

Reset

Sampling

CONFB

MOSI

CMD

RSSI Value

MISO

Figure 16. RSSI Operation in Sample Mode

11.4.2.2 Continuous Mode

Continuous mode is used to make a peak measurement on an incoming frame, without having to select a

specific pulse to be measured.

The quasi peak detector is reset by closing S1. After 7 × T

, S1 is opened. S2 is closed when RSSIC

digclk

is set high. As long as RSSIC is kept high, S2 is closed, and RSSIOUT follows the peak value with a decay

time constant of 5 ms.

The ADC runs continuously, and continually updates the RSSI register. Thus, reading this register gives

the most recent conversion value, prior to the register being read. The minimum duration of the high pulse

on CONFB is 32 × T

.

digclk

MC33596 Data Sheet, Rev. 4

24

Freescale Semiconductor

Standby: LVD Mode

RSSIC

5 x t_digclk

Closed

S1

S2

Open

Closed

RSSI Register

Frozen

Updated

Frozen

Updated

Frozen

RSSIOUT

Peak Detector

Test

CONFB

MOSI

CMD

MISO

RSSI

Figure 17. RSSI Operation in Continuous Mode

12 Standby: LVD Mode

The SPI is deselected. CONFB is set to high level and STROBE to low level in order to enter this mode.

Nothing is sent and all incoming data are ignored until CONFB and SEB go low to switch back to

configuration mode.

Standby/LVD mode allows minimum current consumption to be achieved. Depending upon the value of

the LVDE bit, the circuit is in standby mode (state 60) or LVD mode (state 5 and 20).

LVDE = 0: The receiver is in standby; consumption is reduced to leakage current (current state after POR).

LVDE = 1: The LVD function is enabled; consumption is in the range of tens of microamperes.

The only way to exit this mode is to go back to configuration mode by applying a low level to CONFB and

a high level to STROBE.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

25

Configuration Mode

13 Configuration Mode

13.1 Description

This mode is used to write or read the internal registers of the MC33596.

As long as a low level is applied to CONFB and a high level to STROBE (see Figure 2), the MCU is the

master node driving the SCLK input, the MOSI line input, and the MISO line output. Whatever the

direction, SPI transfers are 8-bit based and always begin with a command byte, which is supplied by the

MCU on MOSI. To be considered as a command byte, this byte must come after a falling edge on CONFB.

Figure 18 shows the content of the command byte.

Bit 7

N1

Bit 6

N0

Bit 5

A4

Bit 4

A3

Bit 3

A2

Bit 2

A1

Bit 1

A0

Bit 0

R/W

Bit Name

Figure 18. Command Byte

Bits N[1:0] specify the number of accessed registers, as defined in Table 7.

Table 7. Number N of Accessed Registers

N[1:0]

Number N of Accessed Registers

00

01

10

11

1

2

4

8

Bits A[4:0] specify the address of the first register to access. This address is then incremented internally

by N after each data byte transfer.

R/W specifies the type of operation:

0 = Read

1 = Write

Thus, this bit is associated with the presence of information on MOSI (when writing) or MISO (when

reading).

Figure 19 and Figure 20 show write and read operations in a typical SPI transfer. In both cases, the SPI is

a slave. A received byte is considered internally on the eighth falling edge of SCLK. Consequently, the last

received bits, which do not form a complete byte, are lost.

Refer to Section 19.8, “Digital Interface Timing,” to view the timing definition for SPI communication.

If several SPI accesses are done, a high and low level is applied to CONFB, and so on. By applying a high

level to STROBE, the MC33596 never enters standby mode. If there is no way to configure the level on

STROBE, the time interval between two SPI accesses must be less than one digital clock period T

.

digclk

MC33596 Data Sheet, Rev. 4

26

Freescale Semiconductor

Configuration Mode

NOTE

A low level applied to CONFB and a high level to STROBE do not affect

the configuration register contents.

1

0

STROBE

SEB

1

0

1

0

CONFB

1

0

SCLK

(Input)

MOSI

(Input)

1

0

N1 N0 A4 A3 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

MISO

(Output)

1

0

Figure 19. Write Operation in Configuration Mode (N[1:0] = 01)

1

0

STROBE

SEB

1

0

1

0

CONFB

SCLK

(Input)

1

0

MOSI

(Input)

1

0

N1 N0 A4 A3 A2 A1 A0 R/W

1

0

MISO

(Output)

D7 D6 D5 D4 D3 D2 D1

D0

D7 D6 D5 D4 D3 D2 D1 D0

Figure 20. Read Operation in Configuration Mode (N[1:0] = 01)

13.2 State Machine

The configuration mode is selected by the microcontroller unit (MCU) to write to the internal registers (to

configure the system) or to read them. In this mode, the SPI is a slave. The analog parts (receiver) remain

in the state (on, off) they were in prior to entering configuration mode, until a new configuration changes

them. In configuration mode, data can not be received. As long as a low level is applied to CONFB, the

circuit stays in State 1, the only state in this mode.

Figure 21 describe the valid sequence for enabling a correct transition from Standby/LVD mode to

configuration mode. SPI startup time corresponds to the addition of the crystal oscillator lock time

(parameter 5.10) and the PLL lock time (parameter 5.9).

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

27

Power-On Reset and MC33596 Startup

STROBE

CONFB

SPI Startup Time

SEB

Figure 21. Valid Sequence from Standby/LVD Mode to Configuration Mode

Figure 22 describes the sequence for enabling a correct transition from receive mode to configuration

mode.

1. MC33596 is in receive mode.

2. CONFB is forced to low level during one digital period T

only.

in order to reset the state machine

digclk

3. CONFB is set to high level during the time length of an ID.

1

2

3

STROBE

CONFB

SEB

SCLK

MOSI

Figure 22. Valid Sequence from Receive Mode to Configuration Mode

14 Power-On Reset and MC33596 Startup

The startup sequence can be divided into three stages as defined in Figure 23:

1. The power supply is applied to the MC33596 and an external pullup resistor on CONFB is required

to enter standby mode. SEB can be either set to low level if the SPI access is not shared with

another external MCU, or connected to an external pullup resistor (see Section 9, “MCU

Interface”).

During this stage and during the ramp-up of the power supply, signals from the MCU connected to

the MC33596 are undefined. That is why the MC33596 must start in standby mode.

NOTE

Along with the ramp-up of power supply, one of these two conditions must

be complied with:

— Power supply of the MC33596 must rise in 1 ms from 0 V to 3 V.

— The level on STROBE pin is lower than 0.75 V until the power supply reaches 3 V.

MC33596 Data Sheet, Rev. 4

28

Freescale Semiconductor

Configuration Switching

Proposed solutions to verify these conditions are :

— If the receiver does not wake periodically and it is only controlled by the STROBE pin (strobe

oscillator disable SOE = 0), an external pulldown resistor on STROBE is required (see

Figure 43 for a 3 V application schematic).

— If the receiver wakes periodically (strobe oscillator enable SOE = 1), the state of the MCU

pins must be defined first and then a power supply must be applied to the MC33596. A

transistor can be used to control the power supply on the VCCIN pin of the MC33596. This

transistor will be driven by an MCU I/O (see Figure 44 for a 3 V application schematic in

strobe oscillator mode).

2. A high level is applied on STROBE in order to wake the MC33596 and enter receive mode. The

duration of this state should be greater than the sum of lock time parameter 5.9 and 5.10. Refer to

Section 13, “Configuration Mode.”

3. CONFB and SEB must be forced to low level to enter configuration mode. Register values are

writen into the internal registers of the MC33596. Refer to Section 13, “Configuration Mode,”

and to Figure 41.

1

2

3

3V

0

VCC

1

0

STROBE

*Refer to

(Section 10)

SEB

1

0

1

0

1

CONFB

SCLK

MOSI

0

1

0

N1N0 A4 A3 A2 A1 A0 R/W

D7D6 D5 D4 D3 D2 D1 D0

1

0

MISO

Figure 23. Startup sequence

15 Configuration Switching

This feature allows for defining two different configurations using two different banks, and for switching

them automatically during wakeup when using a strobe oscillator, or by means of the strobe pin actuation

by the MCU. This automatic feature may be used only in receiver mode; thus allowing fast switching

between any different possible configurations.

15.1 Bit Definition

Two sets of configuration registers are available. They are grouped in two different banks: Bank A and

Bank B. Two bits are used to define which bank represents the state of the component.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

29

Configuration Switching

Bit Name

Direction

Location

BANKA

BANKB

R/W

Bank A

Bank B

BANKA

BANKB

Actions

X

0

1

0

1

Bank A is active

Bank B is active

Bank A and Bank B are active and will be used one after the other

At any time, it is possible to know which is the active bank by reading the status bit BANKS.

Bit Name Direction Location

BANKS A & B

Comment

R

Bank status: indicates which register bank is active.

This bit, available in Bank A and Bank B, returns the same value.

MC33596 Data Sheet, Rev. 4

30

Freescale Semiconductor

Configuration Switching

15.1.1 Direct Switch Control

The conditions to enter direct switch control are:

•

Strobe pin = V

SOE bit = 0

CC

By simply writing BANKA and BANKB, the active bank will be defined:

BANKA BANKB

X

0

1

0

1

Bank A is active

Bank B is active

Not allowed in direct switch control

The defined bank is active after exiting the configuration mode, in other words, CONFB line goes high.

The direct switch control should be used when:

•

When the strobe oscillator cannot be used to define the switch timing (for example, not periodic)

When strobe pin use is not possible (no sleep mode between the two configurations)

No automatic switching is required and MCU SPI access is possible

15.1.2 Strobe Pin Switch Control

The conditions to enter strobe pin switch control are:

•

Strobe pin: controlled by MCU I/O port

SOE bit = 0

By simply writing BANKA and BANKB, the active banks will be defined.

BANKA BANKB

X

0

1

0

1

Bank A is active

Bank B is active

Bank A and Bank B are both active, configuration will toggle at each wakeup

The strobe pin will control the off/on state of the MC33596. The various available sequences are described

in the following subsections.

15.1.2.1 BANKA = X, BANKB = 0

State A

OFF

State A

OFF

Strobe Pin

If strobe pin is 1, configuration is defined by Bank A, BANKS = 1.

If strobe pin is 0, MC33596 configuration is OFF.

If a message is received during State A, current state remains State A up to end of message.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

31

Configuration Switching

15.1.2.2 BANKA = 0, BANKB = 1

State B

OFF

State B

OFF

Strobe Pin

If strobe pin is 1, configuration is defined by Bank B, BANKS = 0.

If strobe pin is 0, MC33596 configuration is OFF.

If a message is received during State B, current state remains State B up to end of message.

15.1.2.3 BANKA = 1, BANK B = 1

State A

OFF

State B

OFF

State A

Strobe Pin

Banks Bit

If strobe pin is 1, configuration is defined by BANKS. BANKS is toggled at each falling edge of the strobe

pin.

If strobe pin is 0, MC33596 configuration is OFF.

If a message is received during state A or state B, current state remains the same up to end of message.

If a read or write access is done using SPI, the next sequence will begin with state A whatever was the

active state before SPI access by MCU.

15.1.3 Strobe Oscillator Switch Control

The conditions to enter strobe oscillator switch control are:

•

Strobe pin connected to an external capacitor to define timing (see Section 11.3, “Receiver

On/Off Control”)

•

Strobe pin can also be connected to the MCU I/O port

SOE bit = 1

By simply writing BANKA and BANKB, the active banks will be defined.

BANKA BANKB

X

0

1

0

1

Bank A is active

Bank B is active

Bank A and Bank B are both active, configuration will toggle at each wakeup

The MCU can override strobe oscillator control by controlling the strobe pin level. If MCU I/O port is in

high impedance, the strobe oscillator will control the OFF/ON state of the MC33596. The various

available sequences are described in the following subsections.

MC33596 Data Sheet, Rev. 4

32

Freescale Semiconductor

Configuration Switching

15.1.3.1 BANKA = X, BANKB = 0

State A

OFF

State A

OFF

State A

If strobe pin is 1, configuration is defined by Bank A, BANKS = 1.

If strobe pin is 0, MC33596 configuration is OFF.

If a message is received during State A, current state remains State A up to end of message.

15.1.3.2 BANKA = 0, BANKB = 1

State B

OFF

State B

OFF

State B

If strobe pin is 1, configuration is defined by Bank B, BANKS = 0.

If strobe pin is 0, MC33596 configuration is OFF.

If a message is received during State B, current state remains State B up to end of message.

15.1.3.3 BANKA = 1, BANK B = 1

State A

State B

OFF

StateA

StateB

OFF

Banks Bit

BANKS toggles at the end of each state A or state B.

If strobe is forced to 1, configuration is frozen according to BANKS value.

If a read or write access is done using SPI, the next sequence will begin with state A in whatever was the

active state before SPI access by MCU.

A

B

OFF

A

B

OFF

A

B

OFF

A

B

1

Z

Strobe

Banks

For all available sequences:

•

State A and State B are defined by Bank A and Bank B.

State A duration, TonA is defined by Bank A RON[3–0].

State B duration, TonB is defined by Bank B RON[3–0].

OFF duration, TonB is defined by Bank A ROFF[2–0].

If strobe pin is 1, the state is ON and defined by BANKS at that time. It remains this state up to

the release of strobe and end of message if a message is being received.

•

If a message is being received during State A or B, current state remains State A or B up to end of

message.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

33

Register Description

•

If strobe pin is 0 the state is OFF.

If strobe pin is released from 0 while state is OFF, the initial OFF period is completed.

The change of duration of one state (due to the STROBE pin level or a message being received) has no

influence on the timing of the following states (A, B, or OFF).

16 Register Description

This section discusses the internal registers, which are composed of two classes of bits.

•

Configuration and command bits allow the MC33596 to operate in a suitable configuration.

Status bits report the current state of the system.

All registers can be accessed by the SPI. These registers are described below.

At power-on, the POR resets all registers to a known value (in the shaded rows in the following tables).

This defines the MC33596’s default configuration.

16.1 Configuration Registers (Description Bank A only)

Figure 24 describes configuration register 1, CONFIG1.

Bit 7

LOF1

1

Bit 6

LOF0

0

Bit 5

CF1

0

Bit 4

CF0

1

Bit 3

RESET

0

Bit 2

SL

Bit 1

LVDE

0

Bit 0

CLKE

1

Addr

$00

Bit Name

Reset Value

Access

0

R/W

Figure 24. CONFIG1 Register

Table 8. LOF[1:0] and CF[1:0] Setting Versus Carrier Frequency

Carrier Frequency

LOF1

LOF0

CF1

CF0

304 MHz

315 MHz

426 MHz

434 MHz

868 MHz

915 MHz

0

1

0

1

0

1

0

1

0

1

RESET is a global reset. The bit is cleared internally, after use.

0 = no action

1 = reset all registers and counters

SL (Switch Level) selects the active level of the SWITCH output pin.

MC33596 Data Sheet, Rev. 4

34

Freescale Semiconductor

Register Description

Table 9. Active Level of SWITCH Output Pin

SL

Receiver Function

Level on SWITCH

0

Receiving

—

Low

High

Low

High

1

—

Receiving

LVDE (Low Voltage Detection Enable) enables the low voltage detection function.

0 = disabled

1 = enabled

NOTE

This bit is cleared by POR. In the event of a complete loss of the supply

voltage, LVD is disabled at power-up, but the information is not lost as the

status bit LVDS is set by POR.

CLKE (Clock Enable) controls the DATACLK output buffer.

0 = DATACLK remains low

1 = DATACLK outputs F

dataclk

Figure 25 describes configuration register 2, CONFIG2.

Bit 7

DSREF

0

Bit 6

FRM

0

Bit 5

MODU

0

Bit 4

DR1

1

Bit 3

DR0

0

Bit 2

TRXE

0

Bit 1

DME

0

Bit 0

SOE

0

Addr

$01

Bit Name

Reset Value

Access

R/W

Figure 25. CONFIG2 Register

DSREF (Data Slicer Reference) selects the data slicer reference.

0 = Fixed reference (cannot be used in FSK)

1 = Adaptive reference (recommended for maximum sensitivity in OOK and FSK)

In the case of FSK modulation (MODU = 1), DSREF must be set.

FRM (Frequency Register Manager) enables either a user friendly access or a direct access to one

frequency register.

0 = The carrier frequency is defined by the F register

1 = The local oscillator frequency is defined by the F register.

MODU (Modulation) sets the data modulation type.

0 = On/Off Keying (OOK) modulation

1 = Frequency Shift Keying (FSK) modulation

DR[1:0] (Data Rate) configure the receiver blocks operating in base band.

•

Low-pass data filter

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

35

Register Description

•

Low-pass average filter generating the data slicer reference, if DSREF is set

Data manager

Table 10. Base Band Parameter Configuration

Data Filter

Cut-off Frequency

Average Filter

Cut-off Frequency

Data Manager

Data Rate Range

DR1

DR0

0

1

0

1

0

1

6 kHz

12 kHz

24 kHz

48 kHz

0.5 kHz

1 kHz

2 kHz

4 kHz

2–2.8 kBd

4–5.6 kBd

8–10.6 kBd

16–22.4 kBd

If the data manager is disabled, the incoming signal data rate must be lower than or equal to the data

manager maximum data rate.

TRXE (Receiver Enable) enables the whole receiver. This bit must be set to high level if MCU wakes the

MC33956 to enter receive mode.

0 = standby mode

1 = other modes can be activated

DME (Data Manager Enable) enables the data manager.

0 = disabled

1 = enabled

SOE (Strobe Oscillator Enable) enables the strobe oscillator.

0 = disabled

1 = enabled

Figure 26 describes configuration register 3, CONFIG3.

Bit 7

AFF1

0

Bit 6

AFF0

0

Bit 5

OLS

1

Bit 4

LVDS

1

Bit 3

ILA1

0

Bit 2

ILA0

0

Bit 1

—

Bit 0

—

Addr

$02

Bit Name

Reset Value

Access

0

R/W

R

R/W

—

Figure 26. CONFIG3 Register

OLS (Out of Lock Status) indicates the current status of the PLL.

0 = The PLL is in lock-in range

1 = The PLL is out of lock-in range

LVDS (Low Voltage Detection Status) indicates that a low voltage event has occurred when LVDE = 1.

This bit is read-only and is cleared after a read access.

0 = No low voltage detected

1 = Low voltage detected

ILA[1:0] (Input Level Attenuation) define the RF input level attenuation.

MC33596 Data Sheet, Rev. 4

36

Freescale Semiconductor

Register Description

Table 11. RF Input Level Attenuation

RF Input Level

See Parameter

Number

ILA1

ILA0

Attenuation

0

1

0

1

0

1

0 dB

8 dB

2.5

2.6

2.7

2.8

16 dB

30 dB

Values in Table 11 assume the LNA gain is not reduced by the AGC.

AFF[1:0] (Average Filter Frequency) define the average filter cut-off frequency if the AFFC bit is set.

Table 12. Average Filter Cut-off Frequency

Average Filter Cut-off

AFF1

AFF0

Frequency

0

1

0

1

0

1

0.5 kHz

1 kHz

2 kHz

4 kHz

If AFFC is reset, the average filter frequency is directly defined by bits DR[1:0], as shown in Table 10.

If AFFC is set, AFF[1:0] allow the overall receiver sensitivity to be improved by reducing the average

filter cut-off frequency. The typical preamble duration of three Manchester zeroes or ones at the data rate

must then be increased, as shown in Table 13.

Table 13. Minimum Number of Manchester Symbols in Preamble

versus DR[1:0] and AFF[1:0]

DR[1:0]

00

01

10

11

3

6

12

24

00

01

10

11

—

3

6

3

12

6

AFF[1:0]

—

3

16.2 Command Register

Figure 27 describes the Command register, COMMAND.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

37

Register Description

Bit 7

Bit 6

IFLA

0

Bit 5

—

Bit 4

RSSIE

0

Bit 3

EDD

1

Bit 2

RAGC

0

Bit 1

FAGC

0

Bit 0

Addr

$03

Bit Name

Reset Value

Access

AFFC

0

BANKS

0

1

R/W

—

R/W

R

Figure 27. COMMAND Register

AFFC (Average Filter Frequency Control) enables direct control of the average filter cut-off frequency.

0 = Average filter cut-off frequency is defined by DR[1:0]

1 = Average filter cut-off frequency is defined by AFF[1:0]

IFLA (IF Level Attenuation) controls the maximum gain of the IF amplifier in OOK modulation.

0 = No effect

1 = Decreases by 20 dB (typical) the maximum gain of the IF amplifier, in OOK modulation only

The reduction in gain can be observed if the IF amplifier AGC system is disabled (by setting RAGC = 1).

RSSIE (RSSI Enable) enables the RSSI function.

0 = Disabled

1 = Enabled

EDD (Envelop Detector Decay) controls the envelop detector decay.

0 = Slow decay for minimum ripple

1 = Fast decay

RAGC (Reset Automatic Gain Control) resets both receiver internal AGCs.

0 = No action

1 = Sets the gain to its maximum value

A first SPI access allows RAGC to be set; a second SPI access is required to reset it.

FAGC (Freeze Automatic Gain Control) freezes both receiver AGC levels.

0 = No action

1= Holds the gain at its current value

BANKS indicates which register bank is active. This bit, available in Bank A and Bank B, returns the same

value.

0 = Bank B

1 = Bank A

16.3 Frequency Register

Figure 28 defines the Frequency register, F.

MC33596 Data Sheet, Rev. 4

38

Freescale Semiconductor

Register Description

Bit 15

—

Bit 14

—

Bit 13

—

Bit 12

—

Bit 11

F11

1

Bit 10

F10

0

Bit 9

F9

0

Bit 8

F8

0

Addr

$04

Bit Name

Reset Value

0

1

0

Bit 7

F7

Bit 6

F6

Bit 5

F5

Bit 4

F4

Bit 3

F3

Bit 2

F2

Bit 1

F1

0

Bit 0

F0

0

Bit Name

$05

Reset Value

0

Figure 28. F Register

How this register is used is determined by the FRM bit, which is described below.

FRM = 0 (User Friendly Access)

Bits F[11:0] define the carrier frequency F

. The local oscillator frequency F is then set

LO

carrier

automatically to F

+ F (with F = intermediate frequency).

carrier

IF IF

FRM = 1 (Direct Access)

F[11:0] defines the receiver local oscillator frequency F

LO

Table 14 defines the value to be binary coded in the frequency registers F[11;0], versus the desired

frequency value F (in Hz).

Table 14. Frequency Register Value versus Frequency Value F

CF[1:0]

Frequency Register Value

00, 01

11

(2 x F/F_ref-35) x 2048

(F/F_ref-35) x 2048

Conversely, Table 15 gives the desired frequency F and the frequency resolution versus the value of the

frequency registers F[11;0].

Table 15. Frequency Value F versus Frequency Register Value

CF[1:0]

Frequency (Hz)

Frequency Resolution (Hz)

00, 01

11

(35 + F[11;0]/2048)xF_ref/2

(35 + F[11;0]/2048)xF_ref

F_ref/4096

F_ref/2048

16.4 Receiver On/Off Duration Register

Figure 29 describes the receiver on/off duration register, RXONOFF.

Bit 7

BANKA

0

Bit 6

RON3

1

Bit 5

RON2

1

Bit 4

RON1

1

Bit 3

RON0

1

Bit 2

ROFF2

1

Bit 1

ROFF1

1

Bit 0

ROFF0

1

Addr

$09

Bit Name

Reset Value

Access

R/W

Figure 29. RXONOFF Register

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

39

Register Description

BANKA defines the register bank selected, as described in Section 15, “Configuration Switching.”

RON[3:0] (Receiver On) define the receiver on time (after crystal oscillator startup) as described in

Section 11.3, “Receiver On/Off Control.”

Table 16. Receiver On Time Definition

RON[3:0]

Receiver On Time: N x 512 x T_digclk

0000

0001

0010

...

Forbidden value

1

2

...

15

1111

ROFF[2:0] (Receiver Off) define the receiver off time as described in Section 11.3, “Receiver On/Off

Control.”

Table 17. Receiver Off Time Definition

ROFF[2:0]

Receiver Off Time: N x T_Strobe

000

001

010

011

100

101

110

111

1

2

4

8

12

16

32

63

16.5 ID and Header Registers

Figure 30 defines the ID register, ID.

Bit 7

IDL1

1

Bit 6

IDL0

1

Bit 5

ID5

0

Bit 4

ID4

0

Bit 3

ID3

0

Bit 2

ID2

0

Bit 1

ID1

0

Bit 0

ID0

0

Addr

$0A

Bit Name

Reset Value

Access

R/W

Figure 30. ID Register

IDL[1:0] (Identifier Length) sets the length of the identifier, as shown on Table 18.

MC33596 Data Sheet, Rev. 4

40

Freescale Semiconductor

Register Description

Table 18. ID Length Selection

IDL1

IDL0

ID Length

0

1

0

1

0

1

2 bits

4 bits

5 bits

6 bits

ID[5:0] (Identifier) sets the identifier. The ID is Manchester coded. Its LSB corresponds to the register’s

LSB, whatever the specified length.

Figure 31 defines the Header register, HEADER.

Bit 7

HDL1

1

Bit 6

HDL0

0

Bit 5

HD5

0

Bit 4

HD4

0

Bit 3

HD3

0

Bit 2

HD2

0

Bit 1

HD1

0

Bit 0

HD0

0

Addr

$0B

Bit Name

Reset Value

Access

R/W

Figure 31. HEADER Register

HDL[1:0] (Header Length) sets the length of the header, as shown on Table 19.

Table 19. Header Length Selection

HDL1

HDL0

HD Length

0

1

0

1

0

1

1 bits

2 bits

4 bits

6 bits

HD[5:0] (Header) sets the header. The header is Manchester coded. Its LSB corresponds to the register’s

LSB, whatever the specified length.

16.6 RSSI Register

Figure 32 describes the RSSI Result register, RSSI.

Bit 7

RSSI7

0

Bit 6

RSSI6

0

Bit 5

RSSI5

0

Bit 4

RSSI4

0

Bit 3

RSSI3

0

Bit 2

RSSI2

0

Bit 1

RSSI1

0

Bit 0

RSSI0

0

Addr

$0C

Bit Name

Reset Value

Access

R

Figure 32. RSSI Register

Bits RSSI[7:4] contain the result of the analog-to-digital conversion of the signal measured at the LNA

output.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

41

Bank Access and Register Mapping

Bits RSSI[3:0] contain the result of the analog-to-digital conversion of the signal measured at the IF filter

output.

17 Bank Access and Register Mapping

Registers are physically mapped following a byte organization. The possible address space is 32 bytes. The

base address is specified in the command byte. This is then incremented internally to address each register,

up to the number of registers specified by N[1:0], also specified by this command byte. All registers can

then be scanned, whatever the type of transmission (read or write); however, writing to read-only bits or

registers has no effect. When the last implemented address is reached, the internal address counter

automatically loops back to the first mapped address ($00).

At any time, it is possible to write or read the content of any register of Bank A and Bank B. Register access

is defined as follows:

R/W

R

Bit can be read and written.

Bit can be read. Write has no effect on bit value.

Bit can be read. Read or write resets the value.

RR

R [A]

RR [A]

Bit can be read. This returns the same value as Bank A.

Bit can be read. This returns the same value as Bank A. Read or write resets the value.

Table 20. Access to Specific Bits

Bit

Bank

Byte

Access

Comment

RESET

OLS

A

CONFIG1

CONFIG3

R/W

Available in BANKA.

A, B

R-R[A]

Bit value is the real time status of the PLL, BANKA,

and BANKB access reflect the same value.

LDVS

SOE

A, B

CONFIG3

CONFIG2

RSSI

RR-RR[A}

R/W-R[A}

R-R[A}

Bit value is the latched value of the low-voltage

detector. Read or write from any bank resets value.

SOE can be modified in BANKA. Access from BANKB

reflects BANKA value.

RSSIx

RSSI value is directly read from RSSI converter.

Reflected value is the same whatever the active byte.

MC33596 Data Sheet, Rev. 4

42

Freescale Semiconductor

Transition Time

18 Transition Time

Table 21 details the different times that must be considered for a given transition in the state machine, once

the logic conditions for that transition are met.

Table 21. Transition Time Definition

Crystal

Oscillator

Startup Time,

Parameter 5.10

Receiver

Transition

State x -> y

PLL Timing

Preamble On-to-Off Time,

Time¹

Parameter 1.12

Standby to SPI running, state 60 -> 1

√

Standby to receiver running, states 5 -> 5b, 20 -> 21

Lock time parameter

5.9

√

Off to receiver running, states 0 -> 0b, 10 -> 11

√

Lock time parameter

5.9

Configuration to receiver running,

states 1 -> (0b, 5b, 11, 21)

0 or lock time

parameter 5.1 or lock

time parameter 5.9 ²

Receiver running to configuration mode,

state (0b, 5b, 11, 12, 13, 21, 22, 23) -> 1,

When CONFB=0, the transition from receive mode to configuration

mode is immediate.

Receiver running to standby mode,

state 5b -> 5, (21, 22, 23) -> 20

√

Receiver running to off mode,

state 0b -> 0, (11, 12, 13) -> 10

N₁OTES:

See Section 11.2.3, “Frame Format.”

Depending on the PLL status before entering configuration mode. For example, the transition time from standby to receiver

running (FSK modulation, 19.2 kBd, AFFC = 0, data manager enabled) is: 0.6 ms + 50 µs + (3 + 1)/19.2k = 970 µs.

2

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

45

Electrical Characteristics

19 Electrical Characteristics

19.1 General Parameters

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

3.0 V, T_A= 25°C.

=

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

1.2 Supply current in receive mode Receiver on

—

2.4

—

10.3

24

13

50

mA

μA

nA

μA

μs

V

1.3

Strobe oscillator only

1.6 Supply current in standby mode –40°C ≤ T_A≤ 25°C

260

700

1200

50

1.8

T_A= 85°C

800

1.9 Supply current in LVD mode

1.12 Receiver on-to-off time

LVDE = 1

35

Supply current reduced to 10%

100

—

1.13 VCC2 voltage regulator output 2.7 V < V_CC

2.6

2.8

—

1.14

2.1 V ≤ V_CC≤ 2.7 V

V_CC–0.1

V

1.15 VCCDIG2 voltage regulator

output

Circuit in standby mode

(V_CCDIG= 3 V)

0.7 x

V_CCDIG

—

V

1.16

Circuit in all other modes

1.4

2.4

1.6

—

1.8

—

V

1.19 Voltage on VCC (Preregulator

output)

Receive mode with VCCIN=5V

19.2 Receiver: RF Parameters

RF parameters assume a matching network between test equipment and the D.U.T, and apply to all bands

unless otherwise specified.

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

=

3.0 V, T_A= 25°C.

Limits

Test Conditions,

Max

(FCE,

FJE)

Max

(FCAE,

FJAE)

Parameter

Unit

Comments

Min

Typ

2.2 OOK sensitivity at 315 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps, PER = 0.1

—

–104

–103.5

–103

–99

–98

–97

–96

dBm

2.40 OOK sensitivity at 434 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps, PER = 0.1

2.41 OOK sensitivity at 868 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps, PER = 0.1

MC33596 Data Sheet, Rev. 4

46

Freescale Semiconductor

Electrical Characteristics

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

3.0 V, T_A= 25°C.

=

Limits

Test Conditions,

Comments

Max

(FCE,

FJE)

Max

(FCAE,

FJAE)

Parameter

Unit

Min

Typ

2.42 OOK sensitivity at 916 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps, PER = 0.1

—

–103

–98

–96

dBm

2.24 FSK sensitivity at 315 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps,

–106.5

–102

–100

DF_carrier= ±64 kHz, PER = 0.1

2.50 FSK sensitivity at 434 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps,

—

–105.5

–104.5

–105.4

–101

–100

–102

–99

–98

dBm

DF_carrier= ±64 kHz, PER = 0.1

2.51 FSK sensitivity at 868 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps,

DF_carrier= ±64 kHz, PER = 0.1

2.52 FSK sensitivity at 916 MHz DME = 1, DSREF = 1,

DR = 4.8 kbps,

–100

DF_carrier= ±64 kHz, PER = 0.1

2.35 Sensitivity improvement in DME = 0

RAW mode

—

0.6

—

dB

%

2.36 Duty Cycle for Manchester

coded data

47

53

2.37 Data Rate¹

2

—

64

0

22.6

170

—

22.6

170

—

kbps

kHz

dB

2.38 FSK deviation range

32

—

2.5 Sensitivity reduction

ILA[1:0] = 00

ILA[1:0] = 01

ILA[1:0] = 10

ILA[1:0] = 11

2.6

2.7

2.8

8

—

dB

16

30

–4

—

dB

—

dB

2.9 In-band jammer

desensitization

Sensitivity reduced by 3 dB CW

jammer at F_carrier± 50 kHz/OOK

—

dBc

2.60

Sensitivity reduced by 3 dB CW

jammer at F_carrier± 50 kHz/FSK

—

–6

37

40

—

dBc

2.11 Out-of-band jammer

desensitization

Sensitivity reduced by 3dB

CW jammer at F_carrier±1 MHz

2.12

Sensitivity reduced by 3dB

CW jammer at F_carrier± 2 MHz

2.13 RFIN parallel resistance

2.14 RFIN parallel resistance

2.15 RFIN parallel capacitance

Receive mode

Standby mode

Receive mode

—

1300

—

300

—

Ω

1.2

pF

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

47

Electrical Characteristics

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

3.0 V, T_A= 25°C.

=

Limits

Test Conditions,

Max

(FCE,

FJE)

Max

(FCAE,

FJAE)

Parameter

Unit

Comments

Min

Typ

2.17 Maximum detectable signal, Modulation depth: 99%,

OOK level measured on a NRZ ‘1’

–25

-10

—

dBm

2.25 Maximum detectable signal, ΔF_carrier= ±64kHz

—

FSK

2.18 Image frequency rejection 304–434 MHz

20

15

36

20

—

dB

2.19

868–915 MHz

N₁OTES:

See Table 10 for additional information.

OOK Sensitivity Variation vs Temperature

(Ref : 3V, 25°C, 4800bps)

1.4

1.2

1

315 MHz

434 MHz

868 MHz

916 MHz

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-40°C

25°C

85°C

Temperature (°C)

Figure 34. OOK Sensitivity Variation Versus Temperature

MC33596 Data Sheet, Rev. 4

48

Freescale Semiconductor

Electrical Characteristics

OOK Sensitivity Variation vs Voltage

(Ref : 3V, 25°C, 4800bps)

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

315 MHz

434 MHz

868 MHz

916 MHz

2.1 V

2.4 V

3 V

3.6 V

Voltage (V)

Figure 35. OOK Sensitivity Variation Versus Voltage

FSK Sensitivity Variation vs Temperature

(Ref : 3V, 25°C, +/-64kHz, 4800 bps )

1.4

1.2

1

315 MHz

434 MHz

868 MHz

916 MHz

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-40°C

25°C

Temperature (°C)

85°C

Figure 36. FSK Sensitivity Variation Versus Temperature

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

49

Electrical Characteristics

FSK Sensitivity Variation vs Voltage

(Ref : 3V, 25°C, +/-64kHz, 4800bps )

0.5

0.4

0.3

0.2

0.1

0

315 MHz

434 MHz

868 MHz

916 MHz

-0.1

-0.2

2.1 V

2.4 V

3 V

3.6 V

Voltage (V)

Figure 37. FSK Sensitivity Variation Versus Voltage

Sensitivity Variation Versus Data Rate

(Ref : 25°C, 3V, 434MHz , OOK, 4800bps)

5

4

3

2

1

0

-1

-2

-3

2400

4800

9600

19200

Data Rate (bps)

Figure 38. OOK Sensitivity Variation Versus Data Rate

MC33596 Data Sheet, Rev. 4

50

Freescale Semiconductor

Electrical Characteristics

Sensitivity Variation vs Data Rate

(Ref : 25°C, 3V, 434MHz , FSK +/-64kHz, 4800bps)

5

4

3

2

1

0

-1

-2

-3

2400

4800

9600

19200

Data Rate (bps)

Figure 39. FSK Sensitivity Variation Versus Data Rate

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

51

Electrical Characteristics

Sensitivity Variation Versus Frequency Deviation

(Ref :25°C, 3V, 434MHz, FSK +/-64kHz, 4800bps)

2,0

1, 5

1, 0

0,5

0,0

-0,5

-1,0

30

40

50

60

70

80

90

100

110

120

130

140

150

160

170

Frequency Deviation (kHz)

Figure 40. FSK Sensitivity Variation Versus Frequency Deviation

19.3 Receiver Parameters

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematics Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC= 3.0

V, T_A= 25°C.

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

Receiver: IF filter, IF Amplifier, FM-to-AM Converter and Envelope Detector

3.1 IF center frequency

—

1.5

380

—

MHz

kHz

MHz

ms

3.2 IF bandwidth at –3dB

Refer to Section 8, “Frequency

Planning”.

3.3 IF cut-off low frequency at –3 dB

3.4 IF cut-off high frequency at –3 dB

—

1.387

—

1.635

—

3.12 Recovery time from strong signal OOK modulation, 2.4 kbps,

FAGC = 0, input signal from

15

—

–50 dBm to –100 dBm

MC33596 Data Sheet, Rev. 4

52

Freescale Semiconductor

Electrical Characteristics

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematics Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC= 3.0

V, T_A= 25°C.

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

Receiver: Analog and Digital RSSI

3.51 Analog RSSI output signal for

Measured on RSSIOUT

380

420

850

1000

0

—

650

700

1200

1300

2

mV

Input signal @–108 dBm

3.52 Analog RSSI output signal for

Input signal @–100 dBm

3.53 Analog RSSI output signal for

Input signal @–70 dBm

3.54 Analog RSSI output signal for

Input signal @–28 dBm

3.55 Digital RSSI Registers for Input RSSI [0:3]

signal @–108 dBm

3.56 Digital RSSI Registers for Input

signal @–100 dBm

0

3

3.57 Digital RSSI Registers for Input

signal @–70 dBm

9

13

3.58 Digital RSSI Registers for Input

signal @–28 dBm

13

0

16

3.59 Digital RSSI Registers for Input RSSI [4:7]

signal @–70 dBm

2

3.6 Digital RSSI Registers for Input

signal @–50 dBm

4

8

3.61 Digital RSSI Registers for Input

signal @–24 dBm

13

15

19.4 PLL & Crystal Oscillator

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at

V

_CC= 3.0 V, T_A= 25 °C.

Limits

Typ

Test Conditions

Comments

Parameter

Unit

Min

Max

5.9 PLL lock time

RF frequency ±25kHz

—

50

30

100

—

μs

5.1 Toggle time between 2

frequencies

RF frequency step <1.5MHz,

RF frequency ±25kHz

5.10 Crystal oscillator startup time

5.8 Crystal series resistance

—

0.6

—

1.2

ms

120

Ω

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

53

Electrical Characteristics

Examples of crystal characteristics are given in Table 22.

Table 22. Typical Crystal Reference and Characteristics

Reference & Type

434 MHz

315 MHz

868 MHz

LN-G102-1183

NX5032GA

NDK

LN-G102-1182

NX5032GA

NDK

EXS00A-01654

NX5032GA

NDK

Parameter

Frequency

Unit

17.5814

24.19066

24.16139

MHz

pF

Load capacitance

ESR

8

25

15

<70

Ω

19.5 Strobe Oscillator (SOE = 1)

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 46,), unless otherwise specified. Typical values reflect average measurement at V_CC

= 3.0 V, T_A= 25°C.

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

6.1 Period range

T

_Strobe= 10⁶.C3

0.1

—

1

—

10

ms

nF

μA

V

6.2 External capacitor C3

6.3 Sourced/sink current

6.4 High threshold voltage

6.5 Low threshold voltage

6.6 Overall timing accuracy

With 1% resistor R13

—

1

—

0.5

—

V

With 1% resistor R13 & 5%

capacitor C3,

–14.2

15.8

%

±3 sigma variations

MC33596 Data Sheet, Rev. 4

54

Freescale Semiconductor

Electrical Characteristics

19.6 Digital Input: CONFB, MOSI, SCLK, SEB, STROBE,

RSSIC

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

=

3.0 V, T_A= 25°C.

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

7.7 Input low voltage

MOSI, SCLK, SEB, RSSIC⁽¹⁾

—

0.8 x V_CC2

0.1 x V_CC2

—

0.4 x V_CC2

V

7.8 Input high voltage

7.9 Input hysteresis

7.10 Input low voltage

7.11 Input high voltage

7.12 Input hysteresis

7.5 Sink current

7.6

—

V

CONFB, STROBE²

0.4 x V_CCDIG2

V

0.8 x V_CCDIG2

0.1 x V_CCDIG2

1

—

V

Configuration, receive, modes

standby or LVD modes

100

10

nA

0.5

N₁OTES:

Input levels of those pins are referenced to V_CC2which depends upon V_CC(see Section 5, “Power Supply”).

Input levels of those pins are referenced to V_CCDIG2which depends upon the circuit state (see Section 5, “Power Supply”).

2

19.7 Digital Output

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

3.0 V, T_A= 25°C.

=

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

Digital Output: DATACLK, LVD, MISO, MOSI, SCLK

8.1 Output low voltage

|

_ILOAD|= 50 μA

—

0.8 x V_CCIO

—

80

0.2 x V_CCIO

V

8.2 Output high voltage

8.3 Fall and rise time

—

From 10% to 90% of the

output swing,

150

ns

C_LOAD= 10pF

Digital Output: SWITCH (V_CC= 3V)

8.4 Output low voltage

8.5 Output high voltage

|

_ILOAD|= 50 μA

—

0.2 x V_CC

—

V

0.8 x V_CC

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

55

Electrical Characteristics

19.8 Digital Interface Timing

Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application

schematic (see Figure 43 through Figure 54), unless otherwise specified. Typical values reflect average measurement at V_CC

3.0 V, T_A= 25°C.

=

Limits

Test Conditions

Parameter

Unit

Comments

Min

Typ

Max

9.2 SCLK period

1

20

—

μs

9.8 Configuration enable time

9.3 Enable lead time

1

Crystal oscillator is running.

3 x T_digclk

9.4 Enable lag time

100

—

ns

μs

2

9.5 Sequential transfer delay

9.6 Data hold time

—

Receive mode, DME = 1,

from SCLK to MOSI

3 x T_digclk

—

100

—

9.7 Data setup time

9.9

Configuration mode,

from SCLK to MISO

—

ns

Configuration mode, from

SCLK to MOSI

120

100

9.10 Data setup time

N₁OTES:

Configuration mode, from

SCLK to MOSI

—

See Section 8.1, “Clock Generator” for T_digclkvalues.

2

The digital interface can be used in SPI burst protocol, i.e., with a continuous clock on SCLK port. For example, one (or more)

read access followed by one (or more) write access and so on. In this case and for a practical use, the pulse required on

CONFB between accesses must be higher than 100 ns only if STROBE signal is always set to high level.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

56

Application Schematics

STROBE

CONFB

9.8

SEB

9.3

9.5

9.4

SCLK

MOSI

MISO

9.2

9.10

9.9

9.7

Figure 41. Digital Interface Timing Diagram in Configuration Mode

SEB

CONFB

STROBE

9.3

SCLK

(input)

9.6

MOSI

(output)

Figure 42. Digital Interface Timing Diagram in Receive Mode (DME = 1)

20 Application Schematics

Examples of application schematics are proposed for Receiver.

Note: The external pullup resistor set on SEB pin (R2) is not mandatory. Instead of R2, an external

pulldown resistor of 10 k may be connected between SEB pin and ground.

20.1 Receiver Schematics

Figure 43 and Figure 44 show the application schematic in receive mode for 3 V operation.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

57

Application Schematics

Figure 45 and Figure 46 show the application schematic in receive mode for 5 V operation.

20.1.1 Receiver Schematics in 3 V Operation—MCU Controls

Wakeup

24

RSSI OUT

25

STROBE

VCC

26

34

R4

10k

3V

C1 2

100pF VCC2

C11

100nF

GND

SW ITCH

VCC

R2

10k

R3

10k

C1

1

24

27

SEB

RSSIOUT

SEB

100nF VCC2

2

3

4

5

6

7

8

23

22

21

20

19

18

17

31

29

32

30

28

33

SCLK

VCC2RF

RFIN

SCLK

MOSI

L1

MOSI

C2 1nF

MI SO

GNDLNA

VCC2VCO

GND

MISO

C3

C4

VCC2

U1

CON FB

DATACLK

RSSI C

CONFB

DATACLK

RSSIC

MC33596

C5

100pF

NC

GND

GNDDIG

VCC

C7

1nF

VCC2

X7

C10

100nF

R1

470k 1%

C8

100nF

C9

100nF

C6

6.8pF

Figure 43. MC33596 Application Schematic (3 V)

The ON/OFF sequencing in receive mode is controlled by driving a low or high level by the MCU on

STROBE pin.

MC33596 Data Sheet, Rev. 4

58

Freescale Semiconductor

Application Schematics

20.1.2 Receiver Schematics in 3V Operation—Strobe Oscillator

Mode

RSSI OUT

C13

1nF

STROBE

VCC

3V

C1 2

100pF VCC2

C11

100nF

GND

SW ITCH

VCC

R2

10k

R3

10k

C1

1

24

23

22

21

20

19

18

17

SEB

RSSIOUT

SEB

100nF VCC2

2

3

4

5

6

7

8

SCLK

VCC2RF

RFIN

SCLK

MOSI

L1

MOSI

C2 1nF

MI SO

GNDLNA

VCC2VCO

GND

MISO

C3

C4

VCC2

U1 8

CON FB

DATACLK

RSSI C

CONFB

DATACLK

RSSIC

MC33596

C5

100pF

NC

GND

GNDDIG

VCC

C7

1nF

VCC2

X4

C10

100nF

R1

470k 1%

C8

100nF

C9

100nF

C6

6.8pF

Figure 44. MC33596 Application Schematic in Strobe mode (3 V)

The ON/OFF sequencing in receive mode is controlled internally. The STROBE pin from the MCU has to

be configured in high impedance and wakeup mode is available when SOE bit is enabled.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

59

Application Schematics

20.1.3 Receiver Schematics in 5 V Operation—MCU Controls

Wakeup

24

RSSI OUT

25

STROBE

VCC

26

34

R5

10k

5V

C1 2

100pF VCC2

C11

100nF

GND

SW ITCH

VCC

R2

10k

R3

10k

C1

1

24

27

SEB

RSSIOUT

SEB

100nF VCC2

2

3

4

5

6

7

8

23

22

21

20

19

18

17

31

29

32

30

28

33

SCLK

VCC2RF

RFIN

SCLK

MOSI

L1

MOSI

C2 1nF

MI SO

GNDLNA

VCC2VCO

GND

MISO

C3

C4

VCC2

U18

CON FB

DATACLK

RSSI C

CONFB

DATACLK

RSSIC

MC33596

C5

100pF

NC

GND

GNDDIG

C7

1nF

VCC2

X8

C10

R1

C8

100nF

C9

100nF

470k 1%

C6

6.8pF

Figure 45. MC33596 Application Schematic (5 V)

The ON/OFF sequencing in receive mode is controlled by driving a low or high level by the MCU on

STROBE pin.

MC33596 Data Sheet, Rev. 4

60

Freescale Semiconductor

Application Schematics

20.1.4 Receiver Schematics in 5 V Operation—Strobe Oscillator

Mode

13

RSSI OUT

C13

1nF

14

STROBE

VCC

15

5V

C1 2

100pF VCC2

C11

100nF

23

GND

SW ITCH

VCC

R2

10k

R3

10k

C1

1

24

16

SEB

RSSIOUT

SEB

100nF VCC2

2

3

4

5

6

7

8

23

22

21

20

19

18

17

20

18

21

19

17

22

SCLK

VCC2RF

RFIN

SCLK

MOSI

L1

MOSI

C2 1nF

MI SO

GNDLNA

VCC2VCO

GND

MISO

C3

C4

VCC2

U1

CON FB

DATACLK

RSSI C

CONFB

DATACLK

RSSIC

MC33596

C5

100pF

NC

GND

GNDDIG

C7

1nF

VCC2

X5

C10

R1

C8

100nF

C9

100nF

470k 1%

C6

6.8pF

Figure 46. MC33596 Application Schematic in Strobe Mode (5 V)

The ON/OFF sequencing in receive mode is controlled internally. The STROBE pin from the MCU has to

be configured in high impedance and wake up mode is available when SOE bit is enabled.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

61

PCB Design Recommendations

21 PCB Design Recommendations

Pay attention to the following points and recommendations when designing the layout of the PCB.

•

Ground Plane

— If you can afford a multilayer PCB, use an internal layer for the ground plane, route power

supply and digital signals on the last layer, with RF components on the first layer.

— Use at least a double-sided PCB.

— Use a large ground plane on the opposite layer.

— If the ground plane must be cut on the opposite layer for routing some signals, maintain

continuity with another ground plane on the opposite layer and a lot of via to minimize

parasitic inductance.

•

Power Supply, Ground Connection and Decoupling

— Connect each ground pin to the ground plane using a separate via for each signal; do not use

common vias.

— Place each decoupling capacitor as close to the corresponding VCC pin as possible (no more

than 2–3 mm away).

— Locate the VCCDIG2 decoupling capacitor (C10) directly between VCCDIG2 (pin 14) and

GND (pin 16).

RF Tracks, Matching Network and Other Components

— Minimize any tracks used for routing RF signals.

— Locate crystal X1 and associated capacitors C6 and C7 close to the MC33596. Avoid loops

occurring due to component size and tracks. Avoid routing digital signals in this area.

— Use high frequency coils with high Q values for the frequency of operation (minimum of 15).

Validate any change of coil source.

NOTE

The values indicated for the matching network have been computed and

tuned for the MC33596 RF Modules available for MC33596 evaluation.

Matching networks should be retuned if any change is made to the PCB

(track width, length or place, or PCB thickness, or component value). Never

use, as is, a matching network designed for another PCB.

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

62

Case Outline Dimensions

22 Case Outline Dimensions

22.1 LQFP32 Case

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

63

Case Outline Dimensions

MC33596 Data Sheet, Rev. 4

64

Freescale Semiconductor

Case Outline Dimensions

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

65

Case Outline Dimensions

22.2 QFN32 Case

MC33596 Data Sheet, Rev. 4

66

Freescale Semiconductor

Case Outline Dimensions

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

67

Case Outline Dimensions

MC33596 Data Sheet, Rev. 4

68

Freescale Semiconductor

Case Outline Dimensions

MC33596 Data Sheet, Rev. 4

Freescale Semiconductor

69

How to Reach Us:

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

circuits or integrated circuits based on the information in this document.

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Freescale Semiconductor reserves the right to make changes without further notice to

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limitation consequential or incidental damages. “Typical” parameters that may be

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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.

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Document Number: MC33596

Rev. 4

02/2010


型号：	MC33596_10
厂家：	Freescale
描述：	PLL Tuned UHF Receiver for Data Transfer Applications 锁相环调谐UHF接收器的数据传输应用数据传输
文件：	总70页 (文件大小：943K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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