MC33910BACR2 [FREESCALE]
LIN System Basis Chip with 2x60mA High Side Drivers; LIN系统基础芯片2x60mA高边驱动器
| 型号： | MC33910BACR2 |
| 厂家： | 
Freescale |
| 描述： | LIN System Basis Chip with 2x60mA High Side Drivers |
| 文件： | 总44页 (文件大小：780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33910
Rev. 4.0, 2/2008
Freescale Semiconductor
Advance Information
LIN System Basis Chip with
2x60mA High Side Drivers
33910
The 33910 is a Serial Peripheral Interface (SPI)-controlled System
Basis Chip (SBC), that combines many frequently used functions in
an MCU-based system, plus a Local Interconnect Network (LIN)
transceiver. It has a 5.0V, 60mA low dropout regulator with full
protection and reporting features. The device provides full SPI-
readable diagnostic and a selectable timing watchdog for detecting
errant operation. The LIN Protocol Specification, version 2.0
compliant LIN transceiver has waveshaping circuitry that can be
disabled for higher data rates.
SYSTEM BASIS CHIP WITH LIN
2ND GENERATION
Two 60mA high side switches with optional pulse-width modulation
(PWM) are implemented to drive small loads. One high voltage input
is available for use in contact monitoring or as external wake-up input.
This input can be used as high voltage Analog Input as well. The
voltage on this pin is divided by a selectable ratio and available via an
analog multiplexer.
The 33910 has three main operating modes: Normal (all functions
available); Sleep (VDD off, wake-up via LIN, wake-up input (L1), cyclic
sense and forced wake-up) and Stop (VDD on with limited current
capability, wake-up via CS, LIN bus, wake-up input, cyclic sense,
forced wake-up and external reset).
AC SUFFIX (Pb-FREE)
98ASH70029A
32-PIN LQFP
The 33910 is compatible with LIN Protocol Specification 2.0.
Features
ORDERING INFORMATION
Temperature
• Two 60mA high side switches
• One high voltage analog/logic input
Device
Package
Range (T )
A
• Full-duplex SPI at frequencies up to 4MHz
• LIN transceiver capable of up to 100kbps with wave shaping
• Configurable window watchdog
MC33910BAC/R2
MC34910BAC/R2
-40°C to 125°C
-40°C to 85°C
32-LQFP
• 5.0V low drop regulator with fault detection and low voltage
reset (LVR) circuitry
• Switched/protected 5.0V output (used for Hall sensors)
• Pb-free packaging designated by suffix code AC
33910
VBAT
VSENSE
HS1
VS1
VS2
L1
VDD
PWMIN
ADOUT0
LIN INTERFACE
LIN
MCU
MOSI
MISO
SCLK
CS
RXD
TXD
IRQ
HVDD
HS2
WDCONF
RST
Figure 1. 33910 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
RST IRQ
VS2
VS1
VDD
INTERRUPT
CONTROL
MODULE
AGND
PGND
VOLTAGE REGULATOR
LVI, HVI, HTI, OCI
RESET CONTROL
MODULE
LVR, HVR, HTR, WD
5V OUTPUT
MODULE
HVDD
WINDOW
WATCHDOG
MODULE
VS2
HIGH SIDE
CONTROL
MODULE
PWMIN
HS1
HS2
VS2
MISO
MOSI
SCLK
SPI
&
CONTROL
VBAT
SENSE MODULE
VSENSE
CS
CHIP TEMPERATURE
SENSE MODULE
ADOUT0
L1
ANALOG INPUT
MODULE
WAKE-UP MODULE
DIGITAL INPUT MODULE
RXD
TXD
LIN PHYSICAL
LAYER
LIN
LGND
WDCONF
Figure 2. 33910 Simplified Internal Block Diagram
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
PIN CONNECTIONS
PIN CONNECTIONS
RXD
TXD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
HS2
L1
MISO
NC*
NC*
NC*
NC*
PGND
NC*
MOSI
SCLK
CS
ADOUT0
PWMIN
* Special Configuration Recommended /
Mandatory for Marked NC Pins
Figure 3. 33910 Pin Connections
Table 1. 33910 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Pin Name
Formal Name
Definition
This pin is the receiver output of the LIN interface which reports the state of
the bus voltage to the MCU interface.
1
RXD
Receiver Output
This pin is the transmitter input of the LIN interface which controls the state of
the bus output.
2
TXD
Transmitter Input
SPI data output. When CS is high, the pin is in the high-impedance state.
SPI data input.
3
4
5
6
7
8
MISO
MOSI
SPI Output
SPI Input
SPI clock Input.
SCLK
SPI Clock
SPI chip select input pin. CS is active low.
Analog multiplexer output.
CS
SPI Chip Select
Analog Output Pin 0
PWM Input
ADOUT0
PWMIN
High side pulse width modulation input.
Bidirectional reset I/O pin - driven low when any internal reset source is
asserted. RST is active low.
9
RST
IRQ
NC
Internal Reset I/O
Interrupt output pin, indicating wake-up events from Stop Mode or events from
Normal and Normal Request Modes. IRQ is active low.
Internal Interrupt
Output
10
11, 15-17,
19-22, 28
No connect
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33910 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on page 20.
Pin
Pin Name
Formal Name
Definition
This input pin is for configuration of the watchdog period and allows the
disabling of the watchdog.
Watchdog
Configuration Pin
12
13
14
WDCONF
LIN
This pin represents the single-wire bus transmitter and receiver.
LIN Bus
This pin is the device LIN ground connection. It is internally connected to the
PGND pin.
LGND
LIN Ground Pin
This pin is the device power ground connection. It is internally connected to
the LGND pin.
18
PGND
Power Ground Pin
This pin is a wake-up capable digital input(1). In addition, L1 can be sensed
analog via the analog multiplexer.
23
24, 25
26, 27
29
L1
Wake-up Input
High Side Outputs
Power Supply Pin
Voltage Sense Pin
High side switch outputs.
HS2, HS1
VS2, VS1
VSENSE
HVDD
These pins are device battery level power supply pins. VS2 is supplying the
HS1 driver while VS1 supplies the remaining blocks.(2)
Battery voltage sense input.(3)
Hall Sensor Supply
Output
+5.0V switchable supply output pin.(4)
30
Voltage Regulator
Output
+5.0V main voltage regulator output pin.(5)
31
32
VDD
This pin is the device analog ground connection.
AGND
Analog Ground Pin
Notes
1. When used as digital input, a series 33kΩ resistor must be used to protect against automotive transients.
2. Reverse battery protection series diodes must be used externally to protect the internal circuitry.
3. This pin can be connected directly to the battery line for voltage measurements. The pin is self protected against reverse battery
connections. It is strongly recommended to connect a 10kΩ resistor in series with this pin for protection purposes.
4. External capacitor (1µF < C < 10µF; 0.1Ω < ESR < 5Ω) required.
5. External capacitor (2µF < C < 100µF; 0.1Ω < ESR < 10Ω) required.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Supply Voltage at VS1 and VS2
Normal Operation (DC)
V
V
-0.3 to 27
-0.3 to 40
SUP(SS)
VSUP(PK)
Transient Conditions (load dump)
Supply Voltage at VDD
VDD
-0.3 to 5.5
V
V
Input / Output Pins Voltage(6)
V
-0.3 to VDD+0.3
CS, RST, SCLK, PWMIN, ADOUT0, MOSI, MISO, TXD, RXD
IN
Interrupt Pin (IRQ)(7)
V
-0.3 to 11
IN(IRQ)
HS1 Pin Voltage (DC)
HS2 Pin Voltage (DC)
V
V
-0.3 to VSUP+0.3
-0.3 to VSUP+0.3
V
V
V
HS1
HS2
L1 Pin Voltage
V
-18 to 40
±100
L1DC
Normal Operation with a series 33kΩ resistor (DC)
Transient input voltage with external component (according to ISO7637-2)
(See Figure 5, page 16)
V
L1TR
VSENSE Pin Voltage (DC)
VVSENSE
-27 to 40
V
V
LIN Pin Voltage
VBUSDC
VBUSTR
-18 to 40
Normal Operation (DC)
-150 to 100
Transient input voltage with external component (according to ISO7637-2)
(See Figure 4, page 16)
VDD output current
I
Internally Limited
A
V
VDD
ESD Voltage(8)
V
V
±8000
±2000
±200
Human Body Model - LIN Pin
Human Body Model - all other Pins
Machine Model
ESD1-1
ESD1-2
V
ESD2
Charge Device Model
Corner Pins (Pins 1, 8, 9, 16, 17, 24, 25 and 32)
All other Pins (Pins 2-7, 10-15, 18-23, 26-31)
V
V
±750
±500
ESD3-1
ESD3-2
VNC
NC Pin Voltage (NC pins 11, 15, 16, 17, 19, 20, 21, 22, and 28)(9)
Note 9
Notes
6. Exceeding voltage limits on specified pins may cause a malfunction or permanent damage to the device.
7. Extended voltage range for programming purpose only.
8. Testing is performed in accordance with the Human Body Model (C
= 100 pF, R
= 1500 Ω), the Machine Model (C = 200 pF,
ZAP
ZAP
ZAP
R
= 0Ω), and the Charge Device Model, Robotic (C
= 4.0pF).
ZAP
ZAP
9. Special configuration recommended / mandatory for marked NC pins. Please refer to the typical application shown on page 40.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings (continued)
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
THERMAL RATINGS
Operating Ambient Temperature(10)
T
°C
A
33910
34910
-40 to 125
-40 to 85
Operating Junction Temperature(10)
Storage Temperature
T
-40 to 150
-55 to 150
°C
°C
J
TSTG
RθJA
Thermal Resistance, Junction to Ambient
°C/W
Natural Convection, Single Layer board (1s)(11), (12)
Natural Convection, Four Layer board (2s2p)(11), (13)
85
56
Thermal Resistance, Junction to Case(14)
Peak Package Reflow Temperature During Reflow(15), (16)
Notes
RθJC
23
°C/W
TPPRT
Note 16
°C
10. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking.
11. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
12. Per JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
13. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
15. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
16. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SUPPLY VOLTAGE RANGE (VS1, VS2)
VSUP
5.5
–
–
–
–
18
27
40
V
V
V
Nominal Operating Voltage
Functional Operating Voltage(17)
Load Dump
VSUPOP
VSUPLD
–
SUPPLY CURRENT RANGE (VSUP = 13.5V)
Normal Mode (IOUT at V
= 10mA), LIN Recessive State(18)
IRUN
–
4.5
10
mA
µA
DD
Stop Mode, VDD ON with IOUT = 100µA, LIN Recessive State(18), (19), (20)
ISTOP
5.5V < VSUP < 12V
VSUP = 13.5V
–
–
48
58
80
90
Sleep Mode, VDD OFF, LIN Recessive State(18), (20)
5.5V < VSUP < 12V
ISLEEP
µA
–
–
27
37
35
48
12V ≤ VSUP < 13.5V
Cyclic Sense Supply Current Adder(21)
ICYCLIC
–
10
–
µA
V
SUPPLY UNDER/OVER-VOLTAGE DETECTIONS
Power-On Reset (BATFAIL)(22)
Threshold (measured on VS1)(21)
Hysteresis (measured on VS1)(21)
VBATFAIL
1.5
–
3.0
0.9
3.9
–
VBATFAIL_HYS
VSUP under-voltage detection (VSUV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
V
V
Threshold (measured on VS1)
Hysteresis (measured on VS1)
VSUV
VSUV_HYS
5.55
–
6.0
1.0
6.6
–
VSUP over-voltage detection (VSOV Flag) (Normal and Normal Request
Modes, Interrupt Generated)
VSOV
VSOV_HYS
Threshold (measured on VS1)
Hysteresis (measured on VS1)
18
–
19.25
1.0
20.5
–
Notes
17. Device is fully functional. All features are operating.
18. Total current (IVS1 + IVS2) measured at GND pins excluding all loads, Cyclic Sense disabled.
19. Total IDD current (including loads) below 100µA.
20. Stop and Sleep Mode currents will increase if VSUP exceeds13.5V.
21. This parameter is guaranteed by process monitoring but, not production tested.
22. The flag is set during power up sequence. To clear the flag, a SPI read must be performed.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
VOLTAGE REGULATOR(23) (VDD)
Normal Mode Output Voltage
1.0mA < I < 50mA; 5.5V < V
Symbol
Min
Typ
Max
Unit
VDDRUN
V
< 27V
SUP
4.75
60
5.00
110
5.25
200
VDD
Normal Mode Output Current Limitation
Dropout Voltage(24)
IVDDRUN
mA
V
VDDDROP
I
= 50mA
–
0.1
0.25
VDD
Stop Mode Output Voltage
< 5mA
V
V
DDSTOP
I
4.75
6.0
5.0
12
5.25
36
VDD
Stop Mode Output Current Limitation
Line Regulation
I
mA
mV
VDDSTOP
LR
Normal Mode, 5.5V < V
Stop Mode, 5.5V < V
< 18V; I
= 10mA
VDD
RUN
–
–
20
25
25
SUP
LR
STOP
< 18V; I
= 1.0mA
VDD
5.0
SUP
Load Regulation
mV
°C
LD
Normal Mode, 1.0mA < I
< 50mA
RUN
–
–
15
10
80
50
VDD
LD
STOP
Stop Mode, 0.1mA < I
< 5mA
VDD
Over-temperature Prewarning (Junction)(25)
Interrupt generated, Bit VDDOT Set
T
PRE
110
–
125
10
140
–
Over-temperature Pre-Warning hysteresis(25)
Over-temperature Shutdown Temperature (Junction)(25)
Over-temperature Shutdown hysteresis(25)
T
°C
°C
°C
PRE_HYS
T
155
–
170
10
185
–
SD
T
SD_HYS
HALL SENSOR SUPPLY OUTPUT(26) (HVDD)
V
Voltage matching HVDDACC = (HVDD-VDD) / VDD * 100%
H
%
DD
VDDACC
IHVDD = 15mA
-2.0
20
–
2.0
50
Current Limitation
I
30
mA
mV
HVDD
Dropout Voltage
H
VDDDROP
IHVDD = 15mA; IVDD = 5mA
–
–
–
160
25
300
40
Line Regulation
LR
LD
mV
mV
HVDD
HVDD
IHVDD = 5mA; IVDD = 5mA
Load Regulation
1mA > IHVDD > 15mA; IVDD = 5mA
10
20
Notes
23. Specification with external capacitor 2µF < C < 100µF and 100mΩ ≤ ESR ≤ 10Ω.
24. Measured when voltage has dropped 250mV below its nominal Value (5V).
25. This parameter is guaranteed by process monitoring but, not production tested.
26. Specification with external capacitor 1µF < C < 10µF and 100mΩ ≤ ESR ≤ 10Ω.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
RST INPUT/OUTPUT PIN (RST)
Symbol
Min
Typ
Max
Unit
VDD Low Voltage Reset Threshold
VRSTTH
VOL
4.3
4.5
4.7
V
V
Low-State Output Voltage
IOUT = 1.5mA; 3.5V ≤ VSUP ≤ 27V
0.0
–
0.9
High-State Output Current (0 < VOUT < 3.5V)
IOH
-150
-250
-350
µA
Pull-down Current Limitation (internally limited)
VOUT = VDD
IPD_MAX
mA
1.5
-0.3
–
–
–
8.0
Low-State Input Voltage
High-State Input Voltage
MISO SPI OUTPUT PIN (MISO)
Low-State Output Voltage
VIL
VIH
0.3 x VDD
VDD + 0.3
V
V
0.7 x VDD
VOL
V
V
I
= 1.5mA
0.0
VDD - 0.9
-10
–
–
–
1.0
VDD
10
OUT
High-State Output Voltage
IOUT = -250µA
VOH
Tri-state Leakage Current
ITriMISO
µA
0 V ≤ VMISO ≤ VDD
SPI INPUT PINS (MOSI, SCLK, CS)
Low-state Input Voltage
VIL
VIH
IIN
-0.3
–
–
0.3 x VDD
VDD + 0.3
V
V
High-state Input Voltage
0.7 x VDD
MOSI, SCLK Input Current
µA
0 ≤ VIN ≤ VDD
-10
10
–
10
30
CS Pull-up current
0 < VIN < 3.5V
IPUCS
µA
20
INTERRUPT OUTPUT PIN (IRQ)
Low-state Output Voltage
IOUT = 1.5 mA
VOL
VOH
VOH
V
V
0.0
VDD - 0.8
–
–
–
–
0.8
VDD
2.0
High-state Output Voltage
IOUT = -250µA
Leakage current
mA
VDD ≤ VOUT ≤ 10V
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
Low-state Input Voltage
VIL
VIH
-0.3
–
–
0.3 x VDD
VDD + 0.3
V
V
High-state Input Voltage
0.7 x VDD
Pull-up current
0 < VIN < 3.5V
IPUPWMIN
µA
10
20
30
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
HIGH SIDE OUTPUT HS1 AND HS2 PINS (HS1, HS2)
Output Drain-to-Source On Resistance
TJ = 25°C, ILOAD = 50mA; VSUP > 9.0V
RDS(ON)
Ω
–
–
–
–
–
–
7.0
10
14
TJ = 150°C, ILOAD = 50mA; VSUP > 9.0V(27)
TJ = 150°C, ILOAD = 30mA; 5.5V < VSUP < 9.0V(27)
Output Current Limitation(28)
0V < VOUT < VSUP - 2.0V
ILIMHS1
mA
60
120
250
Open Load Current Detection(29)
IOLHSx
ILEAK
–
–
5.0
–
7.5
10
mA
µA
V
Leakage Current (-0.2V < VHSx < VS2 + 0.2V)
Short Circuit Detection Threshold(30)
5.5V < VSUP < 27V
VTHSC
VSUP - 2
–
–
Over-temperature Shutdown(31), (32)
Over-temperature Shutdown Hysteresis(32)
L1 INPUT PIN (L1)
THSSD
150
–
165
10
180
–
°C
°C
THSSD_HYS
Low Detection Threshold
5.5V < VSUP < 27V
VTHL
VTHH
VHYS
IIN
V
V
2.0
3.0
0.5
2.5
3.5
1.0
3.0
4.0
1.5
High Detection Threshold
5.5V < VSUP < 27V
Hysteresis
V
5.5V < VSUP < 27V
Input Current(33)
µA
kΩ
-0.2V < VIN < VS1
-10
–
10
–
Analog Input Impedance(34)
RL1IN
800
1550
Analog Input Divider Ratio (RATIOL1 = VL1 / VADOUT0
L1DS (L1 Divider Select) = 0
)
RATIOL1
0.95
3.42
1.0
3.6
1.05
3.78
L1DS (L1 Divider Select) = 1
Analog Output Offset Ratio
L1DS (L1 Divider Select) = 0
L1DS (L1 Divider Select) = 1
VRATIOL1-
mV
%
OFFSET
-80
-22
0.0
0.0
80
22
Analog Inputs Matching
L1MATCHING
L1DS (L1 Divider Select) = 0
L1DS (L1 Divider Select) = 1
96
96
100
100
104
104
Notes
27. This parameter is production tested up to TA = 125°C and guaranteed by process monitoring up to TJ = 150°C.
28. When over-current occurs, the high side stays ON with limited current capability and the HS1CL flag is set in the HSSR.
29. When open-load occurs, the flag (HS1OP) is set in the HSSR.
30. When short circuit occurs and if HVSE flag is enabled, HS1 automatic shutdown.
31. When over-temperature shutdown occurs, both High Sides are turned off. All flags in HSSR are set.
32. Guaranteed by characterization but, not production tested
33. Analog multiplexer input disconnected from L1 input pin.
34. Analog multiplexer input connected to L1 input pin.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
External Resistor Range
Symbol
Min
Typ
Max
Unit
R
20
–
–
200
15
kΩ
EXT
Watchdog Period Accuracy with External Resistor (Excluding Resistor
Accuracy)(35)
WD
-15
%
ACC
ANALOG MULTIPLEXER
Internal Chip Temperature Sense Gain
STTOV
–
10.5
5.25
–
mV/K
mV
VSENSE Input Divider Ratio (RATIOVSENSE = VVSENSE / VADOUT0
5.5V < VSUP < 27V
)
RATIOVSENSE
5.0
5.5
VSENSE Output Related Offset
-40°C < TA < -20°C
OFFSETVSENS
-30
-45
–
–
30
45
E
ANALOG OUTPUT (ADOUT0)
Maximum Output Voltage
-5mA < IO < 5mA
VOUT_MAX
V
V
VDD - 0.35
0.0
–
–
VDD
0.35
Minimum Output Voltage
-5mA < IO < 5mA
VOUT_MIN
RXD OUTPUT PIN (LIN PHYSICAL LAYER) (RXD)
Low-state Output Voltage
IOUT = 1.5 mA
VOL
V
V
0.0
–
–
0.8
High-state Output Voltage
IOUT = -250µA
VOH
VDD-0.8
VDD
TXD INPUT PIN (LIN PHYSICAL LAYER) (TXD)
Low-state Input Voltage
VIL
VIH
-0.3
0.7 x VDD
10
–
–
0.3 x nVDD
VDD + 0.3
30
V
V
High-state Input Voltage
Pin Pull-up Current, 0 < VIN < 3.5V
IPUIN
20
µA
Notes
35. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
LIN PHYSICAL LAYER, TRANSCEIVER (LIN)(36)
Output Current Limitation
IBUSLIM
mA
Dominant State, VBUS = 18V
40
120
–
200
–
Leakage Output Current to GND
Dominant State; VBUS = 0V; VBAT = 12V
IBUS_PAS_DOM
-1.0
mA
IBUS_PAS_REC
IBUS_NO_GND
–
-1.0
–
–
20
1.0
µA
mA
Recessive State; 8V < VBAT < 18V; 8V < VBUS < 18V; VBUS ≥ VBAT
GND Disconnected; GNDDEVICE = VSUP; VBAT = 12V; 0 < V
< 18V
BUS
IBUS
–
–
100
µA
V
disconnected; VSUP_DEVICE = GND; 0 < V
< 18V
BUS
BAT
Receiver Input Voltages
Receiver Dominant State
Receiver Recessive State
VSUP
VBUSDOM
VBUSREC
VBUS_CNT
VHYS
–
0.6
0.475
–
–
–
0.4
–
Receiver Threshold Center (VTH_DOM + VTH_REC)/2
Receiver Threshold Hysteresis (VTH_REC - VTH_DOM
0.5
–
0.525
0.175
)
LIN Transceiver Output Voltage
V
VLIN_REC
VLIN_DOM_0
VLIN_DOM_1
VSUP-1
Recessive State, TXD HIGH, I
= 1.0 µA
–
–
1.4
2
OUT
–
–
Dominant State, TXD LOW, 500Ω External Pull-up Resistor, LDVS =
0
1.1
1.7
Dominant State, TXD LOW, 500Ω External Pull-up Resistor, LDVS =
1
LIN Pull-up Resistor to V
SUP
RSLAVE
TLINSD
20
150
–
30
165
10
60
180
–
kΩ
°C
°C
Over-temperature Shutdown(37)
Over-temperature Shutdown Hysteresis
TLINSD_HYS
Notes
36. Parameters guaranteed for 7.0V ≤ VSUP ≤ 18V.
37. When Over-temperature shutdown occurs, the LIN bus goes in recessive state and the flag LINOT in LINSR is set.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
SPI INTERFACE TIMING (Figure 13)
Symbol
Min
Typ
Max
Unit
SPI Operating Frequency
f
t
–
–
–
–
–
–
–
–
–
4.0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MHz
ns
SPIOP
SCLK Clock Period
250
110
110
100
100
40
CLK
PS
SCLK Clock High Time(38)
t
ns
SCLKH
W
SCLK Clock Low Time(38)
t
ns
SCLKL
W
Falling Edge of CS to Rising Edge of SCLK(38)
Falling Edge of SCLK to CS Rising Edge(38)
MOSI to Falling Edge of SCLK(38)
Falling Edge of SCLK to MOSI(38)
MISO Rise Time(38)
t
ns
LEAD
tLAG
ns
t
ns
SISU
t
40
ns
SIH
tRSO
ns
C
= 220pF
–
–
40
40
–
–
L
MISO Fall Time(38)
= 220pF
t
ns
ns
FSO
C
L
Time from Falling or Rising Edges of CS to:(38)
- MISO Low-impedance
t
0.0
0.0
–
–
50
50
SOEN
- MISO High-impedance
t
SODIS
Time from Rising Edge of SCLK to MISO Data Valid(38)
t
ns
VALID
0.2 x VDD ≤ MISO ≥ 0.8 x VDD, CL = 100pF
0.0
–
75
RST OUTPUT PIN
Reset Low-level Duration after VDD High (See Figure 12, page 19)
Reset Deglitch Filter Time
t
0.65
350
1.0
1.35
900
ms
ns
RST
t
600
RSTDF
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period(39)
t
ms
PWD
External Resistor REXT = 20kΩ (1%)
External Resistor REXT = 200kΩ (1%)
Without External Resistor REXT (WDCONF Pin Open)
8.5
79
10
94
11.5
108
205
110
150
Notes
38. This parameter is guaranteed by process monitoring but, not production tested.
39. Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ)
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
L1 INPUT
Wake-up Filter Time
STATE MACHINE TIMING
t
8.0
20
38
µs
WUF
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation(40)
tSTOP
µs
–
–
5.0
Normal Request Mode Timeout (see Figure 12, page 19)
t
110
150
205
ms
NRTOUT
Delay Between SPI Command and HS Turn On(41)
9V < VSUP < 27V
tS-
µs
ON
–
–
–
–
–
–
10
10
10
Delay Between SPI Command and HS Turn Off(41)
9V < VSUP < 27V
tS-OFF
µs
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)(40)
tSNR2N
µs
µs
Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
First Accepted SPI Command
tWUCS
tWUSPI
9.0
90
15
—
80
N/A
Minimum Time Between Rising and Falling Edge on the CS
t2CS
4.0
—
—
µs
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0KBIT/SEC(42), (43)
Duty Cycle 1: D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50µs
D1
7.0V ≤ VSUP ≤ 18V
0.396
—
—
—
Duty Cycle 2: D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50µs
D2
7.6V ≤ VSUP ≤ 18V
—
0.581
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4KBIT/SEC(42),(44)
Duty Cycle 3: D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96µs
D3
µs
µs
7.0V ≤ VSUP ≤ 18V
0.417
—
—
—
—
Duty Cycle 4: D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96µs
D4
7.6V ≤ VSUP ≤ 18V
0.590
Notes
40. This parameter is guaranteed by process monitoring but, not production tested.
41. Delay between turn on or off command (rising edge on CS) and HS ON or OFF, excluding rise or fall time due to external load.
42. Bus load RBUS and CBUS 1.0nF / 1.0kΩ, 6.8nF / 660Ω, 10nF / 500Ω. Measurement thresholds: 50% of TXD signal to LIN signal threshold
defined at each parameter. See Figure 6, page 17.
43. See Figure 7, page 17.
44. See Figure 8, page 17.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C for the 33910 and -40°C ≤ TA ≤ 85°C for the
34910, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
V/µs
µs
LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR FAST SLEW RATE
LIN Fast Slew Rate (Programming Mode)
SR
—
20
—
FAST
LIN PHYSICAL LAYER: CHARACTERISTICS AND WAKE-UP TIMINGS(45)
Propagation Delay and Symmetry(46)
tREC_PD
Propagation Delay Receiver, tREC_PD=max (tREC_PDR, tREC_PDF
Symmetry of Receiver Propagation Delay tREC_PDF - tREC_PDR
)
—
3.0
—
6.0
2.0
tREC_SYM
-2.0
Bus Wake-up Deglitcher (Sleep and Stop Modes)(47)
tPROPWL
42
70
95
µs
µs
Bus Wake-up Event Reported
From Sleep Mode(48)
tWAKE
tWAKE
—
—
1500
17
From Stop Mode(49)
9.0
13
TXD Permanent Dominant State Delay
tTXDDOM
0.65
1.0
1.35
s
PULSE WIDTH MODULATION INPUT PIN (PWMIN)
PWMIN pin(50)
fPWMIN
kHz
Max. frequency to drive HS output pins
10
Notes
45. VSUP from 7.0V to 18V, bus load RBUS and CBUS 1.0nF / 1.0kΩ, 6.8nF / 660Ω, 10 nF / 500Ω. Measurement thresholds: 50% of TXD
signal to LIN signal threshold defined at each parameter. See Figure 6, page 17.
46. See Figure 9, page 18
47. See Figure 10, page 18 for Sleep and Figure 11, page 19 for Stop Mode.
48. The measurement is done with 1µF capacitor and 0mA current load on VDD. The value takes into account the delay to charge the
capacitor. The delay is measured between the bus wake-up threshold (VBUSWU) rising edge of the LIN bus and when V reaches 3.0 V.
DD
See Figure 10, page 18. The delay depends of the load and capacitor on VDD
.
49. In Stop Mode, the delay is measured between the bus wake-up threshold (VBUSWU) and the falling edge of the IRQ pin. See Figure 11,
page 18.
50. This parameter is guaranteed by process monitoring but, not production tested.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
33910
TRANSIENT PULSE
GENERATOR
1.0nF
LIN
(
NOTE
)
GND
PGND LGND AGND
NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 4. Test Circuit for Transient Test Pulses (LIN)
33910
TRANSIENT PULSE
GENERATOR
(NOTE)
1.0nF
L1
10kΩ
GND
PGND LGND AGND
NOTE: Waveform Per ISO 7637-2. Test Pulses 1, 2, 3a, 3b.
Figure 5. Test Circuit for Transient Test Pulses (L1)
VSUP
R0
LIN
TXD
RXD
R0 AND C0 COMBINATIONS:
• 1.0KΩ and 1.0nF
• 660Ω and 6.8nF
• 500Ω and 10nF
C0
Figure 6. Test Circuit for LIN Timing Measurements
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TXD
t
t
BIT
BIT
t
(MAX)
t
(MIN)
BUS_REC
BUS_DOM
VLIN_REC
t
- MAX
t
- MIN
REC
DOM
74.4% V
60.0% V
SUP
SUP
t
- MIN
DOM
LIN
58.1% V
40.0% V
58.1% V
40.0% V
SUP
SUP
SUP
SUP
28.4% V
SUP
28.4% V
SUP
42.2% V
SUP
t
- MIN
REC
t
- MAX
t
(MIN)
BUS_DOM
DOM
t
(MAX)
BUS_REC
RXD
t
t
RREC
RDOM
Figure 7. LIN Timing Measurements for Normal Slew Rate
TXD
t
t
BIT
BIT
t
(MAX)
t
(MIN)
BUS_REC
BUS_DOM
VLIN_REC
t
- MAX
t
- MIN
REC
DOM
77.8% V
60.0% V
SUP
SUP
t
- MIN
DOM
LIN
61.6% V
40.0% V
61.6% V
40.0% V
SUP
SUP
SUP
SUP
25.1% V
SUP
25.1% V
SUP
38.9% V
SUP
t
- MIN
REC
t
- MAX
t
(MIN)
BUS_DOM
DOM
t
(MAX)
BUS_REC
RXD
t
t
RREC
RDOM
Figure 8. LIN Timing Measurements for Slow Slew Rate
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
VLIN_REC
V
BUSrec
V
SUP
LIN BUS SIGNAL
V
BUSdom
RXD
t
RX_PDF
t
RX_PDR
Figure 9. LIN Receiver Timing
V
LIN_REC
LIN
0.4 V
SUP
DOMINANT LEVEL
VDD
t
WL
t
WAKE
PROP
Figure 10. LIN Wake-up Sleep Mode Timing
V
LIN_REC
LIN
0.4 V
SUP
DOMINANT LEVEL
IRQ
t
WL
t
WAKE
PROP
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
Figure 11. LIN Wake-up Stop Mode Timing
V
SUP
V
DD
RST
t
NRTOUT
t
RST
Figure 12. Power On Reset and Normal Request Time-Out Timing
t
PSCLK
CS
t
t
WSCLKH
LEAD
t
LAG
SCLK
t
WSCLKL
t
t
SIH
SISU
MOSI
MISO
UNDEFINED
D0
DON’T CARE
D7
DON’T CARE
t
VALID
t
SODIS
t
SOEN
D0
D7
DON’T CARE
Figure 13. SPI Timing Characteristics
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33910 is designed and developed as a highly
integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
33910 is well suited to perform keypad applications via the
LIN bus.
include a wake-up capable pin amd a Hall Sensor port
supply. An internal voltage regulator provides power to a
MCU device.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables this device
to be compatible with 3-wire bus systems, where one wire is
used for communication, one for battery, and one for ground.
Two power switches are provided on the device configured
as high side outputs. Other ports are also provided, which
FUNCTIONAL PIN DESCRIPTION
See Table 1, 33910 Simplified Application Diagram,
page 1, for a graphic representation of the various pins
referred to in the following paragraphs. Also, see the pin
diagram on page 3 for a description of the pin locations in the
package.
microcontroller. Data on this output pin changes on the
negative edge of the SCLK. When CS is High, this pin will
remain in high-impedance state.
CHIP SELECT (CS)
CS is a active low digital input. It must remain low during a
valid SPI communication and allow for several devices to be
connected in the same SPI bus without contention. A rising
edge on CS signals the end of the transmission and the
moment the data shifted in is latched. A valid transmission
must consist of 8 bits only.
RECEIVER OUTPUT (RXD)
The RXD pin is a digital output. It is the receiver output of
the LIN interface and reports the state of the bus voltage:
RXD low when LIN bus is dominant, RXD high when LIN bus
is recessive.
While in STOP Mode a low-to-high level transition on this
pin will generate a wake-up condition for the 33910.
TRANSMITTER INPUT (TXD)
The TXD pin is a digital input. It is the transmitter input of
the LIN interface and controls the state of the bus output
(dominant when TXD is Low, recessive when TXD is High).
ANALOG MULTIPLEXER (ADOUT0)
The ADOUT0 pin can be configured via the SPI to allow
the MCU A/D converter to read the several inputs of the
Analog Multiplexer, including the L1 input voltage and the
internal junction temperature.
This pin has an internal pull-up to force recessive state in
case the input is left floating.
LIN BUS (LIN)
PWM INPUT CONTROL (PWMIN)
The LIN pin represents the single-wire bus transmitter and
receiver. It is suited for automotive bus systems and is
compliant to the LIN bus specification 2.0.
This digital input can control the high sides in Normal
Request and Normal Mode.
The LIN interface is only active during Normal and Normal
Request Modes.
To enable PWM control, the MCU must perform a write
operation to the high side control register (HSCR).
This pin has an internal 20uA current pull-up.
SERIAL DATA CLOCK (SCLK)
RESET (RST)
The SCLK pin is the SPI clock input pin. MISO data
changes on the negative transition of the SCLK. MOSI is
sampled on the positive edge of the SCLK.
This bidirectional pin is used to reset the MCU in case the
33910 detects a reset condition or to inform the 33910 that
the MCU has just been reset. After release of the RST pin
Normal Request Mode is entered.
MASTER OUT SLAVE IN (MOSI)
The MOSI digital pin receives SPI data from the MCU. This
data input is sampled on the positive edge of SCLK.
The RST pin is an active low filtered input and output
formed by a weak pull-up and a switchable pull-down
structure which allows this pin to be shorted either to VDD or
to GND during software development without the risk of
destroying the driver.
MASTER IN SLAVE OUT (MISO)
The MISO pin sends data to an SPI-enabled MCU. It is a
digital tri-state output used to shift serial data to the
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
INTERRUPT (IRQ)
HIGH SIDE OUTPUTS (HS1 AND HS2)
The IRQ pin is a digital output used to signal events or
faults to the MCU while in Normal and Normal Request Mode
or to signal a wake-up from Stop Mode. This active low output
will transition to high, only after the interrupt is acknowledged
by a SPI read of the respective status bits.
These high side switches are able to drive loads such as
relays or lamps. Their structure is connected to the VS2
supply pin. The pins are short-circuit protected and also
protected against overheating.
HS1and HS2 are controlled by SPI and can respond to a
signal applied to the PWMIN input pin.
WATCHDOG CONFIGURATION (WDCONF)
The HS1 and HS2 outputs can also be used during Low
Power Mode for the cyclic-sense of the wake input.
The WDCONF pin is the configuration pin for the internal
watchdog. A resistor can be connected to this pin to configure
the window watchdog period. When connected directly to
ground, the watchdog will be disabled. When this pin is left
open, the watchdog period is fixed to its lower precision
internal default value (150ms typical).
POWER SUPPLY (VS1 AND VS2)
Those are the battery level voltage supply pins. In an
application, VS1 and VS2 pins must be protected against
reverse battery connection and negative transient voltages,
with external components. These pins sustain standard
automotive voltage conditions such as load dump at 40V.
GROUND CONNECTION (AGND, PGND, LGND)
The AGND, PGND and LGND pins are the Analog and
Power ground pins.
The high side switches (HS1 and HS2) are supplied by the
VS2 pin, all other internal blocks are supplied by VS1 pin.
The AGND pin is the ground reference of the voltage
regulator.
VOLTAGE SENSE PIN (VSENSE)
The PGND and LGND pins are used for high current load
return as in the LIN interface pin.
This input can be connected directly to the battery line. It
is protected against battery reverse connection. The voltage
present in this input is scaled down by an internal voltage
divider, and can be routed to the ADOUT0 output pin and
used by the MCU to read the battery voltage.
Note: PGND, AGND and LGND pins must be connected
together.
DIGITAL/ANALOG (L1)
The ESD structure on this pin allows for excursion up to
+40V and down to -27V, allowing this pin to be connected
directly to the battery line. It is strongly recommended to
connect a 10kohm resistor in series with this pin for protection
purposes.
The L1 pin is a multi purpose input. It can be used as a
digital input, which can be sampled by reading the SPI and
used for wake-up when 33910 is in Low Power Mode or used
as analog inputs for the analog multiplexer. When used to
sense voltage outside the module, a 33kohm series resistor
must be used on each input.
HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)
When used as a wake-up input L1 can be configured to
operate in Cyclic-Sense Mode. In this mode, one of the high
side switches is configured to be periodically turned on and
sample the wake-up input. If a state change is detected
between two cycles a wake-up is initiated. The 33910 can
also wake-up from Stop or Sleep by a simple state change on
L1.
This pin provides a switchable supply for external hall
sensors. While in Normal Mode, this current limited output
can be controlled through the SPI.
The HVDD pin needs to be connected to an external
capacitor to stabilize the regulated output voltage.
+5V MAIN REGULATOR OUTPUT (VDD)
When used as analog input, the voltage present on the L1
pins is scaled down by an selectable internal voltage divider
and can be routed to the ADOUT0 output through the analog
multiplexer.
An external capacitor has to be placed on the VDD pin to
stabilize the regulated output voltage. The VDD pin is
intended to supply a microcontroller. The pin is current limited
against shorts to GND and over-temperature protected.
Note: If L1 input is selected in the analog multiplexer, it will
be disabled as digital input and remains disabled in low
Power Mode. No wake-up feature is available in that
condition.
During Stop Mode the voltage regulator does not operate
with its full drive capabilities and the output current is limited.
During Sleep Mode the regulator output is completely shut
down.
When the L1 input is not selected in the analog
multiplexer, the voltage divider is disconnected from that
input.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33910 - Functional Block Diagram
Integrated Supply
Hall Sensor Supply
HVDD
Voltage Regulator
VDD
Analog Circuitry
Window Watchdog
Wake-Up
High Side Drivers
HS1 - HS2
Digital / Analog Input
LIN Physical Layer
Interface
Voltage & Temperature Sense
MCU Interface and Output Control
Reset & IRQ Logic
HS - PWM Control
LIN Interface / Control
Analog Output 0
Integrated Supply
Analog Circuitry
MCU Interface and Output Control
Drivers
Figure 14. Functional Internal Block Diagram
as over-current conditions in any of the driver stages can be
reported to the connected MCU via IRQ or RST. The High
Side driver outputs can be controlled via the SPI register as
well as the PWMIN input. The integrated LIN physical layer
interface can be configured via SPI register and its
communication is driven through the RXD and TXD device
pins. All internal analog sources are multiplexed to the
ADOUT0 pin.
ANALOG CIRCUITRY
The 33910 is designed to operate under automotive
operating conditions. A fully configurable window watchdog
circuit will reset the connected MCU in case of an overflow.
Two low power modes are available with several different
wake-up sources to reactivate the device. One analog / digital
input can be sensed or used as the wake-up source. The
device is capable of sensing the supply voltage (VSENSE)
and the internal chip temperature (CTEMP).
VOLTAGE REGULATOR OUTPUTS
Two independent voltage regulators are implemented on
the 33910. The VDD main regulator output is designed to
supply a MCU with a precise 5V. The switchable HVDD
output is dedicated to supply small peripherals as hall
sensors.
HIGH SIDE DRIVERS
Two current and temperature protected High Side drivers
with PWM capability are provided to drive small loads such as
Status LED’s or small lamps. Both Drivers can be configured
for periodic sense during low power modes.
LIN PHYSICAL LAYER INTERFACE
MCU INTERFACE
The 33910 provides a LIN 2.0 compatible LIN physical
layer interface with selectable slew rate and various
diagnostic features.
The 33910 is providing its control and status information
through a standard 8-Bit SPI interface. Critical system events
such as Low- or High-voltage/Temperature conditions as well
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
INTRODUCTION
NORMAL MODE
The 33910 offers three main operating modes: Normal
(Run), Stop, and Sleep (Low Power). In Normal Mode the
device is active and is operating under normal application
conditions. The Stop and Sleep Modes are low power modes
with wake-up capabilities.
In Normal Mode, all 33910 functions are active and can be
controlled by the SPI and the PWMIN pin.
The VDD regulator is ON and delivers its full current
capability.
If an external resistor is connected between the WDCONF
pin and the Ground, the window watchdog function will be
enabled.
In Stop Mode the voltage regulator still supplies the MCU
with VDD (limited current capability) and in Sleep Mode the
voltage regulator is turned off (VDD = 0 V).
The wake-up input (L1) can be read as a digital input or
have its voltage routed through the analog-multiplexer.
Wake-up from Stop Mode is initiated by a wake-up
interrupt. Wake-up from Sleep Mode is done by a reset and
the voltage regulator is turned back on.
The LIN interface has slew rate and timing compatible with
the LIN protocol specification 2.0. The LIN bus can transmit
and receive information.
The selection of the different modes is controlled by the
MOD1:2 bits in the mode control register (MCR).
The high side switches are active and have PWM
capability according to the SPI configuration.
Figure 15 describes how transitions are done between the
different operating modes and Table 5, 25, gives an overview
of the Operating Mode.
The interrupts are generated to report failures 5 for VSUP
over/under-voltage, thermal shutdown or thermal shutdown
prewarning on the main regulator.
RESET MODE
The 33910 enters the Reset Mode after a power up. In this
mode, the RST pin is low for 1ms (typical value). After this
delay, the 33910 enters the Normal Request Mode and the
RST pin is driven high.
SLEEP MODE
The Sleep Mode is a low power mode. From Normal
Mode, the device enters the Sleep Mode by sending one SPI
command through the MCR. All blocks are in their lowest
power consumption condition. Only some wake-up sources
(wake-up input with or without cyclic sense, forced wake-up
and LIN receiver) are active. The 5V regulator is OFF. The
internal low-power oscillator may be active if the IC is
configured for cyclic-sense. In this condition, one of the high
side switches is turned on periodically and the wake-up
inputs are sampled.
The Reset Mode is entered if a reset condition occurs (VDD
low, watchdog trigger fail, after a wake-up from Sleep Mode,
Normal Request Mode time-out occurs).
NORMAL REQUEST MODE
This is a temporary mode automatically accessed by the
device after the Reset Mode or after a wake-up from Stop
Mode.
Wake-up from Sleep Mode is similar to a power-up. The
device goes in Reset Mode except that the SPI will report the
wake-up source and the BATFAIL flag is not set.
In Normal Request Mode, the VDD regulator is ON, the
Reset pin is high and the LIN is operating in Rx Only Mode.
As soon as the device enters the Normal Request Mode
an internal timer is started for 150ms (typical value). During
these 150ms, the MCU must configure the timing control
register (TIMCR) and the MCR with MOD2 and MOD1 bits
ste = 0 to enter in Normal Mode. If within the 150ms timeout
the MCU does not command the 33910 to Normal Mode, it
will enter in Reset Mode. If the WDCONF pin is grounded in
order to disable the watchdog function, the 33910 goes
directly in Normal Mode after the Reset Mode. If the
WDCONF pin is open, the 33910 stays typically for 150ms in
Normal Request before entering in Normal Mode.
STOP MODE
The Stop Mode is the second low power mode, but in this
case the 5V regulator is ON with limited current drive
capability. The application MCU is always supplied while the
33910 is operating in Stop Mode.
The device can enter in Stop Mode only by sending the
SPI command. When the application is in this mode, it can
wake-up from the 33910 side (for example: cyclic sense,
force wake-up, LIN bus, wake inputs) or the MCU side (CS,
RST pins). Wake-up from Stop Mode will transition the 33910
to Normal Request Mode and generates an interrupt except
if the wake-up event is a low to high transition on the CS pin
or comes from the RST pin.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Normal Request Timeout Expired (t
)
NRTOUT
V
LOW
DD
V
HIGH AND
DD
Power Up
RESET DELAY (tRST) EXPIRED
POWER
DOWN
NORMAL
REQUEST
RESET
V
LOW
DD
NORMAL
WD FAILED
V
LOW (>t ) EXPIRED
NRTOUT
DD
AND VSUV = 0
SLEEP COMMAND
WAKE-UP (RESET)
STOP
SLEEP
V
LOW
DD
Legend
WD: Watchdog
WD Disabled: Watchdog disabled (WDCONF pin connected to GND)
WD Trigger: Watchdog is triggered by SPI command
WD Failed: No watchdog trigger or trigger occurs in closed window
Stop Command: Stop command sent via the SPI
Sleep Command: Sleep command sent via the SPI
Wake-up from Stop Mode: L1 state change, LIN bus wake-up, Periodic wake-up, CS rising edge wake-up or RST wake-up.
Wake-up from Sleep Mode: L1 state change, LIN bus wake-up, Periodic wake-up.
Figure 15. Operating Modes and Transitions
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Table 5. Operating Modes Overview
Normal
Mode
Function
Reset Mode Normal Request Mode
Stop Mode
Sleep Mode
VDD
HVDD
full
full
SPI(51)
full
SPI
stop
-
-
-
-
HSx
-
SPI/PWM(52)
SPI
SPI/PWM
SPI
Note(53)
-
Note(54)
-
Analog Mux
L1
-
-
Input
Input
Wake-up
Wake-up
LIN
-
Rx-Only
full/Rx-Only Rx-Only/Wake-up Wake-up
Watchdog
VSENSE
Notes
-
150ms (typ.) timeout
On
On(55)/Off
On
-
-
-
On
VDD
51. Operation can be enabled/controlled by the SPI.
52. Operation can be controlled by the PWMIN input.
53. HSx switches can be configured for cyclic sense operation in Stop Mode.
54. HSx switches can be configured for cyclic sense operation in Sleep Mode.
55. Windowing operation when enabled by an external resistor.
Over-Temperature Prewarning
INTERRUPTS
Interrupts are used to signal a microcontroller that a
peripheral needs to be serviced. The interrupts which can be
generated change according to the Operating Mode. While in
Normal and Normal Request modes the 33910 signals
through interrupts special conditions which may require a
MCU software action. Interrupts are not generated until all
pending wake-up sources are read in the interrupt source
register (ISR).
Signals when the 33910 temperature has reached the pre-
shutdown warning threshold. It is used to warn the MCU that
an over-temperature shutdown in the main 5V regulator is
imminent.
LIN Over-Current Shutdown / Over-Temperature
Shutdown / TXD Stuck At Dominant / RXD Short-Circuit
These signal faulty conditions in the LIN interface (except
the LIN over-current) that had led to disable the LIN driver. In
order to restart operation, the fault must be removed and
must be acknowledged by reading the SPI.
While in Stop Mode, interrupts are used to signal wake-up
events. Sleep Mode does not use interrupts, wake-up is
performed by powering-up the MCU. In Normal and Normal
Request Mode the wake-up source can be read by SPI.
The LINOC bit functionality in the LIN status register
(LINSR) is to indicate that an LIN over-current occurred and
the driver stays enabled.
The interrupts are signaled to the MCU by a low logic level
of the IRQ pin, which will remain low until the interrupt is
acknowledged by a SPI read. The IRQ pin will then be driven
high.
High Side Over-Temperature Shutdown
Interrupts are only asserted while in Normal-, Normal
Request and Stop Mode. Interrupts are not generated while
the RST pin is low.
Signals a shutdown of the high side outputs.
RESET
Following is a list of the interrupt sources in Normal and
Normal Request Modes, some of those can be masked by
writing to the SPI-interrupt mask register (IMR).
To reset an MCU, the 33910 drives the RST pin low for the
time the reset condition lasts.
After the reset source has been removed the state
machine will drive the RST output low for at least 1ms typical
value before driving it high.
Low Voltage Interrupt
Signals when the supply line (VS1) voltage drops below
the VSUV threshold (VSUV).
In the 33910 four main reset sources exist:
5V Regulator Low-Voltage-Reset (VRSTTH
)
High Voltage Interrupt
The 5V regulator output VDD is continuously monitored
against brown outs. If the supply monitor detects that the
voltage at the VDD pin has dropped below the reset threshold
VRSTTH the 33910 will issue a reset. In case of over-
Signals when the supply line (VS1) voltage increases
above the VSOV threshold (VSOV).
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
temperature, the voltage regulator will be disabled and the
voltage monitoring will issue a VDDOT Flag independently of
the VDD voltage.
from an internal timer. Cyclic sense and force wake-up are
exclusive. If cyclic sense is enabled, the force wake-up can
not be enabled.
In order to select and activate the cyclic sense wake-up
from the L1 input, before entering in low power modes (Stop
or Sleep Modes), the following SPI set-up has to be
performed:
Window Watchdog Overflow
If the watchdog counter is not properly serviced while its
window is open, the 33910 will detect a MCU software
runaway and will reset the microcontroller.
• In WUCR: select the L1 input to WU-enable.
• In HSCR: enable HSx.
• In TIMCR: select the CS/WD bit and determine the
cyclic sense period with CYSTx bits.
Wake-up From Sleep Mode
During Sleep Mode, the 5V regulator is not active, hence
all wake-up requests from Sleep Mode require a power-up/
reset sequence.
• Perform Goto Sleep/Stop command.
Forced Wake-up
External Reset
The 33910 can wake-up automatically after a
predetermined time spent in Sleep or Stop Mode. Cyclic
sense and forced wake-up are exclusive. If forced wake-up is
enabled, the cyclic sense can not be enabled.
The 33910 has a bidirectional reset pin which drives the
device to a safe state (same as Reset Mode) for as long as
this pin is held low. The RST pin must be held low long
enough to pass the internal glitch filter and get recognized by
the internal reset circuit. This functionality is also active in
Stop Mode.
To determine the wake-up period, the following SPI set-up
has to be sent before entering in Low Power Modes:
• In TIMCR: select the CS/WD bit and determine the Low
Power Mode period with CYSTx bits.
• In HSCR: the HSx bit must be disabled.
After the RST pin is released, there is no extra tRST to be
considered.
WAKE-UP CAPABILITIES
CS Wake-up
Once entered in to one of the low-power modes (Sleep or
Stop) only wake-up sources can bring the device into Normal
Mode operation.
While in Stop Mode, a rising edge on the CS will cause a
wake-up. The CS wake-up does not generate an interrupt
and is not reported on SPI.
In Stop Mode, a wake-up is signaled to the MCU as an
interrupt, while in Sleep Mode the wake-up is performed by
activating the 5V regulator and resetting the MCU. In both
cases the MCU can detect the wake-up source by accessing
the SPI registers. There is no specific SPI register bit to signal
a CS wake-up or external reset. If necessary this condition is
detected by excluding all other possible wake-up sources.
LIN Wake-up
While in the low power modes the 33910 monitors the
activity on the LIN bus. A dominant pulse larger than tPROPWL
followed by a dominant to recessive transition will cause a
LIN wake-up. This behavior protects the system from a short-
to-ground bus condition.
Wake-up From Wake-up Input (L1) With Cyclic Sense
Disabled
RST Wake-up
While in Stop Mode, the 33910 can wake-up when the
RST pin is held low long enough to pass the internal glitch
filter. Then, the 33910 will change to Normal Request or
Normal modes depending on the WDCONF pin
configuration. The RST wake-up does not generate an
interrupt and is not reported via SPI.
The wake-up line is dedicated to sense state changes of
external switches and wake-up the MCU (in Sleep or Stop
Mode).
In order to select and activate direct wake-up from the L1
input, the wake-up control register (WUCR) must be
configured with L1WE input enabled. The wake-up input
state is read through the wake-up status register (WUSR).
From Stop Mode, the following wake-up events can be
configured:
L1 input is also used to perform cyclic-sense wake-up.
• Wake-up from L1 input without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
Note: Selecting the L1 input in the analog multiplexer
before entering Low Power Mode will disable the wake-up
capability of the L1 input.
• CS wake-up
• LIN wake-up
• RST wake-up
Wake-up From Wake-up Input (L1) With Cyclic Sense
Timer Enabled
From Sleep Mode, the following wake-up events can be
configured:
The SBCLIN can wake-up at the end of a cyclic sense
period if on the wake-up input lines (L1) a state change
occurs. The HSx switch is activated in Sleep or Stop Modes
• Wake-up from L1 input without cyclic sense
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
• Cyclic sense wake-up inputs
• Force wake-up
• LIN wake-up
effectively disables Normal Request Mode. The WDOFF bit
in the WDSR will be set. This condition is only detected
during Reset Mode.
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150ms (typ.) and signals the faulty condition
through the WDSR.
WINDOW WATCHDOG
The 33910 includes a configurable window watchdog
which is active in Normal Mode. The watchdog can be
configured by an external resistor connected to the WDCONF
pin. The resistor is used to achieve higher precision in the
timebase used for the watchdog.
The watchdog timebase can be further divided by a
prescaler which can be configured by the TIMCR. During
Normal Request Mode, the window watchdog is not active
but there is a 150ms (typ.) timeout for leaving the Normal
Request Mode. In case of a timeout, the 33910 will enter into
Reset Mode, resetting the microcontroller before entering
again into Normal Request Mode.
SPI clears are performed by writing through the SPI in the
MOD bits of the MCR.
During the first half of the SPI timeout watchdog clears are
not allowed; but after the first half of the PSPI-timeout window
the clear operation opens. If a clear operation is performed
outside the window, the 33910 will reset the MCU, in the
same way as when the watchdog overflows.
HIGH SIDE OUTPUT PINS HS1 AND HS2
These outputs are two high side drivers intended to drive
small resistive loads or LEDs incorporating the following
features:
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WINDOW OPEN
FOR WATCHDOG
CLEAR
• PWM capability (software maskable)
• Open load detection
• Current limitation
• Over-temperature shutdown (with maskable interrupt)
• High-voltage shutdown (software maskable)
• Cyclic sense
WD TIMING X 50%
WD TIMING X 50%
The high side switches are controlled by the bits HS1:2 in
the High Side Control Register (HSCR).
PWM Capability (direct access)
WD PERIOD (t
)
PWD
Each high side driver offers additional (to the SPI control)
direct control via the PWMIN pin.
WD TIMING SELECTED BY REGISTER
ON WDCONF PIN
If both the bits HS1 and PWMHS1 are set in the High Side
Control Register (HSCR), then the HS1 driver is turned on if
the PWMIN pin is high and turned of if the PWMIN pin is low.
This applies to HS2 configuring HS2 and PWMHS2 bits.
Figure 16. Window Watchdog Operation
To disable the watchdog function in Normal Mode the user
must connect the WDCONF pin to ground. This measure
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
Interrupt
Control
VDD
HVSE
VDD
Module
PWMIN
PWMHSx
VS2
MOD1:2
High Side - Driver
charge pump
open load detection
current limitation
on/off
HSx
Control
HSxOP
Status
overtemperture shutdown (interrupt maskable)
high voltage shutdown (maskable)
HSxCL
HSx
Wakeup
Module
Figure 17. High Side Drivers HS1 and HS2
Open Load Detection
Interrupt Control Module. The shutdown is indicated as HS
Interrupt in the Interrupt Source Register (ISR).
Each high side driver signals an open load condition if the
current through the high side is below the open load current
threshold.
A thermal shutdown of the high side drivers is indicated by
setting all HSxOP and HSxCL bits simultaneously.
If the bit HSM is set in the Interrupt Mask Register (IMR),
then an interrupt (IRQ) is generated.
The open load condition is indicated with the bits HS1OP
and HS2OP in the High Side Status Register (HSSR).
A write to the High Side Control Register (HSCR), when
the over-temperature condition is gone, will re-enable the
high side drivers.
Current Limitation
Each high side driver has an output current limitation. In
combination with the over-temperature shutdown the high-
side drivers are protected against over-current and short-
circuit failures.
High-voltage Shutdown
In case of a high voltage condition and if the high voltage
shutdown is enabled (bit HVSE in the Mode Control Register
(MCR) is set) both high side drivers are shut down.
When the driver operates in the current limitation area, it is
indicated with the bits HS1CL and HS2CL in the HSSR.
A write to the High Side Control Register (HSCR), when
the high voltage condition is gone, will re-enable the high side
drivers.
Note: If the driver is operating in current limitation mode,
excessive power might be dissipated.
Over-temperature Protection (HS Interrupt)
Sleep And Stop Mode
Both high side drivers are protected against over-
temperature. In case of an over-temperature condition both
high side drivers are shut down and the event is latched in the
The high side driver can be enabled to operate in Sleep
and Stop Mode for cyclic sensing. Also see Table 5,
Operating Modes Overview.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
• LIN dominant voltage level selection
LIN PHYSICAL LAYER
The LIN driver is a low side MOSFET with over-current
and thermal shutdown. An internal pull-up resistor with a
serial diode structure is integrated, so no external pull-up
components are required for the application in a Slave Mode.
The fall time from dominant to recessive and the rise time
from recessive to dominant is controlled. The symmetry
between both slopes is guaranteed.
The LIN bus pin provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification
and has the following features:
• LIN physical layer 2.0 compliant
• Slew rate selection
• Over-current shutdown
• Over-temperature shutdown
• LIN pull-up disable in Stop and Sleep Modes
• Advanced diagnostics
LIN Pin
The LIN pin offers a high susceptibility immunity level from
external disturbance, guaranteeing communication.
INTERRUPT
CONTROL
MODULE
WAKE-UP
MODULE
High-voltage
Shutdown
High Side
Interrupt
LIN
Wake-up
MOD1:2
LSR0:1
LINPE
VS1
LIN – DRIVER
LDVS
Slope and Slew Rate Control
Over-current Shutdown (interrupt maskable)
Over-temperature Shutdown (interrupt maskable)
RXONLY
RXSHORT
TXDOM
LINOT
LINOC
30K
LIN
TXD
RXD
SLOPE
CONTROL
LGND
WAKE-UP
FILTER
RECEIVER
Figure 18. LIN Interface
Slew Rate Selection
Mode the internal pull-up resistor on the LIN pin can be
disconnected by clearing the LINPE bit in the MCR. The bit
LINPE also changes the bus wake-up threshold (VBUSWU).
The slew rate can be selected for optimized operation at
10.4 and 20kBit/s as well as a fast baud rate for test and
programming. The slew rate can be adapted with the bits
LSR1:0 in the LIN control register (LINCR). The initial slew
rate is optimized for 20kBit/s.
In case of a LIN bus short to GND, this feature will reduce
the current consumption in Stop and Sleep modes.
Over-Current Shutdown (LIN Interrupt)
LIN Pull-up Disable In Stop and Sleep Mode
The output low side FET is protected against over-current
conditions. In case of an over-current condition (e.g. LIN bus
To improve performance and for safe behavior in case of
LIN bus short to ground or LIN bus leakage during Low Power
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
short to VBAT), the transmitter will not be shut down. The bit
LINOC in the LIN status register (LINSR) is set.
The transmitter is automatically re-enabled once TXD is
high.
If the bit LINM is set in the interrupt mask register (IMR) an
Interrupt IRQ will be generated.
A read of the LIN status register (LINSR) with the TXD pin
is high will clear the bit TXDOM.
Over-Temperature Shutdown (LIN Interrupt)
LIN Dominant Voltage Level Selection
The output low side FET is protected against over-
temperature conditions. In case of an over-temperature
condition, the transmitter will be shut down and the bit LINOT
in the LIN status register (LINSR) is set.
The LIN dominant voltage level can be selected by the bit
LDVS in the LIN control register (LINCR).
LIN Receiver Operation Only
If the bit LINM is set in the interrupt mask register (IMR) an
Interrupt IRQ will be generated.
While in Normal Mode the activation of the RXONLY bit
disables the LIN TX driver. In the case of a LIN error condition
this bit is automatically set. In case a Low Power Mode is
selected with this bit set, the LIN wake-up functionality is
disabled, then, in Stop Mode, the RXD pin will reflect the state
of the LIN bus.
The transmitter is automatically re-enabled once the
condition is gone and TXD is high.
A read of the LIN status register (LINSR) with the TXD pin
will re-enable the transmitter.
STOP Mode And Wake-up Feature
RXD Short Circuit Detection (LIN Interrupt)
During Stop Mode operation the transmitter of the physical
layer is disabled. In case the bit LIN-PU was set in the Stop
Mode sequence the internal pull-up resistor is disconnected
from VSUP and a small current source keeps the LIN pin in
the recessive state. The receiver is still active and able to
detect wake-up events on the LIN bus line.
The LIN transceiver has a short-circuit detection for the
RXD output pin. In case of an short-circuit condition, either 5V
or ground, the bit RXSHORT in the LIN status register
(LINSR) is set and the transmitter is shutdown.
If the bit LINM is set in the interrupt mask register (IMR) an
interrupt IRQ will be generated.
A dominant level longer than tPROPWL followed by a rising
edge will generate a wake-up interrupt and will be reported in
the ISR. Also see Figure 11, page 19.
The transmitter is automatically re-enabled once the
condition is gone (transition on RXD) and TXD is high.
A read of the LIN status register (LINSR) without the RXD
pin short circuit condition will clear the bit RXSHORT.
SLEEP Mode And Wake-up Feature
During Sleep Mode operation the transmitter of the
physical layer is disabled. In case the bit LIN-PU was set in
the Sleep Mode sequence the internal pull-up resistor is
disconnected from VSUP and a small current source keeps
the LIN pin in recessive state. The receiver is still active to be
able to detect wake-up events on the LIN bus line.
TXD Dominant Detection (LIN Interrupt)
The LIN transceiver monitors the TXD input pin to detect
stuck in dominant (0V) condition. In case of a stuck condition
(TXD pin 0V for more than 1 second (typ.)) the transmitter is
shut down and the bit TXDOM in the LIN status register
(LINSR) is set.
A dominant level longer than tPROPWL followed by a rising
edge will generate a system wake-up (Reset) and will be
reported in the ISR. Also see Figure 10, page 18.
If the bit LINM is set in the interrupt mask register (IMR) an
interrupt IRQ will be generated.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
• MISO—Master-In Slave-Out
SPI AND CONFIGURATION
• SCLK—Serial Clock
The SPI creates the communication link between a
microcontroller (master) and the 33910.
A complete data transfer via the SPI consists of 1 byte.
The master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 3 system
status bits and one not defined bit (VMS,LINS,HSS,n.d.) + 4
bits of status information (S3:S0).
The interface consists of four pins (see Figure 19):
•
CS—Chip Select
• MOSI—Master-Out Slave-In
CS
Register Write Data
MOSI
MISO
A3
A2
A1
A0
C3
C2
C1
C0
S0
Register Read Data
VMS LINS HSS S3 S2
–
S1
SCLK
Read Data Latch
Write Data Latch
Rising Edge of SCLK
Falling Edge of SCLK
Change MISO/MISO Output
Sample MISO/MISO Input
Figure 19. SPI Protocol
During the inactive phase of the CS (HIGH), the new data
transfer is prepared.
The rising edge of the chip select CS indicates the end of
the transfer and latches the write data (MOSI) into the
register. The CS high forces MISO to the high-impedance
state.
The falling edge of the CS indicates the start of a new data
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
Register reset values are described along with the reset
condition. Reset condition is the condition causing the bit to
be set to its reset value. The main reset conditions are:
With the rising edge of the SPI clock (SCLK), the data is
moved to MISO/MOSI pins. With the falling edge of the SPI
clock (SCLK) the data is sampled by the receiver.
- Power-On Reset (POR): level at which the logic is reset
and BATFAIL flag sets.
The data transfer is only valid if exactly 8 sample clock
edges are present during the active (low) phase of CS.
- Reset Mode
- Reset done by the RST pin (ext_reset)
33910
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Freescale Semiconductor
31
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
SPI REGISTER OVERVIEW
.
Table 6. System Status Register
BIT
Adress(A3:A0)
Register Name / Read/Write Information
SYSSR - System Status Register
7
6
5
4
$0 - $F
R
VMS
LINS
HSS
-
Table 7 summarizes the SPI Register content for Control Information (C3:C0)=W and status information (S3:S0) = R.
Table 7. SPI Register Overview
BIT
Adress(A3:A0)
Register Name / Read/Write Information
3
HVSE
VSOV
VSOV
-
2
LINPE
VSUV
VSUV
-
1
0
MCR - Mode Control Register
VSR - Voltage Status Register
VSR - Voltage Status Register
WUCR - Wake-up Control Register
WUSR - Wake-up Status Register
WUSR - Wake-up Status Register
LINCR - LIN Control Register
LINSR - LIN Status Register
W
R
MOD2
VDDOT
VDDOT
-
MOD1
BATFAIL
BATFAIL
L1WE
L1
$0
$1
$2
$3
$4
$5
$6
$7
R
W
R
-
-
-
R
-
-
-
L1
W
R
LDVS
RXSHORT
RXSHORT
PWMHS2
HS2OP
HS2OP
RXONLY
TXDOM
TXDOM
PWMHS1
HS2CL
HS2CL
WD2
LSR1
LINOT
LINOT
HS2
LSR0
LINOC
LINOC
HS1
LINSR - LIN Status Register
R
HSCR - High Side Control Register
HSSR - High Side Status Register
HSSR - High Side Status Register
W
R
HS1OP
HS1OP
WD1
CYST1
WDOFF
WDOFF
MX1
HS1CL
HS1CL
WD0
R
TIMCR - Timing Control Register
W
CS/WD
$A
CYST2
WDERR
WDERR
MX2
CYST0
WDWO
WDWO
MX0
WDSR - Watchdog Status Register
WDSR - Watchdog Status Register
AMUXCR - Analog Multiplexer Control Register
CFR - Configuration Register
R
R
WDTO
WDTO
L1DS
HVDD
HSM
$B
$C
$D
W
W
W
R
CYSX8
-
-
-
IMR - Interrupt Mask Register
LINM
ISR1
ISR1
VMM
$E
ISR - Interrupt Source Register
ISR3
ISR2
ISR0
$F
ISR - Interrupt Source Register
R
ISR3
ISR2
ISR0
Note: Address $8 and $9 are reserved and must not be used.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
HSS - High Side Switch Status
REGISTER DEFINITIONS
This read-only bit indicates that one or more bits in the
HSSR are set.
System Status Register - SYSSR
The system status register (SYSSR) is always transferred
with every SPI transmission and gives a quick system status
overview. It summarizes the status of the voltage status
register (VSR), LIN status register (LINSR) and the HSSR.
1 = High Side Status bit set
0 = None
HS1CL
Table 8. System Status Register
HS1OP
HSS
HS2CL
S7
S6
S5
S4
HS2OP
Read
VMS
LINS
HSS
–.
Figure 22. High Side Status
Mode Control Register - MCR
VMS - Voltage Monitor Status
This read-only bit indicates that one or more bits in the
voltage status register (VSR) are set.
The MCR allows to switch between the operation modes
and to configure the 33910. Writing the MCR will return the
voltage status register (VSR).
1 = Voltage Monitor bit set
0 = None
BATFAIL
Table 9. Mode Control Register - $0
VDDOT
VMS
C3
C2
C1
C0
VSUV
VSOV
Write
HVSE
LINPE
MOD2
MOD1
Reset
Value
1
1
-
-
-
-
Figure 20. Voltage Monitor Status
Reset
Condition
POR
POR
LINS - LIN Status
This read-only bit indicates that one or more bits in the LIN
status register (LINSR) are set.
HVSE - High-Voltage Shutdown Enable
1 = LIN Status bit set
0 = None
This write-only bit enables/disables automatic shutdown of
the high side and the low side drivers during a high-voltage
VSOV condition.
LINOC
1 = automatic shutdown enabled
0 = automatic shutdown disabled
LINOT
LINS
TXDOM
LINPE - LIN pull-up enable.
RXSHORT
This write-only bit enables/disables the 30kΩ LIN pull-up
resistor in Stop and Sleep modes. This bit also controls the
LIN bus wake-up threshold.
Figure 21. LIN Status
1 = LIN pull-up resistor enabled
0 = LIN pull-up resistor disabled
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
MOD2, MOD1 - Mode Control Bits
Any access to the MCR or voltage status register (VSR)
will clear the BATFAIL flag.
These write-only bits select the Operating Mode and allow
to clear the watchdog in accordance with Table 11 Mode
Control Bits.
1 = POR Reset has occurred
0 = POR Reset has not occurred
Table 10. Mode Control Bits
Wake-up Control Register - WUCR
MOD2
MOD1
Description
This register is used to control the digital wake-up input.
Writing the wake-up control register (WUCR) will return the
wake-up status register (WUSR).
0
0
1
1
0
1
0
1
Normal Mode
Stop Mode
Sleep Mode
Table 12. Wake-up Control Register - $2
Normal Mode + watchdog Clear
C3
C2
C1
C0
Write
0
0
0
L1WE
Voltage Status Register - VSR
Returns the status of the several voltage monitors. This
register is also returned when writing to the MCR.
Reset
Value
1
1
1
1
Reset
Condition
Table 11. Voltage Status Register - $0/$1
POR, Reset Mode or ext_reset
S3
S2
S1
S0
L1WE - Wake-up Input Enable
Read
VSOV
VSUV
VDDOT BATFAIL
This write-only bit enables/disables the L1 input. In Stop
and Sleep Mode the L1WE bit activates the L1 input for wake-
up. If the L1 input is selected on the analog multiplexer, the
L1WE is masked to 0.
VSOV - VSUP Over-voltage
This read-only bit indicates an over-voltage condition on
the VS1 pin.
1 = Wake-up Input enabled.
0 = Wake-up Input disabled.
1 = Over-voltage condition.
0 = Normal condition.
Wake-up Status Register - WUSR
VSUV - VSUP Under-voltage
This register is used to monitor the digital wake-up inputs
and is also returned when writing to the wake-up control
register (WUCR).
This read-only bit indicates an under-voltage condition on
the VS1 pin.
1 = Under-voltage condition.
0 = Normal condition.
Table 13. Wake-up Status Register - $2/$3
S3
S2
S1
S0
VDDOT - Main Voltage Regulator Over-temperature
Warning
Read
-
-
-
L1
This read-only bit indicates that the main voltage regulator
temperature reached the Over-Temperature Prewarning
Threshold.
L1 - Wake-up input
This read-only bit indicates the status of the L1 input. If the
L1 input is not enabled then the wake-up status will return 0.
1 = Over-temperature prewarning
0 = Normal
After a wake-up form Stop or Sleep Mode this bit also
allows to verify the L1 input has caused the wake-up, by first
reading the interrupt status register (ISR) and then reading
the wake-up status register (WUSR).
BATFAIL - Battery Fail Flag.
This read-only bit is set during power-up and indicates that
the 33910 had a power on reset (POR).
1 = L1 Wake-up.
0 = L1 Wake-up disabled or selected as analog input.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
LIN Control Register - LINCR
LIN Status Register - LINSR
This register controls the LIN physical interface block.
Writing the LIN control register (LINCR) returns the LIN status
register (LINSR).
This register returns the status of the LIN physical
interface block and is also returned when writing to the LIN
control register (LINCR).
Table 14. LIN Control Register - $4
Table 16. LIN Status Register - $4/$5
C3
C2
C1
C0
S3
S2
S1
S0
Write
LDVS
RXONLY
LSR1
LSR0
Read
RXSHORT
TXDOM
LINOT
LINOC
Reset
Value
0
0
0
0
RXSHORT - RXD Pin Short Circuit
POR, Reset
Mode,
ext_reset or
LIN failure
gone*
This read-only bit indicates a short-circuit condition on the
RXD pin (shorted either to 5.0V or to Ground). The short
circuit delay must be 8µs worst case to be detected and to
shutdown the driver. To clear this bit, it must be read after the
condition is gone (transition detected on RXD pin). The LIN
driver is automatically re-enabled once the condition is gone.
POR, Reset
Mode or
ext_reset
Reset
Condition
POR
* LIN failure gone: if LIN failure (overtemp, TXD/RXD short) was set, the flag
resets automatically when the failure is gone.
1 = RXD short circuit condition.
0 = None.
LDVS - LIN Dominant Voltage Select
This write-only bit controls the LIN Dominant voltage:
1 = LIN Dominant Voltage = VLIN_DOM_1 (1.7V typ)
0 = LIN Dominant Voltage = VLIN_DOM_0 (1.1V typ)
TXDOM - TXD Permanent Dominant
This read-only bit signals the detection of a TXD pin stuck
at dominant (Ground) condition and the resultant shutdown in
the LIN transmitter. This condition is detected after the TXD
pin remains in dominant state for more than 1 second typical
value.
RXONLY - LIN Receiver Operation Only
This write-only bit controls the behavior of the LIN
transmitter.
To clear this bit, it must be read after TXD has gone high.
The LIN driver is automatically re-enabled once TXD goes
High.
In Normal Mode the activation of the RXONLY bit disables
the LIN transmitter. In case of a LIN error condition this bit is
automatically set.
1 = TXD stuck at dominant fault detected.
0 = None.
In Stop Mode this bit disables the LIN wake-up
functionality and the RXD pin will reflect the state of the LIN
bus.
LINOT - LIN Driver Over-temperature Shutdown
1 = only LIN receiver active (Normal Mode) or LIN wake-
up disabled (Stop Mode).
This read-only bit signals that the LIN transceiver was
shutdown due to over-temperature. The transmitter is
automatically re-enabled after the over-temperature
condition is gone and TXD is high. The LINOT bit is cleared
after SPI read once the condition is gone.
0 = LIN fully enabled.
LSRx - LIN Slew-Rate
This write-only bit controls the LIN driver slew-rate in
accordance with Table 15.
1 = LIN over-temperature shutdown
0 = None
Table 15. LIN Slew-Rate Control
LINOC - LIN Driver Over-Current Shutdown
LSR1
LSR0
Description
This read-only bit signals an over-current condition
occurred on the LIN pin. The LIN driver is not shutdown but
an IRQ is generated. To clear this bit, it must be read after the
condition is gone.
0
0
1
1
0
1
0
1
Normal Slew Rate (up to 20kb/s)
Slow Slew Rate (up to 10kb/s)
Fast Slew Rate (up to 100kb/s)
Reserved
1 = LIN over-current shutdown
0 = None
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
High Side Control Register - HSCR
HSxCL - High Side Current Limitation
This register controls the operation of the high side drivers.
Writing to this register returns the High Side Status Register
(HSSR).
This read-only bit indicates that the high side switch is
operating in current Limitation Mode.
1 = HSx in current limitation (or thermal shutdown)
0 = Normal
Table 17. High Side Control Register - $6
C3
C2
C1
C0
Timing Control Register - TIMCR
Write
PWMHS2 PWMHS1
HS2
HS1
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the TIMCR will also return the WDSR.
Reset
Value
0
0
0
0
Reset
Condition
POR, Reset Mode, ext_reset, HSx
over-temp or (VSOV & HVSE)
Table 19. Timing Control Register - $A
POR
C3
C2
C1
C0
PWMHSx - PWM Input Control Enable
WD2
WD1
WD0
Write
CS/WD
This write-only bit enables/disables the PWMIN input pin
to control the high side switch. The high side switch must be
enabled (HSx bit).
CYST2
CYST1
CYST0
Reset
Value
-
-
0
0
0
1 = PWMIN input controls HS1 output.
0 = HSx is controlled only by SPI.
Reset
Condition
POR
HSx - High Side Switch Control.
CS/WD - Cyclic Sense or Watchdog Prescaler Select.
This write-only bit enables/disables the high side switch.
1 = HSx switch on.
This write-only bit selects which prescaler is being written
to, the cyclic sense prescaler or the watchdog prescaler.
0 = HSx switch off.
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
High Side Status Register - HSSR
This register returns the status of the high side switch and
is also returned when writing to the HSCR.
WDx - Watchdog Prescaler
Table 18. High Side Status Register - $6/$7
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 20. This configuration is valid only if
windowing watchdog is active.
S3
S2
S1
S0
Read
HS2OP
HS2CL
HS1OP
HS1CL
Table 20. Watchdog Prescaler
High Side thermal shutdown
WD2
WD1
WD0
Prescaler Divider
A thermal shutdown of the high side drivers is indicated by
setting the HSxOP and HSxCL bits simultaneously.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
HSxOP - High Side Switch Open-Load Detection
4
This read-only bit signals that the high side switch is
conducting current below a certain threshold indicating
possible load disconnection.
6
8
10
12
14
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
36
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
CYSTx - Cyclic Sense Period Prescaler Select
1 = Last reset caused by watchdog timeout
0 = None
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
configuration register (CFR) (see page 38).
WDERR - Watchdog Error
This option is only active if the high side switch is enabled
when entering in Stop or Sleep Mode. Otherwise a timed
wake-up is performed after the period shown in Table 21.
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision timebase. The windowing function is
disabled.
Table 21. Cyclic Sense Interval
1 = WDCONF pin resistor missing
CYSX8(56) CYST2
CYST1
CYST0
Interval
0 = WDCONF pin resistor not floating
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
No Cyclic Sense
20ms
WDOFF - Watchdog Off
0
This read-only bit signals that the watchdog pin connected
to GND and therefore disabled. In this case watchdog
timeouts are disabled and the device automatically enters
Normal Mode out of Reset. This might be necessary for
software debugging and for programming the Flash memory.
0
40ms
0
60ms
0
80ms
0
100ms
120ms
140ms
160ms
320ms
480ms
640ms
800ms
960ms
1120ms
1 = Watchdog is disabled
0 = Watchdog is enabled
0
0
1
WDWO - Watchdog Window Open
1
This read-only bit signals when the watchdog window is
open for clears. The purpose of this bit is for testing. Should
be ignored in case WDERR is High.
1
1
1
1 = Watchdog window open
0 = Watchdog window closed
1
1
Analog Multiplexer Control Register - MUXCR
Notes
This register controls the analog multiplexer and selects
the divider ration for the L1 input divider.
56. bit CYSX8 is located in configuration register (CFR)
Watchdog Status Register
Table 23. Analog Multiplexer Control Register -$C
This register returns the watchdog status information and
is also returned when writing to the TIMCR.
C3
C2
C1
C0
Write
L1DS
MX2
MX1
MX0
Table 22. Watchdog Status Register - $A/$B
Reset
Value
S3
S2
S1
S0
1
0
0
0
Read
WDTO
WDERR WDOFF
WDWO
Reset
POR
POR, Reset Mode or ext_reset
Condition
WDTO - Watchdog Time Out
L1DS - L1 Analog Input Divider Select
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
This write-only bit selects the resistor divider for the L1
analog input. Voltage is internally clamped to VDD.
Any access to this register or the TIMCR will clear the
WDTO bit.
0 = L1 Analog divider: 1
1 = L1 Analog divider: 3.6 (typ.)
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
37
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
MXx - Analog Multiplexer Input Select
Table 25. Configuration Register - $D
These write-only bits selects which analog input is
multiplexed to the ADOUT0 pin according to Table 24.
C3
C2
C1
C0
When disabled or when in Stop or Sleep Mode, the output
buffer is not powered and the ADOUT0 output is left floating
to achieve lower current consumption.
Write
0
CYSX8
0
0
Reset
Value
0
0
0
0
POR, Reset
Mode or
ext_reset
Reset
Condition
POR
POR
POR
Table 24. Analog Multiplexer Channel Select
MX2
MX1
MX0
Meaning
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Disabled
Reserved
HVDD - Hall Sensor Supply Enable
This write-only bit enables/disables the state of the hall
sensor supply.
Die Temperature Sensor
VSENSE input
L1 input
1 = HVDD on
0 = HVDD off
Reserved
CYSX8 - Cyclic Sense Timing x 8
Reserved
This write-only bit influences the Cyclic Sense period as
shown in Table 21.
Reserved
1 = Multiplier enabled
0 = None
Configuration Register - CFR
This register controls the cyclic sense timing multiplier.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
38
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Interrupt Mask Register - IMR
VMM - Voltage Monitor Interrupt Mask
This register allow to mask some of interrupt sources. The
respective flags within the ISR will continue to work but will
not generate interrupts to the MCU. The 5V Regulator over-
temperature prewarning interrupt and under-voltage (VSUV)
interrupts can not be masked and will always cause an
interrupt.
This write-only bit enables/disables interrupts generated in
the voltage monitor block. The only maskable interrupt in the
voltage monitor block is the VSUP over-voltage interrupt.
1 = Interrupts Enabled
0 = Interrupts Disabled
Writing to the interrupt mask register (IMR) will return the
ISR.
Interrupt Source Register - ISR
This register allows the MCU to determine the source of
the last interrupt or wake-up respectively. A read of the
register acknowledges the interrupt and leads IRQ pin to
high, in case there are no other pending interrupts. If there
are pending interrupts, IRQ will be driven high for 10µs and
then be driven low again.
Table 26. Interrupt Mask Register - $E
C3
C2
C1
C0
Write
HSM
-.
LINM
VMM
This register is also returned when writing to the interrupt
mask register (IMR).
Reset
Value
1
1
1
1
Reset
Condition
POR
Table 27. Interrupt Source Register - $E/$F
S3
S2
S1
S0
HSM - High Side Interrupt Mask
Read
ISR3
ISR2
ISR1
ISR0
This write-only bit enables/disables interrupts generated in
the high side block.
ISRx - Interrupt Source Register
1 = HS Interrupts Enabled
0 = HS Interrupts Disabled
These read-only bits indicate the interrupt source following
Table 28. If no interrupt is pending than all bits are 0.
In case more than one interrupt is pending, than the
interrupt sources are handled sequentially multiplex.
LINM - LIN Interrupts Mask
This write-only bit enables/disables interrupts generated in
the LIN block.
1 = LIN Interrupts Enabled
0 = LIN Interrupts Disabled
Table 28. Interrupt Sources
Interrupt Source
Priority
ISR3 ISR2 ISR1 ISR0
none maskable
maskable
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
no interrupt
no interrupt
L1 wake-up from Stop Mode-
HS interrupt (Over-temperature)
Reserved
none
highest
-
-
LIN interrupt (RXSHORT, TXDOM, LIN OT, LIN
OC) or LIN wake-up
0
0
1
1
0
1
1
0
Voltage monitor interrupt
Voltage monitor interrupt
(High-voltage)
(Low-voltage and VDD over-temperature)
-
Forced wake-up
lowest
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
TYPICAL APPLICATIONS
LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
The 33910 can be configured in several applications. The figure below shows the 33910 in the typical Slave Node Application.
V
BAT
D1
C2
C1
VDD
IRQ
Interrupt
Control Module
LVI, HVI, HTI, OCI
Voltage Regulator
5V Output Module
C5
C4
C3
AGND
HVDD
Hall Sensor Supply
VDD
Reset
Control Module
LVR, HVR, HTR, WD,
RST
IRQ
RST
Window
R1
Watchdog Module
PWMIN
TIMER
High Side Control
Module
HS1
HS2
MISO
MOSI
SCLK
CS
Chip Temp Sense Module
VBAT Sense Module
SPI
&
CONTROL
SPI
VSENSE
MCU
R2
L1
Analog Input Module
ADOUT0
A/D
Wake Up Module
Digital Input Module
RXD
TXD
LIN Physical Layer
SCI
A/D
LIN
LIN
C6
R7
Typical Component Values:
C1 = 47µF; C2 = C4 = 100nF; C3 = 10µF; C5 = 220pF
R1 = 10kΩ; R2 = 20kΩ-200kΩ
Recommended Configuration of the not Connected Pins (NC):
Pin 15, 16, 17, 19, 20, 21, 22 = GND
Pin 11 = open (floating)
Pin 28 = this pin is not internally connected and may be used for PCB routing optimization.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
40
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.Freescale.com and select Documentation, then under
Available Documentation column select Packaging Information.
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
41
IMPORTANT FOR THE MOST CURRENT REVISION OF THE PACK-
AGE, VISIT WWW.FREESCALE.COM AND SELECT DOCUMENTA-
PACKAGE DIMENSIONS (Continued)
AC SUFFIX (PB-FREE)
32-PIN LQFP
98ASH70029A
REVISION D
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
42
REVISION HISTORY
REVISION HISTORY
Revision Date
Description of Changes
9/2007
2/2008
•
•
Initial Release
Changed Functional Block Diagram on page 22.
3.0
4.0
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
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MC33910
Rev. 4.0
2/2008
相关型号：
MC33910G5AC
0.11A BUF OR INV BASED PRPHL DRVR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32
ROCHESTER
MC33911G5AC
System Basis Chip, LIN, 1x 5.0V/60mA LDOs, DC Motor Predriver, Enhanced EMC, QFP 32, Tray
NXP
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