MC33982BPNA/R2 [FREESCALE]
Single Intelligent High-current Self-protected Silicon High Side Switch (2.0 mΩ); 单智能大电流自我保护硅高边开关（ 2.0毫欧）
| 型号： | MC33982BPNA/R2 |
| 厂家： | 
Freescale |
| 描述： | Single Intelligent High-current Self-protected Silicon High Side Switch (2.0 mΩ) |
| 文件： | 总36页 (文件大小：838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MC33982
Rev. 16.0, 11/2009
Freescale Semiconductor
Technical Data
Single Intelligent High-current
Self-protected Silicon High Side
Switch (2.0 mΩ)
33982B/C
The 33982 is a self-protected silicon 2.0 mΩ high side switch used
to replace electromechanical relays, fuses, and discrete devices in
power management applications. The 33982 is designed for harsh
environments, and it includes self-recovery features. The device is
suitable for loads with high inrush current, as well as motors and all
types of resistive and inductive loads.
HIGH SIDE SWITCH
Programming, control, and diagnostics are implemented via the
Serial Peripheral Interface (SPI). A dedicated parallel input is available
for alternate and Pulse Width Modulation (PWM) control of the output.
SPI programmable fault trip thresholds allow the device to be adjusted
for optimal performance in the application.
Bottom View
The 33982 is packaged in a power-enhanced 12 x 12 nonleaded
PQFN package with exposed tabs.
PNA SUFFIX
98ARL10521D
16-PIN PQFN
Features
• Single 2.0 mΩ max high side switch with parallel input or SPI
control
ORDERING INFORMATION
Temperature
• 6.0 V to 27 V operating voltage with standby currents < 5.0 μA
• Output current monitoring with two SPI-selectable current ratios
• SPI control of over-current limit, over-current fault blanking time,
output-OFF open load detection, output ON/OFF control,
watchdog timeout, slew rates, and fault status reporting
• SPI status reporting of over-current, open and shorted loads,
over-temperature shutdown, under-voltage and over-voltage
shutdown, fail-safe pin status, and program status
Device
Package
Range (T )
A
MC33982BPNA/R2
MC33982CPNA/R2
-40°C to 125°C
16 PQFN
• Enhanced -16 V reverse polarity VPWR protection
VDD
VDD
VDD
VPWR
33982
VDD
FS
VPWR
GND
I/O
I/O
WAKE
SI
SO
SCLK
CS
SCLK
CS
MCU
HS
SO
RST
IN
SI
I/O
I/O
LOAD
CSNS
FSI
A/D
GND
GND
PWR GND
Figure 1. 33982 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Device Variations
Freescale Part No.
Reference
Reference
Location
Output Clamp Energy
OD3 bit for X111 address
Location
Table 3
Table 3
MC33982B
MC33982C
0
1
Table 16
Table 16
1.5J
1.0J
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INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VIC
Internal
Regulator
Over-voltage
Protection
IUP
CS
SO
Programmable
Switch Delay
0–525 ms
Selectable Slew
Rate Gate Drive
SPI
3.0 MHz
HS
Selectable Over-current
SI
SCLK
FS
High Detection
150 A or 100 A
Logic
IN
Selectable Over-
current Low Detection
Blanking Time
Selectable
Overcurrent
Low Detection
15–50 A
RST
WAKE
0.15–155 ms
Open Load
Detection
IDWN
RDWN
Over-temperature
Detection
VIC
Selectable
Output Current
Recopy
Programmable
Watchdog
310–2500 ms
IUP
1/5400 or 1/40000
FSI
GND
CSNS
Figure 2. 33982 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
12 11 10
9
8
7
6
5
4
3
2
1
13
GND
TRANSPARENT
TOP VIEW
14
VPWR
15
HS
16
HS
Figure 3. 33982 Pin Connections
Table 2. Pin Definitions
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Pin
Number
Pin
Function
Pin Name
Formal Name
Definition
This pin is used to output a current proportional to the high side output
current and used externally to generate a ground-referenced voltage for
the microcontroller to monitor output current.
1
CSNS
Output
Output Current
Monitoring
This pin is used to input a Logic [1] signal in order to enable the watchdog
timer function.
2
3
WAKE
RST
Input
Input
Wake
This input pin is used to initialize the device configuration and fault
registers, as well as place the device in a low current sleep mode.
Reset (Active Low)
Direct Input
The Input pin is used to directly control the output.
4
5
IN
Input
This is an open drain configured output requiring an external pull-up
resistor to VDD for fault reporting.
FS
Output
Fault Status
(Active Low)
The value of the resistance connected between this pin and ground
determines the state of the output after a watchdog timeout occurs.
6
7
8
9
FSI
CS
Input
Input
Input
Input
Fail-Safe Input
This input pin is connected to a chip select output of a master
microcontroller (MCU).
Chip Select
(Active Low)
This input pin is connected to the MCU providing the required bit shift
clock for SPI communication.
SCLK
SI
Serial Clock
This is a command data input pin connected to the SPI Serial Data
Output of the MCU or to the SO pin of the previous device in a daisy chain
of devices.
Serial Input
This is an external voltage input pin used to supply power to the SPI
circuit.
10
VDD
Input
Digital Drain Voltage
(Power)
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PIN CONNECTIONS
Table 2. Pin Definitions (continued)
Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 16.
Pin
Number
Pin
Function
Pin Name
Formal Name
Definition
This output pin is connected to the SPI Serial Data Input pin of the MCU
or to the SI pin of the next device in a daisy chain of devices.
11
SO
Output
Serial Output
This pin may not be connected.
12
13
14
NC
NC
No Connect
Ground
This pin is the ground for the logic and analog circuitry of the device.
GND
Ground
Input
This pin connects to the positive power supply and is the source input of
operational power for the device.
VPWR
Positive Power
Supply
Protected high side power output to the load. Output pins must be
connected in parallel for operation.
15, 16
HS
Output
High Side Output
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
ELECTRICAL RATINGS
Operating Voltage Range
Steady-state
VPWR
V
-16 to 41
-0.3 to 5.5
-0.3 to 7.0
VDD Supply Voltage
VDD
V
V
Input/Output Voltage(1)
VIN, RST, FSI,
CSNS, SI, SCLK,
CS, FS
SO Output Voltage(1)
VSO
ICL(WAKE)
ICL(CSNS)
IHS
-0.3 to VDD+0.3
V
mA
mA
A
WAKE Input Clamp Current
CSNS Input Clamp Current
Output Current (2)
2.5
10
60
Output Voltage
Positive
VHS
V
41
Negative
-15
Output Clamp Energy(3)
33982B
ECL
J
1.5
1.0
33982C
ESD Voltage(4)
V
Human Body Model (HBM)
Charge Device Model (CDM)
Corner Pins (1, 12, 15, 16)
All Other Pins (2, 11, 13, 14)
VESD1
VESD3
±2000
±750
±500
Notes
1. Exceeding this voltage limit may cause permanent damage to the device.
2. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output
current using package thermal resistance is required.
3. Active clamp energy using single-pulse method (L = 16 mH, RL = 0, VPWR = 12 V, TJ = 150°C).
4. ESD1 testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω); ESD3 testing is
performed in accordance with the Charge Device Model (CDM), Robotic (Czap = 4.0 pF).
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Unit
THERMAL RATINGS
Operating Temperature
Ambient
°C
TA
TJ
-40 to 125
-40 to 150
Junction
Storage Temperature
TSTG
-55 to 150
°C
Thermal Resistance(5)
Junction-to-Case
°C/W
R
R
<1.0
30
JC
JA
θ
Junction-to-Ambient
θ
Peak Package Reflow Temperature During Reflow(6), (7)
TPPRT
Note 7
°C
Notes
5. Device mounted on a 2s2p test board per JEDEC JESD51-2.
6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
7. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
Full Operational
VPWR
V
6.0
–
–
–
27
20
VPWR Operating Supply Current
Output ON, IHS = 0 A
IPWR(ON)
mA
VPWR Supply Current
IPWR(SBY)
mA
Output OFF, Open Load Detection Disabled, WAKE > 0.7 VDD
RST = VLOGIC HIGH
,
–
–
5.0
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
IPWR(SLEEP)
μA
TJ = 25°C
TJ = 85°C
–
–
–
–
10
50
VDD Supply Voltage
VDD(ON)
IDD(ON)
4.5
5.0
5.5
V
VDD Supply Current
mA
No SPI Communication
3.0 MHz SPI Communication
–
–
–
–
1.0
5.0
VDD Sleep State Current
IDD(SLEEP)
VPWR(OV)
VPWR(OVHYS)
VPWR(UV)
VPWR(UVHYS)
VPWR(UVPOR)
–
28
0.2
5.0
–
–
32
5.0
36
1.5
6.0
–
μA
V
Over-voltage Shutdown Threshold
Over-voltage Shutdown Hysteresis
Under-voltage Output Shutdown Threshold(8)
Under-voltage Hysteresis(9)
0.8
5.5
0.25
–
V
V
V
Under-voltage Power-ON Reset
–
5.0
V
POWER OUTPUT
Output Drain-to-Source ON Resistance (IHS = 30 A, TJ = 25°C)
RDS(ON)
RDS(ON)
RDS(ON)
mΩ
mΩ
mΩ
V
PWR = 6.0 V
–
–
–
–
–
–
3.0
2.0
2.0
VPWR = 10 V
VPWR = 13 V
Output Drain-to-Source ON Resistance (IHS = 30 A, TJ = 150°C)
V
PWR = 6.0 V
–
–
–
–
–
–
5.1
3.4
3.4
VPWR = 10 V
VPWR = 13 V
Output Source-to-Drain ON Resistance (IHS = 30 A, TJ = 25°C)(10)
V
PWR = -12 V
–
2.0
4.0
Notes
8. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification.
9. This applies when the under-voltage fault is not latched (IN = 0).
10. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR
.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (CONTINUED)
Output Over-current High Detection Levels (9.0 V < VPWR < 16 V)
A
SOCH = 0
SOCH = 1
IOCH0
IOCH1
120
80
150
100
180
120
Over-current Low Detection Levels (SOCL[2:0])
A
000
001
010
011
100
101
110
111
IOCL0
IOCL1
IOCL2
IOCL3
IOCL4
IOCL5
IOCL6
IOCL7
41
36
32
29
25
20
16
12
50
45
40
35
30
25
20
15
59
54
48
41
35
30
24
18
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
–
DICR D2 = 0
DICR D2 = 1
CSR0
CSR1
–
–
1/5400
–
–
1/40000
Current Sense Ratio (CSR0) Accuracy
CSR0_ACC
%
Output Current
10 A
-20
-14
-13
-12
-13
-13
–
–
–
–
–
–
20
14
13
12
13
13
20 A
25 A
30 A
40 A
50 A
Current Sense Ratio (CSR1) Accuracy
CSR1_ACC
%
Output Current
10 A
-25
-19
-18
-17
-18
-18
–
–
–
–
–
–
25
19
18
17
18
18
20 A
25 A
30 A
40 A
50 A
Current Sense Clamp Voltage
CSNS Open, IHS = 59.0 A
VCL(CSNS)
V
4.5
0
6.0
10
7.0
20
Current Sense Leakage(11)
ILEAK(CSNS)
μA
IN=1 with OUT opened of load or IN=0
Open Load Detection Current(12)
IOLDC
30
–
100
4.0
μA
Output Fault Detection Threshold
Output Programmed OFF
VOLD(THRES)
V
2.0
3.0
Notes
11. This parameter is achieved by the design characterization by measuring a statistically relevant sample size across process variations
but, not tested in production.
12. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of
an open load condition when the specific output is commanded OFF.
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ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT (CONTINUED)
Output Negative Clamp Voltage
0.5 A < IHS < 2.0 A, Output OFF
VCL
V
-20
160
5.0
–
175
–
-15
190
20
Over-temperature Shutdown(13)
TSD
°C
°C
Over-temperature Shutdown Hysteresis(13)
TSD(HYS)
CONTROL INTERFACE
Input Logic High-voltage(14)
VIH
VIL
0.7 x VDD
–
–
–
–
V
V
Input Logic Low-voltage(14)
0.2 x
VDD
Input Logic Voltage Hysteresis(15)
Input Logic Pull-down Current (SCLK, IN, SI)
RST Input Voltage Range
VIN(HYS)
IDWN
100
5.0
4.5
–
600
–
1200
20
mV
μA
V
VRST
5.0
–
5.5
20
SO, FS Tri-state Capacitance(16)
Input Logic Pull-down Resistor (RST) and WAKE
Input Capacitance(16)
CSO
pF
kΩ
pF
V
RDWN
CIN
100
–
200
4.0
400
12
WAKE Input Clamp Voltage(17)
ICL(WAKE) < 2.5 mA
VCL(WAKE)
7.0
-2.0
–
–
14
-0.3
–
WAKE Input Forward Voltage
VF(WAKE)
V
V
I
CL(WAKE) = -2.5 mA
SO High-state Output Voltage
OH = 1.0 mA
FS, SO Low-state Output Voltage
OL = -1.6 mA
VSOH
I
0.8 x VDD
–
VSOL
V
I
–
0.2
0.0
–
0.4
5.0
20
SO Tri-state Leakage Current
CS > 0.7 x VDD
ISO(LEAK)
μA
μA
kΩ
-5.0
Input Logic Pull-up Current (18)
CS, VIN > 0.7 x VDD
IUP
5.0
FSI Input Pin External Pull-down Resistance
FSI Disabled, HS Indeterminate
FSI Enabled, HS OFF
RFS
RFSDIS
RFSOFF
RFSON
–
0.0
10
–
1.0
14
–
6.0
30
FSI Enabled, HS ON
Notes
13. Guaranteed by process monitoring. Not production tested.
14. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN, and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage reference to VPWR
.
15. No hysteresis on FSI and wake pins. Parameter is guaranteed by process monitoring but is not production tested.
16. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
17. The current must be limited by a series resistance when using voltages > 7.0 V.
18. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD
.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rising Slow Slew Rate A (DICR D3 = 0)(19)
9.0 V < VPWR < 16 V
SRRA_SLOW
SRRB_SLOW
SRRA_FAST
SRRB_FAST
SRFA_SLOW
SRFB_SLOW
SRFA_FAST
SRFB_FAST
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
V/μs
0.2
0.03
0.4
0.6
0.1
1.0
0.1
0.6
0.1
2.0
0.35
1.2
0.3
4.0
1.2
1.2
0.3
4.0
1.2
Output Rising Slow Slew Rate B (DICR D3 = 0)(20)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1)(19)
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1)(20)
9.0 V < VPWR < 16 V
0.03
0.2
Output Falling Slow Slew Rate A (DICR D3 = 0)(19)
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0)(20)
9.0 V < VPWR < 16 V
0.03
0.8
Output Falling Fast Slew Rate A (DICR D3 = 1)(19)
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1)(20)
9.0 V < VPWR < 16 V
0.1
Output Turn-ON Delay Time in Fast/Slow Slew Rate(21)
DICR = 0, DICR = 1
tDLY(ON)
tDLY_SLOW(OFF)
tDLY_FAST(OFF)
fPWM
μs
μs
μs
Hz
1.0
20
18
100
500
Output Turn-OFF Delay Time in Slow Slew Rate Mode(22)
DICR = 0
230
Output Turn-OFF Delay Time in Fast Slew Rate Mode(22)
DICR = 1
10
–
60
200
–
Direct Input Switching Frequency (DICR D3 = 0)
300
Notes
19. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high side output = 0.5 V to VPWR-3.5 V. These parameters are
guaranteed by process monitoring.
20. Rise and Fall Slow Slew Rates B measured across a 5.0 Ω resistive load at high side output = VPWR-3.5 V to VPWR-0.5 V. These
parameters are guaranteed by process monitoring.
21. Turn-ON delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to VHS = 0.5 V with
RL = 5.0 Ω resistive load.
22. Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to VHS = VPWR-0.5 V
with RL = 5.0 Ω resistive load.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (CONTINUED)
Over-current Low Detection Blanking Time (OCLT[1:0])
ms
tOCL0
tOCL1
tOCL2
tOCL3
00
01
10
11
108
7.0
155
10
202
13
0.8
1.2
1.6
0.08
0.15
0.25
Over-current High Detection Blanking Time
CS to CSNS Valid Time(23)
tOCH
1.0
–
10
–
20
10
μs
μs
tCNSVAL
Output Switching Delay Time (OSD[2:0])
ms
tOSD0
tOSD1
tOSD2
tOSD3
tOSD4
tOSD5
tOSD6
tOSD7
000
001
010
011
100
101
110
111
–
0.0
75
–
52
95
105
157
210
262
315
367
150
225
300
375
450
525
195
293
390
488
585
683
Watchdog Timeout (WD[1:0])(24)
ms
00
01
10
11
tWDTO0
tWDTO1
tWDTO2
tWDTO3
434
207
620
310
806
403
1750
875
2500
1250
3250
1625
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
Required Low-state Duration for RST(25)
fSPI
–
–
–
3.0
MHz
ns
tWRST
50
167
Notes
23. Time necessary for the CSNS to be within ±5% of the targeted value.
24. Watchdog timeout delay measured from the rising edge of WAKE to RST from a sleep state condition to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured
watchdog timeouts.
25. RST low duration measured with outputs enabled and going to OFF or disabled condition.
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(26)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)(26)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(26)
Required High-state Duration of SCLK (Required Setup Time)(26)
Required Low-state Duration of SCLK (Required Setup Time)(26)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(26)
SI to Falling Edge of SCLK (Required Setup Time)(27)
tCS
tENBL
–
–
–
–
–
–
–
–
–
–
300
5.0
167
167
167
167
83
ns
μs
ns
ns
ns
ns
ns
ns
ns
tLEAD
50
–
tWSCLKH
tWSCLKL
tLAG
–
50
25
25
tSI(SU)
tSI(HOLD)
tRSO
Falling Edge of SCLK to SI (Required Setup Time)(27)
83
SO Rise Time
CL = 200 pF
–
25
50
SO Fall Time
CL = 200 pF
tFSO
ns
–
25
50
SI, CS, SCLK, Incoming Signal Rise Time(27)
tRSI
tFSI
–
–
–
–
–
–
50
50
ns
ns
ns
ns
ns
SI, CS, SCLK, Incoming Signal Fall Time(27)
Time from Falling Edge of CS to SO Low-impedance(28)
Time from Rising Edge of CS to SO High-impedance(29)
tSO(EN)
tSO(DIS)
tVALID
–
145
145
65
Time from Rising Edge of SCLK to SO Data Valid(30)
0.2 VDD ≤ SO ≤ 0.8 VDD, CL = 200 pF
–
65
105
Notes
26. Maximum setup time required for the 33982 is the minimum guaranteed time needed from the microcontroller.
27. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
28. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
29. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
30. Time required to obtain valid data out from SO following the rise of SCLK.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
CS
V
VPWR-0.5 V
PWR
SRFB_SLOW & SRFB_FAST
SRfB
SRRB_SLOW
&
SRRB_FAST
VPWR-3.5 V
SRFA_SLOW & SRFA_FAST
SR
SRrA
& SRRA _FAST
RA_SLOW
0.5 V
HS
tDLY_SLOW(OFF) & tDLY_FAST(OFF)
t
DlLY(ON)
Figure 4. Output Slew Rate and Time Delays
IOCH
x
Load
Current
IOCLx
tOCH
Time
tOCLx
Figure 5. Over-current Shutdown
I
I
I
OCH
0
OCH1
OCL0
IOCL1
I
OCL2
Load
Current
I
OCL3
I
I
I
I
OCL4
OCL5
OCL6
OCL7
Time
t
t
t
t
t
OCL0
OCH
OCL3
OCL2
OCL1
x
Figure 6. Over-current Low and High Detection
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
ELECTRICAL CHARACTERISTICS
Figure 6 illustrates the over-current detection level (IOCLX
,
• During tOCHX, the device can reach up to Ioch0 over-
current level.
• During tOCL3 or tOCL2 or tOCL1 or tOCL0, the device can be
programmed to detect up to Iocl0.
IOCHX) the device can reach for each over-current detection
blanking time (tOCHX, tOCLX):
VIH
RST
0.2 VDD
0.2 VDD
VIL
tENBL
tCS
tWRST
0.7 V
DD
VIH
CS
0.2V
DD
VIL
tRSI
t
WSCLKH
I
t
LEAD
tLAG
VIH
0.7 VDD
SCLK
0.2 VDD
VIL
t
SI(SU)
t
WSCLKl
tFSI
t
SI(HOLD)
VIH
0.7V
DD
Don’t Care
Don’t Care
Don’t Care
Valid
Valid
SI
0.2V
DD
V
IH
Figure 7. Input Timing Switching Characteristics
tRSI
tFSI
VOH
3.5 V
50%
SCLK
1.0 V
VOL
tSO(EN)
0.2V
VOH
0.7 V
DD
SO
DD
VOL
Low to High
tRSO
tVALID
tFSO
SO
VOH
0.7 V
DD
High to Low
0.2 VDD
VOL
tSO(DIS)
Figure 8. SCLK Waveform and Valid SO Data Delay Time
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33982 is a self-protected silicon 2.0 mΩ high side
switch used to replace electromechanical relays, fuses, and
discrete devices in power management applications. The
33982 is designed for harsh environments, including self-
recovery features. The device is suitable for loads with high
inrush current, as well as motors and all types of resistive and
inductive loads.
Programming, control, and diagnostics are implemented
via the Serial Peripheral Interface (SPI). A dedicated parallel
input is available for alternate and pulse width modulation
(PWM) control of the output. SPI programmable fault trip
thresholds allow the device to be adjusted for optimal
performance in the application.
The 33982 is packaged in a power-enhanced 12 x 12
nonleaded PQFN package with exposed tabs.
FUNCTIONAL PIN DESCRIPTION
operation are disabled. This pin incorporates an active
internal pull-up current source.
OUTPUT CURRENT MONITORING (CSNS)
The CSNS pin outputs a current proportional to the high
side output current and used externally to generate a ground-
referenced voltage for the microcontroller to monitor output
current.
CHIP SELECT (CS)
This input pin is connected to a chip select output of a
master microcontroller (MCU). The MCU determines which
device is addressed (selected) to receive data by pulling the
CS pin of the selected device logic LOW, enabling SPI
communication with the device. Other unselected devices on
the serial link having their CS pins pulled up logic HIGH
disregard the SPI communication data sent. This pin
incorporates an active internal pull-up current source.
WAKE (WAKE)
This pin is used to input a Logic [1] signal in order to enable
the watchdog timer function. An internal clamp protects this
pin from high damaging voltages when the output is current
limited with an external resistor. This input has a passive
internal pull-down.
SERIAL CLOCK (SCLK)
RESET (RST)
This input pin is connected to the MCU providing the
required bit shift clock for SPI communication. It transitions
one time per bit transferred at an operating frequency, fSPI
defined by the communication interface. The 50 percent duty
cycle CMOS-level serial clock signal is idle between
command transfers. The signal is used to shift data into and
out of the device. This input has an active internal pull-down
current source.
This input pin is used to initialize the device configuration
and fault registers, as well as place the device in a low-
current sleep mode. The pin also starts the watchdog timer
when transitioning from logic LOW to logic HIGH. This pin
should not be allowed to be logic HIGH until VDD is in
regulation. This pin has a passive internal pull-down.
,
DIRECT IN (IN)
The Input pin is used to directly control the output. This
input has an active internal pulldown current source and
requires CMOS logic levels. This input may be configured via
SPI.
SERIAL INTERFACE (SI)
This is a command data input pin connected to the SPI
Serial Data Output of the MCU or to the SO pin of the
previous device in a daisy chain of devices. The input
requires CMOS logic level signals and incorporates an active
internal pull-down current source. Device control is facilitated
by the input's receiving the MSB first of a serial 8-bit control
command. The MCU ensures data is available upon the
falling edge of SCLK. The logic state of SI present upon the
rising edge of SCLK loads that bit command into the internal
command shift register.
FAULT STATUS (FS)
This is an open drain configured output requiring an
external pull-up resistor to VDD for fault reporting. When a
device fault condition is detected, this pin is active LOW.
Specific device diagnostic faults are reported via the SPI SO
pin.
FAIL-SAFE INPUT (FSI)
DIGITAL DRAIN VOLTAGE POWER (VDD)
The value of the resistance connected between this pin
and ground determines the state of the output after a
watchdog timeout occurs. Depending on the resistance
value, either the output is OFF or ON. When the FSI pin is
connected to GND, the watchdog circuit and fail-safe
This is an external voltage input pin used to supply power
to the SPI circuit. In the event VDD is lost, an internal supply
provides power to a portion of the logic, ensuring limited
functionality of the device. All device configuration registers
are reset.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
SERIAL OUTPUT (SO)
POSITIVE POWER SUPPLY (VPWR)
This output pin is connected to the SPI Serial Data Input
pin of the MCU or to the SI pin of the next device in a daisy
chain of devices. This output will remain tri-stated (high-
impedance OFF condition) so long as the CS pin of the device
is logic HIGH. SO is only active when the CS pin of the device
is asserted logic LOW. The generated SO output signals are
CMOS logic levels. SO output data is available on the falling
edge of SCLK and transitions immediately on the rising edge
of SCLK.
This pin connects to the positive power supply and is the
source input of operational power for the device. The VPWR
pin is a backside surface mount tab of the package.
HIGH-SIDE OUTPUT (HS)
This pin protects high side power output to the load.
Output pins must be connected in parallel for operation.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC33982 - Functional Block Diagram
Power Supply
Self-protected
High Side Switch
HS
MCU Interface and Output Control
Parallel Control Inputs
SPI Interface
High Side Switch
Power Supply
MCU Interface and Output Control
Figure 9. Functional Internal Block Diagram
presents extended diagnostics in order to detect load
disconnections and short-circuit fault conditions. The HS
output is actively clamped during a turn-off of inductive loads.
POWER SUPPLY
The 33982 is designed to operate from 4.0 to 28 V on the
VPWR pin. Characteristics are provided from 6.0 to 20 V for
the device. The VPWR pin supplies power to internal
regulator, analog, and logic circuit blocks. The VDD supply is
used for Serial Peripheral Interface (SPI) communication in
order to configure and diagnose the device. This IC
architecture provides a low quiescent current sleep mode.
Applying VPWR and VDD to the device will place the device in
the Normal Mode. The device will transit to Fail-safe mode in
case of failures on the SPI (watchdog timeout).
MCU INTERFACE AND OUTPUT CONTROL
In Normal mode, the load is controlled directly from the
MCU through the SPI. With a dedicated SPI command, it is
possible to independently turn on and off several loads that
are PWM’d at the same frequency, and duty cycles with only
one PWM signal. An analog feedback output provides a
current proportional to the load current. The SPI is used to
configure and to read the diagnostic status (faults) of high
side output. The reported fault conditions are: open load,
short-circuit to ground (OCLO-resistive and OCHI-severe
short-circuit), thermal shutdown, and under/over-voltage.
HIGH SIDE SWITCH: HS
This pin is the high side output controlling multiple
automotive loads with high inrush current, as well as motors
and all types of resistive and inductive loads. This N-channel
MOSFET with a 2.0 mΩ RDS(ON), is self-protected and
In Fail-safe mode, the load is controlled with dedicated
parallel input pins. The device is configured in default mode.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33982 has four operating modes: Sleep, Normal,
Fault, and Fail-safe. Table 6 summarizes details contained in
succeeding paragraphs.
transitions from Logic [0] to Logic [1]. The WAKE input is
capable of being pulled up to VPWR with a series of limiting
resistance that limits the internal clamp current.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 15. As long as the WD bit (D7) of an
incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the
programmed value of the WDR the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-safe mode until the
device is reinitialized.
Table 6. Fail-safe Operation and Transitions to Other
33982 Modes
Mode
FS WAKE RST WDTO
Comments
Device is in Sleep mode.
All outputs are OFF.
Sleep
x
0
x
0
1
x
Normal mode. Watchdog
is active if enabled.
Normal
Fault
1
No
No
During the Fail-safe mode, the output will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 7). In this mode, the SPI register content is retained
except for over-current high and low detection levels and
timing, which are reset to their default value (SOCL, SOCH,
OCLT). The watchdog, over-voltage, over-temperature, and
over-current circuitry (with default value for this one) are fully
operational.
The device is currently in
Fault mode. The faulted
output is OFF.
0
0
1
x
x
1
Watchdog has timed out
and the device is in Fail-
safe mode. The output is
as configured with the
RFS resistor connected
to FSI. RST and WAKE
must be transitioned to
Logic [0] simultaneously
to bring the device out of
the Fail-safe mode or
momentarily tied the FSI
pin to ground.
1
1
1
1
0
1
0
1
1
1
1
0
Fail-
safe
Table 7. Output State During Fail-safe Mode
Yes
RFS (kΩ)
High Side State
0
Fail-safe Mode Disabled
HS OFF
10
30
HS ON
x = Don’t care.
The Fail-safe mode can be detected by monitoring the
WDTO bit D2 of the WDR register. This bit is Logic [1] when
the device is in Fail-safe mode. The device can be brought
out of the Fail-safe mode by transitioning the WAKE and RST
pins from Logic [1] to Logic [0] or forcing the FSI pin to
Logic [0]. Table 6 summarizes the various methods for
resetting the device from the latched Fail-safe mode.
SLEEP MODE
The default mode of the 33982 is the Sleep mode. This is
the state of the device after first applying battery voltage
(VPWR), prior to any I/O transitions. This is also the state of
the device when the WAKE and RST are both Logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to Logic [0]. The device will transition to the
Normal or Fail-safe operating modes based on the WAKE
and RST inputs as defined in Table 6.
If the FSI pin is tied to GND, the Watchdog Fail-safe
operation is disabled.
LOSS OF VDD
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The output
can still be driven by the direct input IN. The 33982 uses the
battery input to power the output MOSFET related current
sense circuitry, and any other internal Logic, providing fail-
safe device operation with no VDD supplied. In this state, the
watchdog, over-voltage, over-temperature, and over-current
circuitry are fully operational with default values. Current
recopy is active with the default current recopy value.
NORMAL MODE
The 33982 is in Normal mode when:
• VPWR is within the normal voltage range.
•
RST pin is Logic [1].
• No fault has occurred.
FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input pin
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
• Over-current fault (high and low)
FAULT MODE
The FS pin will automatically return to Logic [1] when the
fault condition is removed, except for over-current and in
some cases under-voltage.
The 33982 indicates the following faults as they occur by
driving the FS pin to Logic [0]:
• Over-temperature fault
• Over-voltage and under-voltage fault
• Open load fault
Fault information is retained in the fault register and is
available (and reset) via the SO pin during the first valid SPI
communication (refer to Table 17).
PROTECTION AND DIAGNOSIS FEATURES
to re-enable the state of output and release FS. The
UVF bit will remain set to 1 until the next read operation.
OVER-TEMPERATURE FAULT (NON-LATCHING)
The 33982 incorporates over-temperature detection and
shutdown circuitry in the output structure. Over-temperature
detection is enabled when the output is in the ON state.
The under-voltage protection can be disabled through the
SPI (bit UV_dis = 1). In this case, the FS and UVF bits do not
report any under-voltage fault condition and the output state
will not be changed as long as the battery voltage does not
drop any lower than 2.5 V.
For the output, an over-temperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely
until action is taken by the MCU to shut OFF the output, or
until the offending load is removed.
OPEN LOAD FAULT (NON-LATCHING)
The 33982 incorporates open load detection circuitry on
the output. Output open load fault (OLF) is detected and
reported as a fault condition when the output is disabled
(OFF). The open load fault is detected and latched into the
status register after the internal gate voltage is pulled low
enough to turn OFF the output. The OLF fault bit is set in the
status register. If the open load fault is removed, the status
register will be cleared after reading the register.
When experiencing this fault, the OTF fault bit will be set
in the status register and cleared after either a valid SPI read
or a power reset of the device.
OVER-VOLTAGE FAULT (NON-LATCHING)
The 33982 shuts down the output during an over-voltage
fault (OVF) condition on the VPWR pin. The output remains
in the OFF state until the over-voltage condition is removed.
When experiencing this fault, the OVF fault bit is set in bit
OD1 and cleared after either a valid SPI read or a power reset
of the device.
The open load protection can be disabled through the SPI
(bit OL_dis). It is recommended to disable the open load
detection circuitry (OL_dis bit sets to logic [1]) in case of a
permanent open load fault condition.
The over-voltage protection and diagnostic can be
disabled through the SPI (bit OV_dis).
OVER-CURRENT FAULT (LATCHING)
The 33982 has eight programmable over-current low
detection levels (IOCL) and two programmable over-current
high detection levels (IOCH) for maximum device protection.
The two selectable, simultaneously active over-current
detection levels, defined by IOCH and IOCL, are illustrated in
Figure 6. The eight different over-current low detection levels
(IOCL0:IOCL7) are likewise illustrated in Figure 6.
UNDER-VOLTAGE SHUTDOWN (LATCHING OR
NON-LATCHING)
The output(s) will latch off at some battery voltage below
6.0 V. As long as the VDD level stays within the normal
specified range, the internal logic states within the device will
be sustained.
In the cases where the battery voltage drops below the
under-voltage threshold, (VPWRUV) the output will turn off,
FS will go to Logic [0], and the fault register UVF bit will be set
to 1.
If the load current level ever reaches the selected over-
current low detection level and the over-current condition
exceeds the programmed over-current time period (tOCx), the
device will latch the output OFF.
Two cases need to be considered when the battery level
recovers:
If at any time the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF
the output, regardless of the selected tOCL driver.
• If the output(s) command is (are) low, FS will go to
Logic [1], but the UVF bit will remain set to 1 until the
next read operation.
• If the output command is ON, then FS will remain at
Logic [0]. The output must be turned OFF and ON again
For both cases, the device output will stay off indefinitely
until the device is commanded OFF and then ON again.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
20
FUNCTIONAL DEVICE OPERATION
PROTECTION AND DIAGNOSIS FEATURES
Table 8. Device Behavior in Case of Under-voltage
High Side
UV Disable
IN = 0
(Falling or
UV Disable
IN∗∗∗ = 1
(Falling or
UV Enable
IN = 0
UV Enable
IN = 0
UV Enable
IN∗∗∗ = 1
UV Enable
IN∗∗∗ = 1
Switch
(VPWR Battery
Voltage)∗∗
State
(Falling VPWR) (Rising VPWR) (Falling VPWR) (Rising VPWR)
Rising VPWR) Rising VPWR)
VPWR >
VPWRUV
Output State
FS State
OFF
OFF
ON
1
OFF
OFF
ON
1
1
0
1
0
1
1
0
SPI Fault
Register UVF
Bit
1 until next read
0
0
VPWRUV >
VPWR >
UVPOR
Output State
FS State
OFF
OFF
OFF
OFF
OFF
ON
1
0
1
0
1
0
1
0
1
1
0
SPI Fault
Register UVF
Bit
0
UVPOR >
VPWR > 2.5 V∗
Output State
FS State
OFF
OFF
OFF
1
OFF
1
OFF
ON
1
1
1
1
1
0
SPI Fault
Register UVF
Bit
1 until next read
1 until next read 1 until next read
0
2.5 V > VPWR > Output State
OFF
1
OFF
1
OFF
1
OFF
1
OFF
OFF
0 V
FS State
1
0
1
0
SPI Fault
Register UVF
Bit
1 until next read 1 until next read 1 until next read 1 until next read
Comments
UV fault is
not latched
UV fault is
not latched
UV fault
is latched
∗ Typical value; not guaranteed
∗∗ While VDD remains within specified range.
∗∗∗ = IN is equivalent to IN direct input or IN_spi SPI input.
REVERSE BATTERY
GROUND DISCONNECT PROTECTION
The output survives the application of reverse voltage as
low as -16 V. Under these conditions, the output’s gate is
enhanced to keep the junction temperature less than 150°C.
The ON resistance of the output is fairly similar to that in the
Normal mode. No additional passive components are
required.
In the event the 33982 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless the state of the output at the time of
disconnection. A 10 kΩ resistor needs to be added between
the WAKE pin and the rest of the circuitry in order to ensure
that the device turns off in case of ground disconnect and to
prevent this pin to exceed its maximum ratings.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
stream of serial data is required on the SI pin, starting with D7
SPI PROTOCOL DESCRIPTION
to D0. The internal registers of the 33982 are configured and
controlled using a 4-bit addressing scheme, as shown in
Table 9. Register addressing and configuration are described
in Table 10. The SI input has an active internal pull-down,
The SPI interface has a full duplex, three-wire
synchronous data transfer with four I/O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
IDWN
.
The SI/SO pins of the 33982 follow a first-in first-out (D7/
D0) protocol with both input and output words transferring the
most significant bit (MSB) first. All inputs are compatible with
5.0 V CMOS logic levels.
SERIAL OUTPUT (SO)
The SO pin is a tri-stateable output from the shift register.
The SO pin remains in a high-impedance state until the CS
pin is put into a Logic [0] state. The SO data is capable of
reporting the status of the output, the device configuration,
and the state of the key inputs. The SO pin changes states on
the rising edge of SCLK and reads out on the falling edge of
SCLK. Fault and input status descriptions are provided in
Table 16.
The SPI lines perform the following functions:
SERIAL CLOCK (SCLK)
The SCLK pin clocks the internal shift registers of the
33982 device. The serial input pin (SI) accepts data into the
input shift register on the falling edge of the SCLK signal
while the serial output pin (SO) shifts data information out of
the SO line driver on the rising edge of the SCLK signal. It is
important that the SCLK pin be in a logic LOW state
whenever CS makes any transition. For this reason, it is
recommended that the SCLK pin be in a Logic [0] state
whenever the device is not accessed (CS Logic [1] state).
SCLK has an active internal pull-down, IDWN. When CS is
Logic [1], signals at the SCLK and SI pins are ignored and SO
is tri-stated (high-impedance). (See Figure 10 and
Figure 11.)
CHIP SELECT (CS)
The CS pin enables communication with the master
microcontroller (MCU). When this pin is in a Logic [0] state,
the device is capable of transferring information to and
receiving information from the MCU. The 33982 latches in
data from the input shift registers to the addressed registers
on the rising edge of CS. The device transfers status
information from the power output to the shift register on the
falling edge of CS. The SO output driver is enabled when CS
is Logic [0]. CS should transition from a Logic [1] to a Logic [0]
state only when SCLK is a Logic [0]. CS has an active internal
SERIAL INTERFACE (SI)
This is a serial interface (SI) command data input pin. SI
instruction is read on the falling edge of SCLK. An 8-bit
pull-up, IUP
.
CS
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1 OD0
Notes 1. RST is a Logic [1] state during the above operation.
2. D7:D0 relate to the most recent ordered entry of data into the device.
3. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 10. Single 8-Bit Word SPI Communication
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
22
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
CS
SCLK
SI
D
7
D
6
D
5
D
2
D
1
D
0
D
7
*
D
6
*
D
5
*
D
2
*
D
1
*
D
0
*
O
D
7
O
D
6
O
D
5
O
D
2
O
D
1
O
D
0
D
7
D
6
D
5
D
2
D
1
D
0
SO
Notes
1. RST is a Logic [1] state during the above operation.
2. D
7
:D0
r
e
la
t
e
to
th
e
m
o
s
t
re
c
e
n
t o
r
d
e
r
e
d
e
n
t
r
y
o
f
d
a
ta
i
nto
th
ed
e
v
ic
e
.
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7:OD0 relate to the first8bits of ordered faultandstatus data outof thedevice.
Figure 11. Multiple 8-Bit Word SPI Communication
Table 10, summarizes the SI registers. The registers are
addressed via D6:D4 of the incoming SPI word (Table 9).
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit
messages. A message is transmitted by the MCU starting
with the MSB, D7, and ending with the LSB, D0 (Table 9).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB (D7)
is the watchdog bit and in some cases a register address bit;
the next three bits, D6:D4, are used to select the command
register; and the remaining four bits, D3:D0, are used to
configure and control the output and its protection features.
Table 9. SI Message Bit Assignment
Bit Sig SI Msg Bit
Message Bit Description
Watchdog in: toggled to satisfy watchdog
requirements; also used as a register
address bit.
MSB
D7
Register address bits.
D6:D4
D3:D1
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable or to confirm transmitted data as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
Used to configure the inputs, outputs, and
the device protection features and SO
status content.
Used to configure the inputs, outputs, and
the device protection features and SO
status content.
LSB
D0
The 33982 has defined registers, which are used to
configure the device and to control the state of the output.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
eight possible levels as defined in Table 11. Bit D3 is used to
set the over-current high detection level to one of two levels
as defined in Table 12.
Table 10. Serial Input Address and Configuration Bit
Map
Serial Input Data
SI
Table 11. Over-current Low Detection Levels
Register
D7 D6 D5 D4
D3
0
D2
SOA2
0
D1
D0
SOCL2 SOCL1 SOCL0
Over-current Low Detection
(Amperes)
STATR
OCR
x
x
0
0
0
0
0
1
SOA1
SOA0
(D2)
(D1)
(D0)
0
CSNS IN_SPI
EN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
45
40
35
30
25
20
15
SOCHLR
CDTOLR
DICR
x
x
x
0
0
1
1
1
0
0
1
0
SOCH SOCL2 SOCL1 SOCL0
OL_dis CD_dis OCLT1 OCLT0
FAST CSNS
IN dis
A/O
SR
high
OSDR
WDR
NAR
0
1
0
1
x
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
OSD2
OSD1
WD1
0
OSD0
WD0
0
0
0
0
0
0
UOVR
TEST
0
UV_dis OV_dis
Table 12. Over-current High Detection Levels
Freescale Internal Use (Test)
Over-current High Detection
x = Don’t care.
SOCH (D3)
(Amperes)
DEVICE REGISTER ADDRESSING
0
1
150
100
The following section describes the possible register
addresses and their impact on device operation.
Address x011—Current Detection Time and Open Load
Register (CDTOLR)
Address x000—Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2, D1, and D0 determine the content of the first eight bits of
SO data. In addition to the device status, this feature provides
the ability to read the content of the OCR, SOCHLR,
CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers.
(Refer to the section entitled Serial Output Communication
(Device Status Return Data) beginning on page 26.)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an over-current low
condition before output latches OFF occurs. Bits D1 and D0
allow the MCU to select one of four fault blanking times
defined in Table 13. Note that these timeouts apply only to
the over-current low detection levels. If the selected over-
current high level is reached, the device will latch off within
20 μs.
Table 13. Over-current Low Detection Blanking Time
Address x001—Output Control Register (OCR)
OCLT[1:0]
Timing
The OCR register allows the MCU to control the output
through the SPI. Incoming message bit D0 (IN_SPI) reflects
the desired states of the high-side output: a Logic [1] enables
the output switch and a Logic [0] turns it OFF. A Logic [1] on
message bit D1 enables the Current Sense (CSNS) pin. Bits
D2 and D3 must be Logic [0]. Bit D7 is used to feed the
watchdog if enabled.
00
01
10
11
155 ms
10 ms
1.2 ms
150 μs
A Logic [1] on bit D2 disables the over-current low
(CD_dis) detection timeout feature. A Logic [1] on bit D3
disables the open load (OL) detection feature.
Address x010—Select Over-current High and Low
Register (SOCHLR)
The SOCHLR register allows the MCU to configure the
output over-current low and high detection levels,
Address x100—Direct Input Control Register (DICR)
respectively. In addition to protecting the device, this slow
blow fuse emulation feature can be used to optimize the load
requirements to match system characteristics. Bits D2:D0
are used to set the over-current low detection level to one of
The DICR register is used by the MCU to enable, disable,
or configure the direct IN pin control of the output. A Logic [0]
on bit D1 will enable the output for direct control by the IN pin.
A Logic [1] on bit D1 will disable the output from direct control.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
24
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
While addressing this register, if the input was enabled for
direct control, a Logic [1] for the D0 bit will result in a Boolean
AND of the IN pin with its corresponding D0 message bit
when addressing the OCR register. Similarly, a Logic [0] on
the D0 pin will result in a Boolean OR of the IN pin with the
corresponding message bits when addressing the OCR
register.
Table 14 shows the eight selectable output switching delay
times, which range from 0 to 525 ms.
Table 14. Switching Delay
OSD[2:0] (D2:D0)
Turn ON Delay (ms)
000
001
010
011
100
101
110
111
0
The DICR register is useful if there is a need to
independently turn on and off several loads that are PWM’d
at the same frequency and duty cycle with only one PWM
signal. This type of operation can be accomplished by
connecting the pertinent direct IN pins of several devices to a
PWM output port from the MCU, and configuring each of the
outputs to be controlled via their respective direct IN pin. The
DICR is then used to Boolean AND the direct IN(s) of each of
the outputs with the dedicated SPI bit that also controls the
output. Each configured SPI bit can now be used to enable
and disable the common PWM signal from controlling its
assigned output.
75
150
225
300
375
450
525
Address 1101—Watchdog Register (WDR)
A Logic [1] on bit D2 is used to select the high ratio (C
,
The WDR register is used by the MCU to configure the
watchdog timeout. Watchdog timeout is configured using bits
D1 and D0 (Table 15). When bits D1 and D0 are programmed
for the desired watchdog timeout period, the WD bit (D7)
should be toggled as well to ensure that the new timeout
period is programmed at the beginning of a new count
sequence.
SR1
1/40000) on the CSNS pin. The default value [0] is used to
select the low ratio (C , 1/5400). A Logic [1] on bit D3 is
SR0
used to select the high-speed slew rate. The default value [0]
corresponds to the low-speed slew rate.
Address 0101—Output Switching Delay Register (OSDR)
The OSDR register is used to configure the device with a
programmable time delay that is active during Output On
transitions that are initiated via the SPI (not via direct input).
Whenever the input is commanded to transition from
Logic [0] to Logic [1], the output will be held OFF for the time
delay configured in the OSDR register.
Table 15. Watchdog Timeout
WD[1:0] (D1:D0)
Timing (ms)
00
01
10
11
620
310
The programming of the contents of this register has no
effect on device Fail-safe mode operation. The default value
of the OSDR register is 000, equating to no delay, since the
switching delay time is 0 ms. This feature allows the user a
way to minimize inrush currents, or surges, thereby allowing
loads to be synchronously switched ON with a single
command.
2500
1250
Address 0110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy chain SPI configuration. This allows
devices to not be affected by commands being clocked over
a daisy-chained SPI configuration, and by toggling the WD bit
(D7) the watchdog circuitry will continue to be reset while no
programming or data readback functions are being requested
from the device.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Address 1110—Under-voltage/Over-voltage Register
(UOVR)
A valid message length is determined following a CS
transition of Logic [0] to Logic [1]. If there is a valid message
length, the data is latched into the appropriate registers. A
valid message length is a multiple of eight bits. At this time,
the SO pin is tri-stated and the fault status register is now
able to accept new fault status information.
The UOVR register can be used to disable or enable the
over-voltage and/or under-voltage protection. By default ([0]),
both protections are active. When disabled, an under-voltage
or over-voltage condition fault will not be reported in bits D1
and D0 of the output fault register.
The output status register correctly reflects the status of
the STATR-selected register data at the time the CS is pulled
to a Logic [0] during SPI communication and/or for the period
of time since the last valid SPI communication, with the
following exceptions:
Address x111—TEST
The TEST register is reserved for test and is not
accessible with SPI during normal operation.
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as
though the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an under-
voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI
SERIAL OUTPUT COMMUNICATION (DEVICE
STATUS RETURN DATA)
When the CS pin is pulled low, the output status register is
loaded. Meanwhile, the data is clocked out MSB- (OD7-) first
as the new message data is clocked into the SI pin. The first
eight bits of data clocking out of the SO, and following a CS
transition, are dependant upon the previously written SPI
word.
communication following an under-voltage VPWR
condition should be ignored.
• The RST pin transition from a Logic [0] to Logic [1] while
the WAKE pin is at Logic [0] may result in incorrect data
loaded into the status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
Any bits clocked out of the SO pin after the first eight will
be representative of the initial message bits clocked into the
SI pin since the CS pin first transitioned to a Logic [0]. This
feature is useful for daisy chaining devices as well as
message verification.
Table 16. Serial Output Bit Map Descriptions
Previous STATR
D7, D2, D1, D0
Serial Output Returned Data
SOA3 SOA2 SOA1 SOA0
OD7
WDin
WDin
WDin
WDin
WDin
0
OD6
OD5
OD4
OD3
OD2
UVF
OD1
OVF
OD0
FAULT
IN_SPI
SOCL0
OCLT0
A/O
x
x
x
x
x
0
1
0
1
x
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
OTF
0
OCHF
OCLF
OLF
0
1
1
0
0
0
1
1
–
1
0
1
0
1
1
0
0
–
0
SOCH
OL_dis
Fast SR
FSM_HS
0
0
CSNS EN
SOCL1
OCLT1
IN dis
OSD1
WD1
0
SOCL2
CD_dis
CSNS high
OSD2
WDTO
IN Pin
1110
0
1
1
OSD0
WD0
1
1
0
1
0
FSI Pin
UV_dis
–
WAKE Pin
OV_dis
–
1
1
0
WDin
–
See Table 1
–
x = Don’t care.
Previous Address SOA[2:0]=000
SERIAL OUTPUT BIT ASSIGNMENT
The eight bits of serial output data depend on the previous
serial input message, as explained in the following
If the previous three MSBs are 000, bits OD6:OD0 reflect
the current state of the Fault register (FLTR) (Table 17).
paragraphs. Table 16 summarizes the SO register content.
Previous Address SOA[2:0]=001
Bit OD7 reflects the state of the watchdog bit (D7)
addressed during the prior communication. The contents of
bits OD6:OD0 depend upon the bits D2:D0 from the most
recent STATR command SOA2:SOA0.
The data in bits OD1 and OD0 contain CSNS EN and
IN_SPI programmed bits, respectively.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
26
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Previous Address SOA[2:0]=010
Previous Address SOA[2:0]=100
The returned data contain the programmed values in the
DICR.
The data in bit OD3 contain the programmed over-current
high detection level (refer to Table 12), and the data in bits
OD2, OD1, and OD0 contain the programmed over-current
low detection levels (refer to Table 11).
Previous Address SOA[2:0]=101
• SOA3 = 0. The returned data contain the programmed
values in the OSDR. Bit OD3 (FSM_HS) reflects the state
of the output in the Fail-safe mode after a watchdog
timeout occurs.
Table 17. Fault Register
OD7
x
OD6
OD5
OD4
OD3
OD2
UVF
OD1
OD0
OTF OCHF OCLF OLF
OVF FAULT
• SOA3 = 1. The returned data contain the programmed
values in the WDR. Bit OD2 (WDTO) reflects the status of
the watchdog circuitry. If WDTO bit is Logic [1], the
watchdog has timed out and the device is in Fail-safe
mode. If WDTO is Logic [0], the device is in Normal mode
(assuming device is powered and not in the Sleep mode),
with the watchdog either enabled or disabled.
OD7 (x) = Don’t care.
OD6 (OTF) = Over-temperature Flag.
OD5 (OCHF) = Over-current High Flag. (This fault is latched.)
OD4 (OCLF) = Over-current Low Flag. (This fault is latched.)
OD3 (OLF) = Open Load Flag.
Previous Address SOA[2:0]=110
OD2 (UVF) = Under-voltage Flag. (This fault is latched or not
latched.)
• SOA3 = 0. OD2, OD1, and OD0 return the state of the IN,
FSI, and WAKE pins, respectively (Table 18).
OD1 (OVF) = Over-voltage Flag.
OD0 (FAULT) = This flag reports a fault and is reset by a read
operation.
Table 18. Pin Register
OD2
OD1
OD0
Note The FS pin reports a fault and is reset by a new Switch-ON
command (via SPI or direct input IN).
IN Pin
FSI Pin
WAKE Pin
• SOA3 = 1. The returned data contains the programmed
values in the UOVR register. Bit OD1 reflects the state of
the under-voltage protection, while bit OD0 reflects the
state of the over-voltage protection (refer to Table 16).
Previous Address SOA[2:0]=011
The data returned in bits OD1 and OD0 are current values
for the over-current fault blanking time, illustrated in Table 13.
Bit OD2 reports when the over-current detection timeout
feature is active. OD3 reports whether the open load circuitry
is active.
Previous Address SOA[2:0]=111
Null Data. No previous register Read Back command
received, so bits OD2, OD1, and OD0 are null, or 000.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
TYPICAL APPLICATIONS
LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
VPWR
VDD
Voltage
Regulator
VDD
VDD NC VPWR
VDD
VPWR
10 k
10 k
10
MCU
14
VDD
NC
VPWR
100nF
10µF
2.5µF
10nF
2
4
8
12
15
16
WAKE
IN
NC
HS
10k
10k
I/O
SCLK
CS
SCLK
10k
10k
7
3
33982
CS
I/O
RST
SO
11
HS
SI
10k
9
5
1
6
SO
I/O
SI
FS
LOAD
A/D
CSNS
FSI
13
GND
1k
RFS
Figure 12. Typical Applications
The loads must be chosen in order to guarantee the device
normal operating condition for junction temperatures from -40
to 150°C. In case of permanent short-circuit conditions, the
duration and number of activation cycles must be limited with
a dedicated MCU fault management, using the fault reporting
through the SPI. When driving DC motor or Solenoid loads
demanding multiple switching, an external recirculation
device must be used to maintain the device in its Safe
Operating Area.
• AN3274, which proposes safe configurations of the
eXtreme Switch devices in case of application faults, and
to protect all circuitry with minimum external components.
• AN2469, which provides guidelines for Printed Circuit
Board (PCB) design and assembly.
Development effort will be required by the end users to
optimize the board design and PCB layout, in order to reach
electromagnetic compatibility standards (emission and
immunity).
Two application notes are available:
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
28
PACKAGING
SOLDERING INFORMATION
PACKAGING
SOLDERING INFORMATION
• Convection: 225°C +5.0/-0°C
SOLDERING INFORMATION
• Vapor Phase Reflow (VPR): 215°C to 219°C
• Infrared (IR)/Convection: 225°C +5.0/-0°C
The 33982 is packaged in a surface mount power package
intended to be soldered directly on the printed circuit board.
The maximum peak temperature during the soldering
process should not exceed 230°C. The time at maximum
temperature should range from 10 to 40 s maximum.
The 33982 was qualified in accordance with JEDEC
standards JESD22-A113-B and J-STD-020A. The
recommended reflow conditions are as follows:
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS
For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ARL10596D.
PNA SUFFIX
16-PIN PQFN
NONLEADED PACKAGE
98ARL10521D
ISSUE C
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
30
PACKAGING
PACKAGE DIMENSIONS
PACKAGE DIMENSIONS (CONTINUED)
PNA SUFFIX
16-PIN PQFN
NONLEADED PACKAGE
98ARL10521D
ISSUE C
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
ADDITIONAL DOCUMENTATION
33982
THERMAL ADDENDUM (REV 3.0)
Introduction
This thermal addendum is provided as a supplement to the 33982 technical
datasheet. The addendum provides thermal performance information that may be
critical in the design and development of system applications. All electrical,
application, and packaging information is provided in the datasheet.
High Side Switch
Packaging and Thermal Considerations
This package is a dual die package. There are two heat sources in the package
independently heating with P1 and P2. This results in two junction temperatures,
TJ1 and TJ2, and a thermal resistance matrix with RθJAmn
.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
PNA SUFFIX
98ARL10521D
16-PIN PQFN
12 mm x 12 mm
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to RθJ21
and RθJ22, respectively.
Note For package dimensions, refer to
the 33982 data sheet.
RθJA11 RθJA12
RθJA21 RθJA22
TJ1
TJ2
P1
P2
.
=
The stated values are solely for a thermal performance comparison of one
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the
standards listed below.
Standards
Table 19. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Resistance
1.0
(1), (2)
R
R
R
R
20
6
16
2.0
40
39
26
73
1.0
0.2
θJAmn
1.0
(2), (3)
θJBmn
(1), (4)
53
θJAmn
0.2
(5)
<0.5
0.0
θJCmn
* All measurements
are in millimeters
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
Note: Recommended via diameter is 0.5 mm. PTH (plated through
hole) via must be plugged / filled with epoxy or solder mask in order
to minimize void formation and to avoid any solder wicking into the
via.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
Figure 13. Surface Mount for Power PQFN
with Exposed Pads
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
32
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
Transparent Top View
A
12 11 10
9
8
7
6
5
4
3
2
1
13
GND
A
14
VPWR
15
HS
16
HS
33982 Pin Connections
16-Pin PQFN
0.90 mm Pitch
12.0 mm x 12.0 mm Body
Figure 14. Thermal Test Board
Table 20. Thermal Resistance Performance
Device on Thermal Test Board
1 = Power Chip, 2 = Logic Chip (°C/W)
Material:
Single layer printed circuit board
FR4, 1.6 mm thickness
Area A
(mm2)
Thermal
Resistance
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
Cu traces, 0.07 mm thickness
0
55
41
39
42
32
29
74
66
65
Outline:
Area A:
80 mm x 100 mm board area,
including edge connector for thermal
testing
300
600
R
θJAmn
Cu heat-spreading areas on board
surface
RθJA is the thermal resistance between die junction and
ambient air.
Ambient Conditions: Natural convection, still air
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 3.0)
80
70
60
50
40
30
20
10
0
R
R
x
θ
θ
JA11
JA22
R
JA12 = R
θ
θJA21
0
300
600
Heat spreading area [mm²]
A
Figure 15. Device on Thermal Test Board RθJA
100
10
1
R
x
θ
JA11
JA22
R
θ
R
JA12 = R
θJA21
θ
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time(s)
Figure 16. Transient Thermal Resistance RθJA (1.0 W Step Response)
Device on Thermal Test Board Area A = 600(mm2)
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
34
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
Implemented Revision History page
Deletion of MC33982 part number, replaced with MC33982B.
2/2006
10
•
•
•
•
•
•
Corrected Pin Connections to the proper case outline
Added final sentence to Open Load Fault (Non-Latching)
Corrected heading labels on Input Timing Switching Characteristics
Changed labels in the Typical Applications drawing
Corrected Package Dimensions to Revision C
5/2006
11
Added Thermal Addendum (Rev 3.0).
1/2007
7/2007
•
Added RoHS logo to the data sheet
12
13
•
•
Added Functional Internal Block Description
Minor corrections to Serial Output Bit Map Descriptions and Device Behavior in Case of Under-
voltage
•
•
Changed the labeling header on DYNAMIC Electrical Characteristics from 150 to 125 degrees C
Updated Freescale form and style
6/2008
14
7/2009
•
Added Current Sense Leakage to Static Electrical Characteristics table (Table 3).
15.0
16.0
•
•
Added MC33982C to the ordering information
Added a Device Variations table
10/2009
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
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MC33982
Rev. 16.0
11/2009
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