MC56F8036VLF [FREESCALE]
16-bit Digital Signal Controllers; 16位数字信号控制器型号: | MC56F8036VLF |
厂家: | Freescale |
描述: | 16-bit Digital Signal Controllers |
文件: | 总164页 (文件大小:2686K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
56F8036
Data Sheet
Preliminary Technical Data
56F8000
16-bit Digital Signal Controllers
MC56F8036
Rev. 3
01/2007
freescale.com
Document Revision History
Version History
Rev. 0
Description of Change
Initial public release.
Rev. 1
• In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-21 as follows:
Old values: 1 μs typical, 2 μs maximum
New values: 35 ns typical, 45 ns maximum
Rev. 2
Rev. 3
In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.
Added the following note to the description of the TMS signal in Table 2-3:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8036 Data Sheet, Rev. 3
2
FreescaleSemiconductor
Preliminary
56F8036 General Description
• Up to 32 MIPS at 32MHz core frequency
• One Queued Serial Peripheral Interface (QSPI)
• DSP and MCU functionality in a unified,
C-efficient architecture
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• 64KB (32K x 16) Program Flash
• One 16-bit Quad Timer clocked at up to 96MHz
2
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module clocked at up to 96MHz
• One Inter-Integrated Circuit (I C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Two independent 5-channel 12-bit high-speed
Analog-to-Digital Converters (ADCs)
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• Two internal 12-bit Digital-to-Analog Converters
(DACs)
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• Up to 39 GPIO lines
• 48-pin LQFP Package
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
RESET or
GPIOA
V
2
V
2
V
V
V
SSA
CAP
DD
SS
DDA
4
3
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Low-Voltage
Supervisor
Analog Reg
PWM
or TMRA or CMP
or GPIOA
11
16-Bit
56800E Core
Data ALU
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Bit
Manipulation
Unit
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
PAB
PDB
CDBR
CDBW
DAC
AD0
5
5
Memory
R/W Control
ADC
or CMP
XDB2
XAB1
XAB2
Program Memory
32K x 16 Flash
or GPIOC
System Bus
Control
AD1
PAB
Unified Data /
Program RAM
4K x 16
PDB
CDBR
CDBW
Programmable
Interval
Timer
IPBus Bridge (IPBB)
QSCI
QSPI
2
or PWM
I C
or PWM
2
or CAN
or CMP
or GPIOB
or I C
2
or I C
XTAL, CLKIN, or
GPIOD
P
or TMRA
or GPIOB
System
Integration
Module
or TMRA
or GPIOB
Interrupt
Controller
COP/
Watchdog
O
O
S
C
Clock
Generator*
R
EXTAL or GPIOD
*Includes On-Chip
Relaxation Oscillator
4
4
3
56F8036 Block Diagram
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
3
56F8036 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
Part 8: General Purpose
Input/Output (GPIO) . . . . . . . . . . . . 114
1.1. 56F8036 Features . . . . . . . . . . . . . . . . . . . . . 5
1.2. 56F8036 Description . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Developme . nt Environment 8
1.4. Architecture Block Diagram 8
1.5. Product Documentation . . . . . . . . . . . . . . . 16
1.6. Data Sheet Conventions. . . . . . . . . . . . . . . 16
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 114
8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . 114
8.3. Reset Values . . . . . . . . . . . . . . . . . . . . . . . 117
Part 9: Joint Test Action Group (JTAG). . 122
9.1. 56F8036 Informatio . . . . . . . . . . . . . . . . .n 122
Part 2: Signal/Connection Descriptions . . 17
2.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2. 56F8036 Signal Pins . . . . . . . . . . . . . . . . . 21
Part 10: Specifications . . . . . . . . . . . . . . . .122
10.1. General Characteristics . . . . . . . . . . . . . . 122
10.2. DC Electrical Characteristics . . . . . . . . . . 126
10.3. AC Electrical Characteristics . . . . . . . . . . 129
10.4. Flash Memory Characteristics . . . . . . . . . 129
10.5. External Clock Operation Timing . . . . . . . 130
10.6. Phase Locked Loop Timing . . . . . . . . . . . 131
10.7. Relaxation Oscillator Timing. . . . . . . . . . . 131
10.8. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 133
Part 3: OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 33
3.4. Internal Clock Source . . . . . . . . . . . . . . . . . 34
3.5. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 34
3.6. Ceramic Resonator . . . . . . . . . . . . . . . . . . . 35
3.7. External Clock Input - Crystal
10.9. Serial Peripheral Interface (SPI) Timing . 134
10.10. Quad Timer Timing. . . . . . . . . . . . . . . . . 137
10.11. Serial Communication Interface
Oscillator Option. . . . . . . . . . . . . . 35
3.8. Alternate External Clock Input . . . . . . . . . . . 36
(SCI) Timing. . . . . . . . . . . . . . . . . 138
10.12. Freescale’s Scalable Controller
Area Network (MSCAN) Timing. . 139
10.13. Inter-Integrated Circuit Interface
(I2C) Timing . . . . . . . . . . . . . . . . 139
10.14. JTAG Timing. . . . . . . . . . . . . . . . . . . . . . 141
10.15. Analog-to-Digital Converter
Part 4: Memory Maps . . . . . . . . . . . . . . . . . 36
4.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2. Interrupt Vector Table . . . . . . . . . . . . . . . . . 37
4.3. Program Map . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5. EOnCE Memory Map . . . . . . . . . . . . . . . . . 41
4.6. Peripheral Memory-Mapped Registers. . . . 42
(ADC) Parameters . . . . . . . . . . . . 142
10.16. Equivalent Circuit for ADC Inputs. . . . . . 143
10.17. Comparator (CMP) Parameters . . . . . . . 143
10.18. Digital-to-Analog Converter
(DAC) Parameters . . . . . . . . . . . 144
10.19. Power Consumption . . . . . . . . . . . . . . . 145
Part 5: Interrupt Controller (ITCN) . . . . . . . 56
5.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3. Functional Description . . . . . . . . . . . . . . . . . 56
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 58
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 59
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 59
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Part 11: Packaging . . . . . . . . . . . . . . . . . . .147
11.1. 56F8036 Package and
Pin-Out Information . . . . . . . . . . . 147
Part 6: System Integration Module (SIM) . . 79
6.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3. Register Descriptions . . . . . . . . . . . . . . . . . 81
6.4. Clock Generation Overview . . . . . . . . . . . . 107
6.5. Power-Saving Modes . . . . . . . . . . . . . . . . 108
6.6. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.7. Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 112
Part 12: Design Considerations . . . . . . . . 150
12.1. Thermal Design Considerations . . . . . . . . 150
12.2. Electrical Design Considerations . . . . . . . 151
Part 13: Ordering Information. . . . . . . . . . 152
Part 14: Appendix. . . . . . . . . . . . . . . . . . . . 153
Part 7: Security Features . . . . . . . . . . . . . 112
7.1. Operation with Security Enabled . . . . . . . 112
7.2. Flash Access Lock and
Unlock Mechanisms. . . . . . . . . . 113
56F8036 Data Sheet, Rev. 3
4
FreescaleSemiconductor
Preliminary
56F8036 Features
Part 1 Overview
1.1 56F8036 Features
1.1.1
Digital Signal Controller Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture
As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency
Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
32-bit arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time
debugging
1.1.2
Memory
•
•
•
Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security and protection that prevent unauthorized users from gaining access to the internal Flash
On-chip memory
— 64KB of Program Flash
— 8KB of Unified Data/Program RAM
•
EEPROM emulation capability using Flash
1.1.3
Peripheral Circuits for 56F8036
One multi-function six-output Pulse Width Modulator (PWM) module
— Up to 96MHz PWM operating clock
•
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Four programmable fault inputs with programmable digital filter
— Double-buffered PWM registers
— Each complementary PWM signal pair allows selection of a PWM supply source from:
– PWM generator
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
5
– External GPIO
– Internal timers
– Analog comparator outputs
– ADC conversion result which compares with values of ADC high- and low-limit registers to set
PWM output
•
Two independent 12-bit Analog-to-Digital Converters (ADCs)
— 2 x 5 channel inputs
— Supports both simultaneous and sequential conversions
— ADC conversions can be synchronized by both PWM and timer modules
— Sampling rate up to 2.67MSPS
— 16-word result buffer registers
•
•
Two internal 12-bit Digital-to-Analog Converters (DACs)
— 2 microsecond settling time when output swing from rail to rail
— Automatic waveform generation generates square, triangle and sawtooth waveforms with
programmable period, update rate, and range
One 16-bit multi-purpose Quad Timer module (TMR)
— Up to 96MHz operating clock
— Eight independent 16-bit counter/timers with cascading capability
— Each timer has capture and compare capability
— Up to 12 operating modes
•
•
One Queued Serial Communication Interface (QSCI) with LIN Slave functionality
— Full-duplex or single-wire operation
— Two receiver wake-up methods:
– Idle line
– Address mark
— Four-bytes-deep FIFOs are available on both transmitter and receiver
One Queued Serial Peripheral Interfaces (QSPI)
— Full-duplex operation
— Master and slave modes
— Four-words-deep FIFOs available on both transmitter and receiver
— Programmable Length Transactions (2 to 16 bits)
•
•
One Inter-Integrated Circuit (I2C) port
— Operates up to 400kbps
— Supports both master and slave operation
— Supports both 10-bit address mode and broadcasting mode
One Freescale scalable controller area network (MSCAN) module
56F8036 Data Sheet, Rev. 3
6
FreescaleSemiconductor
Preliminary
56F8036 Description
— Fully compliant with CAN protocol - Version 2.0 A/B
— Supports standard and extended data frames
— Supports data rate up to 1Mbps
— Five receive buffers and three transmit buffers
Three 16-bit Programmable Interval Timers (PITs)
Two analog Comparators (CMPs)
•
•
— Selectable input source includes external pins, DACs
— Programmable output polarity
— Output can drive Timer input, PWM fault input, PWM source, external pin output and trigger ADCs
— Output falling and rising edge detection able to generate interrupts
Computer Operating Properly (COP)/Watchdog timer capable of selecting different clock sources
Up to 39 General-Purpose I/O (GPIO) pins with 5V tolerance
•
•
•
•
•
Integrated Power-On Reset (POR) and Low-Voltage Interrupt (LVI) module
Phase Lock Loop (PLL) provides a high-speed clock to the core and peripherals
Clock sources:
— On-chip relaxation oscillator
— External clock: crystal oscillator, ceramic resonator and external clock source
JTAG/EOnCE debug programming interface for real-time debugging
•
1.1.4
Energy Information
•
•
•
•
•
Fabricated in high-density CMOS with 5V tolerance
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8036 Description
The 56F8036 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). It
combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with
a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8036 is well-suited for many applications.
The 56F8036 includes many peripherals that are especially useful for industrial control, motion control,
home appliances, general purpose inverters, smart sensors, fire and security systems, switched-mode
power supply, power management, and medical monitoring applications.
The 56800E core is based on a dual Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient, compact
DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
7
development of optimized control applications.
The 56F8036 supports program execution from internal memories. Two data operands can be accessed
from the on-chip data RAM per instruction cycle. The 56F8036 also offers up to 39 General Purpose
Input/Output (GPIO) lines, depending on peripheral configuration.
The 56F8036 Digital Signal Controller includes 64KB of Program Flash and 8KB of Unified
Data/Program RAM. Program Flash memory can be independently bulk erased or erased in pages.
Program Flash page erase size is 512 Bytes (256 Words).
A full set of programmable peripherals—PWM, ADCs, QSCI, QSPI, I2C, PITs, Quad Timers, DACs, and
analog comparators—supports various applications. Each peripheral can be independently shut down to
save power. Any pin in these peripherals can also be used as General Purpose Input/Outputs (GPIOs).
1.3 Award-Winning Development Environment
TM
Processor Expert
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit and
development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs
create a complete, scalable tools solution for easy, fast, and efficient development.
1.4 Architecture Block Diagram
The 56F8036’s architecture is shown in Figures 1-1, 1-2, 1-3, 1-4, 1-5, 1-6, and 1-7. Figure 1-1 illustrates
how the 56800E system buses communicate with internal memories and the IPBus Bridge and the internal
connections between each unit of the 56800E core. Figure 1-2 shows the peripherals and control blocks
connected to the IPBus Bridge. Figures 1-3, 1-4, 1-5, 1-6 and 1-7 detail how the device’s I/O pins are
muxed. Please see Part 2, Signal/Connection Descriptions, for information about which signals are
multiplexed with those of other peripherals.
1.4.1
PWM, TMR and ADC Connections
Figure 1-3 shows the over- and under-voltage connections from the ADC to the PWM and the connections
to the PWM from the TMR and GPIO. These signals can control the complementary PWM outputs in a
similar manner to the over- and under-voltage control signals. See the 56F802X and 56F803XPeripheral
Reference Manual for additional information.
The PWM_reload_sync output can be connected to Timer A’s (TMRA) Channel 3 input; TMRA’s
Channels 2 and 3 outputs are connected to the ADC sync inputs. TMRA Channel 3 output is connected to
SYNC0 and TMRA Channel 2 is connected to SYNC1. SYNC0 is the master ADC sync input that is used
to trigger ADCA and ADCB in sequence and parallel mode. SYNC1 is used to trigger ADCB in parallel
independent mode. These are controlled by bits in the SIM Control Register; see Section 6.3.1.
56F8036 Data Sheet, Rev. 3
8
FreescaleSemiconductor
Preliminary
Architecture Block Diagram
DSP56800E Core
Program Control Unit
ALU1
ALU2
Address
PC
LA
LA2
Generation
Unit
Instruction
Decoder
R0
R1
(AGU)
HWS0
HWS1
FIRA
R2
R3
Interrupt
Unit
Program
Memory
M01
N3
OMR
R4
R5
N
SR
LC
LC2
Looping
Unit
SP
FISR
XAB1
XAB2
PAB
Data /
Program
RAM
PDB
CDBW
CDBR
XDB2
A2
B2
C2
D2
A1
B1
C1
D1
Y1
Y0
X0
A0
B0
C0
D0
Bit-
Manipulation
Unit
IPBUS
Interface
Y
Data
Enhanced
OnCE™
Arithmetic
Logic Unit
(ALU)
JTAG TAP
MAC and ALU
Multi-Bit Shifter
Figure 1-1 56800E Core Block Diagram
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
9
To/From IPBus Bridge
OCCS
Interrupt
(ROSC / PLL /
OSC)
Controller
Low-Voltage Interrupt
POR & LVI
System POR
GPIO A
GPIO B
GPIO C
GPIO D
RESET
SIM
(Muxed with GPIOA7)
COP Reset
COP
IPBus
(Continues on Figure 1-3)
Figure 1-2 Peripheral Subsystem
56F8036 Data Sheet, Rev. 3
10
FreescaleSemiconductor
Preliminary
Architecture Block Diagram
To/From IPBus Bridge
IPBus
INTC
SYNC
MSTR_CNT_EN
PIT0
3
DAC SYNC on Figure 1-5
MSTR_CNT_EN
SYNC
SYNC
PIT1
MSTR_CNT_EN
PIT2
2
3
SYNC0, SYNC1 on Figure 1-7
LIMIT on Figure 1-6
Sync0, Over/Under
ANA0
ANA0 on Figure 1-5
Sync1
Limits
GPIOC2
GPIOC3
GPIOC8
GPIOC1
ANA2 (VREFHA
ANA3 (VREFLA
)
)
ANA4
ANA1
ADC
ANB0
ANB0 on Figure 1-5
GPIOC6
GPIOC7
GPIOC12
ANB2 (VREFHA
ANB3 (VREFLB
)
)
ANB4
ANB1
GPIOC5
Figure 1-3 56F8036 I/O Pin-Out Muxing (Part 1/5)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
11
To/From IPBus Bridge
RXD0, TXD0
2
QSCI0
GPIOB6 - 7
GPIOB2 - 3
TA2, TA3 on Figure 1-7
MISO0, MOSI0
2
QSPI0
I2C
SCLK0, SS0
SCL, SDA
2
2
2
GPIOB0 - 1
GPIOB8 - 9
2
2
CANTX, CANRX
2
MSCAN
IPBus
Figure 1-4 56F8036 I/O Pin-Out Muxing (Part 2/5)
56F8036 Data Sheet, Rev. 3
12
FreescaleSemiconductor
Preliminary
Architecture Block Diagram
To/From IPBus Bridge
FAULT1 on Figure 1-6
TA2 on Figure 1-7
GPIOA8
GPIOC0
CMPAI1
CMPAI3
CMP_IN1
CMP_IN3
CMPA
CMP_OUT
CMPAO on Figure 1-6, Figure 1-7
CMPAI2
GPIOA10
GPIOB10
CMP_IN2
Export Import
ANA0 on Figure 1-3
DAC0
2
TA0o, TA1o on Figure 1-7
3
DAC SYNC on Figure 1-3
RELOAD on Figure 1-6
DAC1
GPIOB11
GPIOA11
ANB0 on Figure 1-3
Import Export
CMP_IN2
CMPBI2
CMP_OUT
CMPBO on Figure 1-6, Figure 1-7
CMPB
GPIOC4
GPIOA9
CMPBI3
CMPBI1
CMP_IN3
CMP_IN1
TA3 on Figure 1-7
FAULT2 on Figure 1-6
IPBus
Figure 1-5 56F8036 I/O Pin-Out Muxing (Part 3/5)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
13
To/From IPBus Bridge
TA0 on Figure 1-7
GPIOA6
2
TA2 - 3 on Figure 1-7
GPIOA0 - 3
4
PWM0 - 3
FAULT0
GPIOA4 - 5
2
2
PWMA4 - 5
1
PWM
FAULT1
FAULT1 on Figure 1-5
FAULT2
FAULT3
1
RELOAD PSRC0 - 1
FAULT2 on Figure 1-5
TA1 on Figure 1-7
GPIOB5
CMPAO on Figure 1-5
CMPBO on Figure 1-5
IPBus
3
2
GPIOB2 - 3 on Figure 1-4
LIMIT on Figure 1-3
3
3
TA0o, TA2o, TA3 o on Figure 1-3
Figure 1-6 56F8036 I/O Pin-Out Muxing (Part 4/5)
56F8036 Data Sheet, Rev. 3
14
FreescaleSemiconductor
Preliminary
Architecture Block Diagram
To/From IPBus Bridge
TA0o on Figure 1-6 (PWM)
TA0 on Figure 1-6 (GPIOA6)
T0o
T0i
T1o
T1i
TA1 on Figure 1-6 (GPIOB5)
CMPAO on Figure 1-6 (CMPA)
SYNC1 on Figure 1-3 (ADC)
TA2o on Figure 1-6 (PWM)
TA2 on Figure 1-6 (GPIOA4)
TMRA
T2o
T2i
TA2 on Figure 1-5 (GPIOA8)
TA2 on Figure 1-4 (GPIOB2)
CMPBO on Figure 1-6 (CMPB)
SYNC0 on Figure 1-3 (ADC)
TA3o on Figure 1-6 (PWM)
TA2 on Figure 1-6 (GPIOA5)
T3o
T3i
TA3 on Figure 1-5 (GPIOA9)
TA2 on Figure 1-4 (GPIOB3)
RELOAD on Figure 1-6 (PWM)
IPBus
Figure 1-7 56F8036 I/O Pin-Out Muxing (Part 5/5)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
15
1.5 Product Documentation
The documents listed in Table 1-1 are required for a complete description and proper design with the
56F8036. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices,
Freescale Literature Distribution Centers, or online at:
http://www.freescale.com
Table 1-1 56F8036 Chip Documentation
Topic
DSP56800E
Description
Order Number
DSP56800ERM
Detailed description of the 56800E family architecture,
16-bit Digital Signal Controller core processor, and the
instruction set
Reference Manual
56F802X and
56F803XPeripheral
Reference Manual
Detailed description of peripherals of the 56F802x and
56F803x family of devices
MC56F80xxRM
56F801xBLUG
56F802x and 56F803x
Serial Bootloader User
Guide
Detailed description of the Serial Bootloader in the
56F801x family of devices
56F8036
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
MC56F8036
56F8036
Errata
Details any chip issues that might be present
MC56F8036E
1.6 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted”
“deasserted”
Examples:
A high true (active high) signal is high or a low true (active low) signal is low.
A high true (active high) signal is low or a low true (active low) signal is high.
Voltage1
Signal/Symbol
Logic State
True
Signal State
Asserted
PIN
PIN
PIN
PIN
VIL/VOL
False
Deasserted
Asserted
VIH/VOH
VIH/VOH
VIL/VOL
True
False
Deasserted
1. Values for V , V , V , and V are defined by individual product specifications.
IL
OL
IH
OH
56F8036 Data Sheet, Rev. 3
16
FreescaleSemiconductor
Preliminary
Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8036 are organized into functional groups, as detailed in Table 2-1.
Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present
on a pin, sorted by pin number.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power Inputs (VDD, VDDA
Number of Pins
)
3
4
Ground (VSS, VSSA
Supply Capacitors
Reset1
)
2
1
Pulse Width Modulator (PWM) Ports1
Queued Serial Peripheral Interface (QSPI) Ports1
Timer Module A (TMRA) Ports1
12
4
4
Analog-to-Digital Converter (ADC) Ports1
Queued Serial Communications Interface 0 (QSCI0) Ports1
MSCAN Ports1
10
2
2
Inter-Integrated Circuit Interface (I2C) Ports1
Oscillator Signals1
2
2
JTAG/Enhanced On-Chip Emulation (EOnCE)1
4
1. Pins may be shared with other peripherals; see Table 2-2.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
17
In Table 2-2, peripheral pins in bold identify reset state.
Table 2-2 56F8036 Pins
Peripherals:
Pin
#
Quad
Timer
Power&
Ground
Pin Name
GPIOB6
Signal Name
GPIO I2C
QSCI
QSPI
ADC
PWM
Comp
MSCAN
JTAG
Misc
1
GPIOB6, RXD0,
SDA, CLKIN
B6
SDA RXD0
CLKIN
2
3
4
GPIOB1
GPIOB7
GPIOB5
GPIOB1, SS0, SDA
GPIOB7, TXD0, SCL
B1
B7
B5
SDA
SS0
SCL TXD0
GPIOB5, TA1,
FAULT3, CLKIN
FAULT3 TA1
FAULT2 TA3
CLKIN
5
GPIOA9
GPIOA9, FAULT2,
TA3, CMPBI1
A9
CMPBI1
CMPBI2
6
7
8
GPIOA11 GPIOA11, CMPBI2
GPIOC12 GPIOC12, ANB4
A11
C12
C4
ANB4
ANB0
GPIOC4
GPIOC4, ANB0,
CMPBI3
CMPBI3
9
GPIOC5
GPIOC5, ANB1
GPIOC6, ANB2,
C5
C6
ANB1
ANB2
10 GPIOC6
V
V
REFHB
REFHB
11 GPIOC7
GPIOC7, ANB3,
C7
ANB3
V
V
V
V
REFLB
REFLB
12 VDDA
13 VSSA
14 GPIOC3
V
DDA
DDA
V
SSA
SSA
GPIOC3, ANA3,
V
C3
C2
ANA3
V
REFLA
REFLA
15 GPIOC2
GPIOC2, ANA2,
ANA2
V
V
REFHA
REFHA
ANA1
ANA0
16 GPIOC1
17 GPIOC0
GPIOC1, ANA1
C1
C0
GPIOC0, ANA0,
CMPAI3
CMPAI3
18 GPIOC8
19 VSS
GPIOC8, ANA4
C8
ANA4
V
V
V
SS
SS
20 VCAP
21 TCK
V
CAP
CAP
TCK, GPIOD2
D2
B10
A7
TCK
22 GPIOB10 GPIOB10, CMPAO,
CMPAO
23 RESET
24 GPIOB3
RESET, GPIOA7
RESET
GPIOB3, MOSI0,
TA3, PSRC1
B3
MOSI0
MISO0
PSRC1
PSRC0
TA3
TA2
25 GPIOB2
26 GPIOA6
GPIOB2, MISO0,
TA2, PSRC0
B2
A6
GPIOA6, FAULT0,
TA0
FAULT0 TA0
27 GPIOA10 GPIOA10, CMPAI2
A10
CMPAI2
56F8036 Data Sheet, Rev. 3
18
FreescaleSemiconductor
Preliminary
Introduction
Table 2-2 56F8036 Pins (Continued)
Peripherals:
Pin
#
Quad
Timer
Power&
Ground
Pin Name
Signal Name
GPIO I2C
A8
QSCI
QSPI
ADC
PWM
Comp
MSCAN
JTAG
Misc
28 GPIOA8
29 GPIOA5
GPIOA8, FAULT1,
TA2, CMPAI1
FAULT1 TA2
CMPAI1
GPIOA5, PWM5,
TA3, FAULT2
A5
PWM5
FAULT2
TA3
30 VSS
V
V
V
SS
SS
DD
31 VDD
V
DD
32 GPIOB0
GPIOB0, SCLK0,
SCL
B0
A4
B9
SCL
SDA
SCLK0
33 GPIOA4
34 GPIOB9
GPIOA4, PWM4,
TA2, FAULT1
PWM4
TA2
FAULT1
GPIOB9, SDA,
CANRX
CANRX
35 GPIOA2
36 GPIOA3
37 VCAP
GPIOA2, PWM2
GPIOA3, PWM3
A2
A3
PWM2
PWM3
V
V
V
V
CAP
CAP
DD
38 VDD
V
DD
39 VSS
V
SS
SS
40 GPIOD5
GPIOD5, XTAL,
CLKIN
D5
XTAL
CLKIN
41 GPIOD4
42 GPIOB8
GPIOD4, EXTAL
D4
B8
EXTAL
GPIOB8, SCL,
CANTX
SCL
CANTX
43 GPIOA1
44 GPIOA0
45 TDI
GPIOA1, PWM1
GPIOA0, PWM0
TDI, GPIOD0
A1
A0
PWM1
PWM0
D0
TD1
46 GPIOB11 GPIOB11, CMPBO
B11
D3
CMPBO
47 TMS
48 TDO
TMS, GPIOD3
TDO, GPIOD1
TMS
TDO
D1
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
19
VDD
VSS
GPIOA0-3 (PWM0-3)
Power
Ground
Power
4
1
1
1
1
2
3
GPIOA4 (PWM4, TA2, FAULT1)
GPIOA5 (PWM5, TA3, FAULT2)
GPIOA6 (FAULT0, TA0)
VDDA
1
1
PWM
VSSA
or TMRA
or CMP
or QSPI
or GPIOA
Ground
GPIOA8 (FAULT1, TA2, CMPAI1)
Other
Supply
Ports
56F8036
VCAP
2
GPIOA9 (FAULT2, TA3, CMPBI1)
GPIOA10 (CMPAI2)
1
1
1
GPIOD4 (EXTAL)
OSC Port
or GPIO
1
1
GPIOA11 (CMPBI2)
GPIOD5 (XTAL, CLKIN)
RESET
or GPIOA
RESET (GPIOA7)
1
GPIOB0 (SCLK0, SCL)
GPIOB1 (SS0, SDA)
1
1
QSPI
or I2C
or PWM
or TMRA
or GPIOB
GPIOB2 (MISO0, TA2, PSRC0)
GPIOB3 (MOSI0, TA3, PSRC1)
GPIOB10 (CMPAO)
GPIOB11 (CMPBO)
1
1
1
1
1
CAN
or CMP
or GPIOB
1
GPIOB8 (SCL, CANTX)
GPIOB9 (SDA, CANRX)
QSCI
or PWM
or I2C
or TMRA
or TMRB
or QSPI
or GPIOB
GPIOB5 (TA1, FAULT3, CLKIN)
GPIOB6 (RXD0, SDA, CLKIN)
GPIOB7 (TXD0, SCL)
1
1
GPIOC0 (ANA0 & CMPAI3)
GPIOC1 (ANA1)
1
1
1
1
GPIOC2 (ANA2, VREFHA
)
GPIOC3 (ANA3, VREFLA
GPIOC8 (ANA4)
)
1
1
ADC
or CMP
or QSCI1
or GPIOC
GPIOC4 (ANB0 & CMPBI3)
GPIOC5 (ANB1)
TDI (GPIOD0)
TDO (GPIOD1)
TCK (GPIOD2)
TMS (GPIOD3)
1
1
1
1
1
GPIOC6 (ANB2, VREFHB
)
JTAG/ EOnCE
or GPIOD
1
1
1
GPIOC7 (ANB3, VREFLB
GPIOC12 (ANB4)
)
1
Figure 2-1 56F8036 Signals Identified by Functional Group
56F8036 Data Sheet, Rev. 3
20
FreescaleSemiconductor
Preliminary
56F8036 Signal Pins
2.2 56F8036 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
VDD
VDD
VSS
31
38
19
30
39
12
Supply
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface.
Supply
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
VSS
VSS
VDDA
Supply
Supply
Supply
Supply
Supply
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VSSA
13
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
VCAP
VCAP
20
37
23
VCAP — Connect this pin to a 4.7μF or greater bypass capacitor in
order to bypass the core voltage regulator, required for proper chip
operation. See Section 10.2.1.
RESET
Input
Input,
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
(GPIOA7)
Input/Open
Drain
Output
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
21
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOA0
(PWM0)
GPIOA1
(PWM1)
GPIOA2
(PWM2)
GPIOA3
(PWM3)
44
43
35
36
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
PWM0 — This is one of the six PWM output pins.
After reset, the default state is GPIOA0.
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
PWM1 — This is one of the six PWM output pins.
After reset, the default state is GPIOA1.
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
PWM2 — This is one of the six PWM output pins.
After reset, the default state is GPIOA2.
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
PWM3 — This is one of the six PWM output pins.
After reset, the default state is GPIOA3.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
22
FreescaleSemiconductor
Preliminary
56F8036 Signal Pins
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOA4
33
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(PWM4)
(TA21)
Output
PWM4 — This is one of the six PWM output pins.
TA2 — Timer A, Channel 2
Input/
Output
(FAULT12)
Input
Fault1 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
After reset, the default state is GPIOA4. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
1The TA2 signal is also brought out on the GPIOA8-9 and GPIOB2-3 pins.
2The Fault1 signal is also brought out on the GPIOA8-9 and GPIOB10 pins.
GPIOA5
29
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(PWM5)
(TA33)
Output
PWM5 — This is one of the six PWM output pins.
TA3 — Timer A, Channel 3
Input/
Output
Input
Fault2 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
(FAULT24)
After reset, the default state is GPIOA5. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
3The TA3 signal is also brought out on the GPIOA8-9 and GPIOB2-3 pins.
4The Fault2 signal is also brought out on the GPIOA8-9 and GPIOB10 pins.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
23
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOA6
26
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(FAULT0)
(TA0)
Input
Fault0 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
TA0 — Timer A, Channel 0.
After reset, the default state is GPIOA6. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
GPIOA8
28
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(FAULT1)
(TA2)
Input
Fault1 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
Input/
TA2 — Timer A, Channel 2.
Output
(CMPAI1)
Input
Comparator A, Input 1 — This is an analog input to Comparator A.
After reset, the default state is GPIOA8. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
GPIOA9
5
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(FAULT2)
(TA3)
Input
Fault2 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
Input/
TA2 — Timer A, Channel 3.
Output
(CMPBI1)
Input
Comparator B, Input 1 — This is an analog input to Comparator B.
After reset, the default state is GPIOA9. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
24
FreescaleSemiconductor
Preliminary
56F8036 Signal Pins
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOA10
(CMPAI2)
27
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Input
Comparator A, Input 2 — This is an analog input to Comparator A.
After reset, the default state is GPIOA10. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
GPIOA11
(CMPBI2)
6
Input/
Output
Input,
internal
pull-up
enabled
Port A GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Input
Comparator B, Input 2 — This is an analog input to Comparator B.
After reset, the default state is GPIOA11. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
GPIOB0
(SCLK0)
32
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Input/
Output
QSPI0 Serial Clock — In the master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves as
the data clock input. A Schmitt trigger input is used for noise
immunity.
(SCL5)
Serial Clock — This pin serves as the I2C serial clock.
Input/
Output
After reset, the default state is GPIOB0. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
5The SCL signal is also brought out on the GPIOB7 pin.
GPIOB1
2
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(SS0)
Input/
QSPI0 Slave Select — SS is used in slave mode to indicate to the
Output
QSPI0 module that the current transfer is to be received.
(SDA6)
Serial Data — This pin serves as the I2C serial data line.
Input
After reset, the default state is GPIOB1. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
6The SDA signal is also brought out on the GPIOB6 pin.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
25
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOB2
25
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(MISO0)
Input/
Output
QSPI0 Master In/Slave Out — This serial data pin is an input to a
master device and an output from a slave device. The MISO line of a
slave device is placed in the high-impedance state if the slave device
is not selected. The slave device places data on the MISO line a
half-cycle before the clock edge the master device uses to latch the
data.
(TA27)
Input/
Output
TA2 — Timer A, Channel 2
Input
PSRC0 — External PWM signal source input for the complementary
PWM4/PWM5 pair.
(PSRC0)
After reset, the default state is GPIOB2. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
7The TA2 signal is also brought out on the GPIOA4 and GPIOA8 pins.
GPIOB3
24
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(MOSI0)
Input/
Output
QSPI0 Master Out/Slave In— This serial data pin is an output from
a master device and an input to a slave device. The master device
places data on the MOSI line a half-cycle before the clock edge the
slave device uses to latch the data.
(TA38)
Input/
Output
TA3 — Timer A, Channel 3
Input
PSRC1 — External PWM signal source input for the complementary
PWM2/PWM3 pair.
(PSRC1)
After reset, the default state is GPIOB3. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
8The TA3 signal is also brought out on the GPIOA5 and GPIOA9 pins.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
26
FreescaleSemiconductor
Preliminary
56F8036 Signal Pins
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOB5
4
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(TA1)
Input/
TA1 — Timer A, Channel 1
Output
(FAULT3)
(CLKIN)
Input
Input
FAULT3 — This fault input pin is used for disabling selected PWM
outputs in cases where fault conditions originate off-chip.
External Clock Input— This pin serves as an external clock input.
After reset, the default state is GPIOB5. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
GPIOB6
1
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(RXD0)
(SDA9)
Input
Receive Data 0 — QSCI0 receive data input.
Serial Data — This pin serves as the I2C serial data line.
Input/
Output
Input
(CLKIN)
External Clock Input — This pin serves as an external clock input.
After reset, the default state is GPIOB6. The peripheral functionality
is controlled via the SIM (See Section 6.3.16) and the CLKMODE bit
of the OCCS Oscillator Control Register.
9The SDA signal is also brought out on the GPIOB1 pin.
GPIOB7
3
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(TXD0)
Input/
Transmit Data 0 — QSCI0 transmit data output or transmit / receive
Output
in single wire operation.
(SCL10
)
Serial Clock — This pin serves as the I2C serial clock.
Input/
Output
After reset, the default state is GPIOB7. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
10The SCL signal is also brought out on the GPIOB0 pin.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
27
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOB8
42
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(SCL11
)
Serial Clock 1 — This pin serves as the I2C serial clock.
CAN Transmit Data — This is the SCAN interface output.
Input/
Output
Open Drain
Output
(CANTX12
)
After reset, the default state is GPIOB8. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
11The SCL signal is also brought out on the GPIOB0 and GPIOB7 pins.
12The CANTX signal is also brought out on the GPIOB12 pin.
GPIOB9
34
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
(SDA13
)
Serial Data 1 — This pin serves as the I2C serial data line.
CAN Receive Data — This is the MSCAN interface input.
Input/
Output
Input
(CANRX14
)
After reset, the default state is GPIOB9. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
13The SDA signal is also brought out on the GPIOB1 and GPIOB6 pins.
14The CANRX signal is also brought out on the GPIOB13 pin.
GPIOB10
(CMPAO)
22
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
Comparator A Output— This is the output of comparator A.
After reset, the default state is GPIOB10. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
GPIOB11
(CMPBO)
46
Input/
Output
Input,
internal
pull-up
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Output
Comparator B Output— This is the output of comparator B.
After reset, the default state is GPIOB11. The peripheral functionality
is controlled via the SIM. See Section 6.3.16.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
28
FreescaleSemiconductor
Preliminary
56F8036 Signal Pins
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOC0
17
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
(ANA0 &
CMPAI3)
Analog
Input
ANA0 — Analog input to ADC A, Channel 0.
Comparator A, Input 3 — This is an analog input to Comparator A.
When used as an analog input, the signal goes to both the ANA0
and CMPAI3.
After reset, the default state is GPIOC0.
GPIOC1
(ANA1)
16
15
Input/
Output
Input
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANA1 — Analog input to ADC A, Channel 1.
After reset, the default state is GPIOC1.
GPIOC2
(ANA2)
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANA2 — Analog input to ADC A, Channel 2.
(VREFHA
)
Analog
Input
VREFHA — Analog reference voltage high (ADC A).
After reset, the default state is GPIOC2.
GPIOC3
(ANA3)
14
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANA3 — Analog input to ADC A, Channel 3.
(VREFLA
)
Analog
Input
VREFLA — Analog reference voltage low (ADC A).
After reset, the default state is GPIOC3.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
29
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOC4
8
Input/
Input
Port C GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
(ANB0 &
CMPBI3)
Analog
Input
ANB0 — Analog input to ADC B, Channel 0.
Comparator B, Input 3 — This is an analog input to Comparator B.
When used an analog input, the signal goes to both the ANB0 and
CMPBI3.
After reset, the default state is GPIOC4.
GPIOC5
(ANB1)
9
Input/
Output
Input
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB1 — Analog input to ADC B, Channel 1.
After reset, the default state is GPIOC5.
GPIOC6
(ANB2)
10
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB2 — Analog input to ADC B, Channel 2.
(VREFHB
)
Input
VREFHB — Analog reference voltage high (ADC B).
After reset, the default state is GPIOC6.
GPIOC7
(ANB3)
11
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB3 — Analog input to ADC B, Channel 3.
(VREFLB
)
Input
VREFLB — Analog reference voltage low (ADC B).
After reset, the default state is GPIOC7.
GPIOC8
(ANA4)
18
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANA4 — Analog input to ADC A, Channel 4.
After reset, the default state is GPIOC8.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
30
FreescaleSemiconductor
Preliminary
56F8036 Signal Pins
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
GPIOC12
(ANB4)
7
Input/
Output
Input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
ANB4 — Analog input to ADC B, Channel 4.
After reset, the default state is GPIOC12.
GPIOD4
(EXTAL)
41
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. Tie this pin low if XTAL is being driven by
an external clock source.
After reset, the default state is GPIOD4.
GPIOD5
(XTAL)
40
Input/
Output
Input
Port D GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Analog
Input/
External Crystal Oscillator Output — This output connects the
internal crystal oscillator output to an external crystal.
Output
(CLKIN)
TDI
Input
External Clock Input — This pin serves as an external clock input.
After reset, the default state is GPIOD5.
45
Input
Input,
internal
pull-up
enabled
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
(GPIOD0)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is TDI.
TDO
48
Output
Output
Test Data Output — This tri-stateable output pin provides a serial
tri-stated, output data stream from the JTAG/EOnCE port. It is driven in the
internal
pull-up
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
enabled
(GPIOD1)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is TDO.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
31
Table 2-3 56F8036 Signal and Package Information for the 48-Pin LQFP (Continued)
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
TCK
21
Input
Input,
internal
pull-up
enabled
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-up resistor. A Schmitt
trigger input is used for noise immunity.
(GPIOD2)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is TCK.
TMS
47
Input
Input,
internal
pull-up
enabled
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
(GPIOD3)
Input/
Port D GPIO — This GPIO pin can be individually programmed as
Output
an input or output pin.
After reset, the default state is TMS.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
Return to Table 2-2
56F8036 Data Sheet, Rev. 3
32
FreescaleSemiconductor
Preliminary
Overview
Part 3 OCCS
3.1 Overview
The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an
external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to
32MHz. For details, see the OCCS chapter in the 56F802X and 56F803XPeripheral Reference Manual.
3.2 Features
The OCCS module interfaces to the oscillator and PLL and offers these features:
•
•
•
•
•
•
Internal relaxation oscillator
Ability to power down the internal relaxation oscillator or crystal oscillator
Ability to put the internal relaxation oscillator into Standby mode
3-bit postscaler provides control for the PLL output
Ability to power down the PLL
Provides a 2X system clock which operates at twice the system clock to the System Integration Module
(SIM)
•
•
•
Provides a 3X system clock which operates at three times the system clock to PWM and Timer modules
Safety shutdown feature is available if the PLL reference clock is lost
Can be driven from an external clock source
The clock generation module provides the programming interface for the PLL, internal relaxation
oscillator, and crystal oscillator.
3.3 Operating Modes
In 56F8000 family devices, an internal oscillator, an external crystal, or an external clock source can be
used to provide a reference clock to the SIM.
The 2X system clock source output from the OCCS can be described by one of the following equations:
2X system frequency = oscillator frequency
2X system frequency = (oscillator frequency x 8) / (postscaler)
where:
postscaler = 1, 2, 4, 8, 16, or 32
The SIM is responsible for further dividing these frequencies by two, which will insure a 50% duty cycle
in the system clock output.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
33
The 56F8000 family devices’ on-chip clock synthesis module has the following registers:
•
•
•
•
•
Control Register (OCCS_CTRL)
Divide-by Register (OCCS_DIVBY)
Status Register (OCCS_STAT)
Shutdown Register (OCCS_SHUTDN)
Oscillator Control Register (OCCS_OCTRL)
For more information on these registers, please refer to the 56F802X and 56F803XPeripheral Reference
Manual.
3.4 Internal Clock Source
An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal is not used. It is optimized for accuracy and programmability while providing several power-saving
configurations which accommodate different operating conditions. The internal relaxation oscillator has
very little temperature and voltage variability. To optimize power, the architecture supports a standby state
and a power-down state.
During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the
PLLCR word is set to 0). Application code can then also switch to the external clock source and power
down the internal oscillator, if desired. If a changeover between internal and external clock sources is
required at power-on, the user must ensure that the clock source is not switched until the desired external
clock source is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within + 0.078% of 8MHz by trimming an internal capacitor. Bits 0-9 of
the OSCTL (oscillator control) register allow the user to set in an additional offset (trim) to this preset
value to increase or decrease capacitance. Each unit added or subtracted changes the output frequency by
about 0.078% of 8MHz, allowing incremental adjustment until the desired frequency accuracy is achieved.
The center frequency of the internal oscillator is calibrated at the factory to 8MHz and the TRIM value is
stored in the Flash information block and loaded to the FMOPT1 register at reset. When using the
relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM.
For further information, see the 56F802X and 56F803XPeripheral Reference Manual.
3.5 Crystal Oscillator
The internal crystal oscillator circuit is designed to interface with a parallel-resonant crystal resonator in a
frequency range of 4-8MHz, specified for the external crystal. Figure 3-1 shows a typical crystal oscillator
circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters
determine the component values required to provide maximum stability and reliable start-up. The load
capacitance values used in the oscillator circuit design should include all stray layout capacitances. The
crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins
to minimize output distortion and start-up stabilization time.
56F8036 Data Sheet, Rev. 3
34
FreescaleSemiconductor
Preliminary
Ceramic Resonator
Crystal Frequency = 4 - 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
EXTAL XTAL
Rz
Sample External Crystal Parameters:
Rz = 750 KΩ
Note: If the operating temperature range is limited to
below 85oC (105oC junction), then Rz = 10 Meg Ω
CL1
CL2
Figure 3-1 External Crystal Oscillator Circuit
3.6 Ceramic Resonator
The internal crystal oscillator circuit is also designed to interface with a ceramic resonator in the frequency
range of 4-8MHz. Figure 3-2 shows the typical 2 and 3 terminal ceramic resonators and their circuits.
Follow the resonator supplier’s recommendations when selecting a resonator, since their parameters
determine the component values required to provide maximum stability and reliable start up. The load
capacitance values used in the resonator circuit design should include all stray layout capacitances. The
resonator and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.
Resonator Frequency = 4 - 8MHz (optimized for 8MHz)
3 Terminal
2 Terminal
EXTAL XTAL
Rz
Sample External Ceramic Resonator Parameters:
Rz = 750 KΩ
EXTAL XTAL
Rz
CL1
CL2
C1
C2
Figure 3-2 External Ceramic Resonator Circuit
3.7 External Clock Input - Crystal Oscillator Option
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock
source is connected to XTAL and the EXTAL pin is grounded. The external clock input must be generated
using a relatively low impedance driver.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
35
56F8036
CLKMODE = 1
XTAL
EXTAL
External
Clock
GND or
GPIO
Figure 3-3 Connecting an External Clock Signal using XTAL
3.8 Alternate External Clock Input
The recommended method of connecting an external clock is illustrated in Figure 3-3. The external clock
source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary).
The user has the option of using GPIO6/RXD/CLKIN or GPIOB5/TA1/FAULT3/CLKIN as external
clock input.
56F8036
GPIO
ExternalClock
Figure 3-4 Connecting an External Clock Signal using GPIO
Part 4 Memory Maps
4.1 Introduction
The 56F8036 device is a 16-bit motor-control chip based on the 56800E core. It uses a Harvard-style
architecture with two independent memory spaces for Data and Program. On-chip RAM is shared by both
spaces and Flash memory is used only in Program space.
This section provides memory maps for:
•
•
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for the device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
56F8036 Data Sheet, Rev. 3
36
FreescaleSemiconductor
Preliminary
Interrupt Vector Table
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8036
Use Restrictions
Program Flash
(PFLASH)
32k x 16
or 64KB
Erase / Program via Flash interface unit and word writes to CDBW
Usable by both the Program and Data memory spaces
Unified RAM (RAM)
4k x 16
or 8KB
4.2 Interrupt Vector Table
Table 4-2 provides the 56F8036’s reset and interrupt priority structure, including on-chip peripherals. The
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.
As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.8
for the reset value of the VBA.
By default, VBA = 0, and the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
1
Table 4-2 Interrupt Vector Table Contents
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
Reserved for Reset Overlay2
core
P:$00
core
core
core
core
core
core
core
core
core
core
core
core
core
P:$02
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
P:$10
P:$12
P:$14
P:$16
P:$18
P:$1A
Reserved for COP Reset Overlay
Illegal Instruction
2
3
4
5
6
7
8
9
3
3
3
3
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
EOnCE Step Counter
EOnCE Breakpoint Unit
EOnCE Trace Buffer
EOnCE Transmit Register Empty
EOnCE Receive Register Full
SW Interrupt 2
1-3
1-3
1-3
1-3
1-3
2
10
11
12
13
14
1
SW Interrupt 1
0
SW Interrupt 0
Reserved
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
37
1
Table 4-2 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
LVI
15
1-3
P:$1E
P:$20
P:$22
P:$24
P:$26
P:$28
P:$2a
P:$2C
P:$2E
P:$30
P:$32
P:$34
P:$36
P:$38
P:$3A
Low-Voltage Detector (Power Sense)
Phase-Locked Loop
FM Access Error Interrupt
FM Command Complete
FM Command, Data, and Address Buffers Empty
MSCAN Error
PLL
16
1-3
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
0-2
FM
17
FM
18
FM
19
MSCAN
MSCAN
MSCAN
MSCAN
GPIOD
GPIOC
GPIOB
GPIOA
QSPI0
QSPI0
20
21
MSCAN Receive
22
MSCAN Transmit
23
MSCAN Wake-Up
GPIOD
24
25
GPIOC
26
GPIOB
27
GPIOA
28
QSPI0 Receiver Full
QSPI0 Transmitter Empty
Reserved
29
30 - 31
32
QSCI0
QSCI0
QSCI0
QSCI0
0-2
0-2
0-2
0-2
P:$40
P:$42
P:$44
P:$46
QSCI0 Transmitter Empty
QSCI0 Transmitter Idle
QSCI0 Receiver Error
QSCI0 Receiver Full
Reserved
33
34
35
36 - 39
40
I2C Error
I2C
I2C
I2C
I2C
I2C
0-2
0-2
0-2
0-2
0-2
P:$50
P:$52
P:$54
P:$56
P:$58
I2C General
I2C Receive
I2C Transmit
41
42
43
44
I2C Status
TMRA
TMRA
TMRA
TMRA
45
0-2
0-2
0-2
0-2
P:$5A
P:$5C
P:$5E
P:$60
Timer A, Channel 0
Timer A, Channel 1
Timer A, Channel 2
Timer A, Channel 3
Reserved
46
47
48
49 - 52
53
CMPA
CMPB
PIT0
0-2
0-2
0-2
0-2
0-2
0-2
0-2
P:$6A
P:$6C
P:$6E
P:$70
P:$72
P:$74
P:$76
Comparator A
54
Comparator B
55
Interval Timer 0
PIT1
56
Interval Timer 1
PIT2
57
Interval Timer 2
ADC
58
ADC A Conversion Complete
ADC B Conversion Complete
ADC
59
56F8036 Data Sheet, Rev. 3
38
FreescaleSemiconductor
Preliminary
Program Map
1
Table 4-2 Interrupt Vector Table Contents (Continued)
Vector
Number
Priority
Level
Vector Base
Address +
Peripheral
Interrupt Function
ADC
60
0-2
P:$78
P:$7A
P:$7C
P:$7E
ADC Zero Crossing or Limit Error
PWM
PWM
SWILP
61
62
63
0-2
0-2
-1
Reload PWM
PWM Fault
SW Interrupt Low Priority
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0000, the first two locations of the vector table will overlay the chip reset addresses since the reset
address would match the base of this vector table.
4.3 Program Map
The Program Memory map is shown in Table 4-3.
1
Table 4-3 Program Memory Map at Reset
Begin/End Address
Memory Allocation
P: $1F FFFF
RESERVED
P: $00 8800
On-Chip RAM2
8KB
P: $00 87FF
P: $00 8000
P: $00 7FFF
P: $00 0000
Internal Program Flash
64KB
Cop Reset Address = $00 0002
Boot Location = $00 0000
1. All addresses are 16-bit Word addresses.
2. This RAM is shared with Data space starting at address X: $00 0000; see Figure 4-1.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
39
4.4 Data Map
1
Table 4-4 Data Memory Map
Begin/End Address
Memory Allocation
X:$FF FFFF
EOnCE
X:$FF FF00
256 locations allocated
X:$FF FEFF
X:$01 0000
RESERVED
X:$00 FFFF
X:$00 F000
On-Chip Peripherals
4096 locations allocated
X:$00 EFFF
X:$00 8800
RESERVED
RESERVED
RESERVED
X:$00 87FF
X:$00 8000
X:$00 7FFF
X:$00 0800
X:$00 07FF
X:$00 0000
On-Chip Data RAM
8KB2
1. All addresses are 16-bit Word addresses.
2. This RAM is mapped into Program space starting at P: $00 8000; see Figure 4-1.
Program
Data
EOnCE
Reserved
Reserved
RAM
Peripherals
Reserved
RAM
Reserved
Dual Port RAM
Flash
Figure 4-1 Dual Port RAM
56F8036 Data Sheet, Rev. 3
40
FreescaleSemiconductor
Preliminary
EOnCE Memory Map
4.5 EOnCE Memory Map
Figure 4-5 lists all EOnCE registers necessary to access or control the EOnCE.
Table 4-5 EOnCE Memory Map
Address
X:$FF FFFF
Register Acronym
Register Name
OTX1 / ORX1
Transmit Register Upper Word
Receive Register Upper Word
X:$FF FFFE
OTX / ORX (32 bits)
Transmit Register
Receive Register
X:$FF FFFD
X:$FF FFFC
X:$FF FFFB - X:$FF FFA1
X:$FF FFA0
X:$FF FF9F
X:$FF FF9E
X:$FF FF9D
X:$FF FF9C
X:$FF FF9B
X:$FF FF9A
X:$FF FF99
OTXRXSR
OCLSR
Transmit and Receive Status and Control Register
Core Lock / Unlock Status Register
Reserved
OCR
Control Register
Instruction Step Counter
OSCNTR (24 bits)
OSR
Instruction Step Counter
Status Register
OBASE
Peripheral Base Address Register
Trace Buffer Control Register
Trace Buffer Pointer Register
Trace Buffer Register Stages
OTBCR
OTBPR
X:$FF FF98
OTB (21 - 24 bits/stage) Trace Buffer Register Stages
Breakpoint Unit Control Register
X:$FF FF97
X:$FF FF96
OBCR (24 bits)
OBAR1 (24 bits)
OBAR2 (32 bits)
OBMSK (32 bits)
OBCNTR
Breakpoint Unit Control Register
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 1
Breakpoint Unit Address Register 2
Breakpoint Unit Address Register 2
Breakpoint Unit Mask Register 2
Breakpoint Unit Mask Register 2
Reserved
X:$FF FF95
X:$FF FF94
X:$FF FF93
X:$FF FF92
X:$FF FF91
X:$FF FF90
X:$FF FF8F
X:$FF FF8E
X:$FF FF8D
X:$FF FF8C
X:$FF FF8B
X:$FF FF8A
X:$FF FF89 - X:$FF FF00
EOnCE Breakpoint Unit Counter
Reserved
Reserved
Reserved
OESCR
External Signal Control Register
Reserved
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
41
4.6 Peripheral Memory-Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read or written using word accesses only.
Table 4-6 summarizes base addresses for the set of peripherals on the 56F8036 device. Peripherals are
listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Table 4-6 Data Memory Peripheral Base Address Map Summary
Peripheral
Prefix
Base Address
Table Number
Timer A
ADC
TMRA
ADC
X:$00 F000
X:$00 F080
X:$00 F0C0
X:$00 F0E0
X:$00 F100
X:$00 F120
X:$00 F130
X:$00 F140
X:$00 F150
X:$00 F160
X:$00 F170
X:$00 F180
X:$00 F190
X:$00 F1A0
X:$00 F1B0
X:$00 F1C0
X:$00 F1D0
X:$00 F1E0
X:$00 F1F0
X:$00 F200
X:$00 F220
X:$00 F280
4-7
4-8
PWM
ITCN
SIM
PWM
ITCN
SIM
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
COP
COP
CLK, PLL, OSC
Power Supervisor
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
PIT 0
OCCS
PS
GPIOA
GPIOB
GPIOC
GPIOD
PIT0
PIT 1
PIT1
PIT 2
PIT2
DAC 0
DAC0
DAC1
CMPA
CMPB
SCI0
DAC 1
Comparator A
Comparator B
QSCI 0
QSPI 0
SPI0
I2C
I2C
FM
FM
X:$00 F400
X:$00 F800
4-29
4-30
MSCAN
CAN
56F8036 Data Sheet, Rev. 3
42
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
Table 4-7 Quad Timer A Registers Address Map
(TMRA_BASE = $00 F000)
Register Acronym
Address Offset
$0
Register Description
Compare Register 1
TMRA0_COMP1
TMRA0_COMP2
TMRA0_CAPT
TMRA0_LOAD
TMRA0_HOLD
TMRA0_CNTR
TMRA0_CTRL
TMRA0_SCTRL
TMRA0_CMPLD1
TMRA0_CMPLD2
TMRA0_CSCTRL
TMRA0_FILT
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA0_ENBL
TMRA1_COMP1
TMRA1_COMP2
TMRA1_CAPT
TMRA1_LOAD
TMRA1_HOLD
TMRA1_CNTR
TMRA1_CTRL
TMRA1_SCTRL
TMRA1_CMPLD1
TMRA1_CMPLD2
TMRA1_CSCTRL
TMRA1_FILT
$F
Timer Channel Enable Register
Compare Register 1
Compare Register 2
Capture Register
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA2_COMP1
TMRA2_COMP2
TMRA2_CAPT
TMRA2_LOAD
TMRA2_HOLD
TMRA2_CNTR
TMRA2_CTRL
TMRA2_SCTRL
$20
$21
$22
$23
$24
$25
$26
$27
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
43
Table 4-7 Quad Timer A Registers Address Map (Continued)
(TMRA_BASE = $00 F000)
Register Acronym
Address Offset
Register Description
Comparator Load Register 1
TMRA2_CMPLD1
TMRA2_CMPLD2
TMRA2_CSCTRL
TMRA2_FILT
$28
$29
$2A
$2B
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
TMRA3_COMP1
TMRA3_COMP2
TMRA3_CAPT
TMRA3_LOAD
TMRA3_HOLD
TMRA3_CNTR
TMRA3_CTRL
TMRA3_SCTRL
TMRA3_CMPLD1
TMRA3_CMPLD2
TMRA3_CSCTRL
TMRA3_FILT
$30
$31
$32
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Comparator Load Register 2
Comparator Status and Control Register
Input Filter Register
Reserved
Table 4-8 Analog-to-Digital Converter Registers Address Map
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
Register Description
Control Register 1
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_CLIST 1
ADC_CLIST 2
ADC_CLIST 3
ADC_CLIST 4
ADC_SDIS
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
Control Register 2
Zero Crossing Control Register
Channel List Register 1
Channel List Register 2
Channel List Register 3
Channel List Register 4
Sample Disable Register
Status Register
ADC_STAT
ADC_RDY
Conversion Ready Register
Limit Status Register
Zero Crossing Status Register
Result Register 0
ADC_LIMSTAT
ADC_ZXSTAT
ADC_RSLT0
ADC_RSLT1
Result Register 1
56F8036 Data Sheet, Rev. 3
44
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
Table 4-8 Analog-to-Digital Converter Registers Address Map (Continued)
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
$E
Register Description
ADC_RSLT2
ADC_RSLT3
ADC_RSLT4
ADC_RSLT5
ADC_RSLT6
ADC_RSLT7
ADC_RSLT8
ADC_RSLT9
ADC_RSLT10
ADC_RSLT11
ADC_RSLT12
ADC_RSLT13
ADC_RSLT14
ADC_RSLT15
ADC_LOLIM0
ADC_LOLIM1
ADC_LOLIM2
ADC_LOLIM3
ADC_LOLIM4
ADC_LOLIM5
ADC_LOLIM6
ADC_LOLIM7
ADC_HILIM0
ADC_HILIM1
ADC_HILIM2
ADC_HILIM3
ADC_HILIM4
ADC_HILIM5
ADC_HILIM6
ADC_HILIM7
ADC_OFFST0
ADC_OFFST1
ADC_OFFST2
ADC_OFFST3
ADC_OFFST4
ADC_OFFST5
Result Register 2
Result Register 3
Result Register 4
Result Register 5
Result Register 6
Result Register 7
Result Register 8
Result Register 9
$F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
Result Register 10
Result Register 11
Result Register 12
Result Register 13
Result Register 14
Result Register 15
Low Limit Register 0
Low Limit Register 1
Low Limit Register 2
Low Limit Register 3
Low Limit Register 4
Low Limit Register 5
Low Limit Register 6
Low Limit Register 7
High Limit Register 0
High Limit Register 1
High Limit Register 2
High Limit Register 3
High Limit Register 4
High Limit Register 5
High Limit Register 6
High Limit Register 7
Offset Register 0
Offset Register 1
Offset Register 2
Offset Register 3
Offset Register 4
Offset Register 5
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
45
Table 4-8 Analog-to-Digital Converter Registers Address Map (Continued)
(ADC_BASE = $00 F080)
Register Acronym
Address Offset
Register Description
ADC_OFFST6
ADC_OFFST7
ADC_PWR
$32
$33
$34
$35
Offset Register 6
Offset Register 7
Power Control Register
Calibration Register
Reserved
ADC_CAL
Table 4-9 Pulse Width Modulator Registers Address Map
(PWM_BASE = $00 F0C0)
Register Acronym
Address Offset
Register Description
PWM_CTRL
PWM_FCTRL
PWM_FLTACK
PWM_OUT
$0
$1
Control Register
Fault Control Register
Fault Status Acknowledge Register
Output Control Register
Counter Register
$2
$3
PWM_CNTR
PWM_CMOD
PWM_VAL0
PWM_VAL1
PWM_VAL2
PWM_VAL3
PWM_VAL4
PWM_VAL5
PWM_DTIM0
PWM_DTIM1
PWM_DMAP1
PWM_DMAP2
PWM_CNFG
PWM_CCTRL
PWM_PORT
PWM_ICCTRL
PWM_SCTRL
PWM_SYNC
PWM_FFILT0
PWM_FFILT1
PWM_FFILT2
PWM_FFILT3
$4
$5
Counter Modulo Register
Value Register 0
$6
$7
Value Register 1
$8
Value Register 2
$9
Value Register 3
$A
Value Register 4
$B
Value Register 5
$C
$D
$E
Dead Time Register 0
Dead Time Register 1
Disable Mapping Register 1
Disable Mapping Register 2
Configure Register
$F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
Channel Control Register
Port Register
Internal Correction Control Register
Source Control Register
Synchronization Window Register
Fault0 Filter Register
Fault1 Filter Register
Fault2 Filter Register
Fault3 Filter Register
56F8036 Data Sheet, Rev. 3
46
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
Table 4-10 Interrupt Control Registers Address Map
(ITCN_BASE = $00 F0E0)
Register Acronym
Address Offset
$0
Register Description
Interrupt Priority Register 0
ITCN_IPR0
ITCN_IPR1
ITCN_IPR2
ITCN_IPR3
ITCN_IPR4
ITCN_IPR5
ITCN_IPR6
ITCN_VBA
$1
$2
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Vector Base Address Register
Fast Interrupt Match 0 Register
Fast Interrupt Vector Address Low 0 Register
Fast Interrupt Vector Address High 0 Register
Fast Interrupt Match 1 Register
Fast Interrupt Vector Address Low 1 Register
Fast Interrupt Vector Address High 1 Register
IRQ Pending Register 0
$3
$4
$5
$6
$7
ITCN_FIM0
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_IRQP3
$8
$9
$A
$B
$C
$D
$E
$F
$10
$11
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
Reserved
ITCN_ICTRL
$16
Interrupt Control Register
Reserved
Table 4-11 SIM Registers Address Map
(SIM_BASE = $00 F100)
Register Acronym
Address Offset
Register Description
SIM_CTRL
SIM_RSTAT
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
SIM_PWR
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half JTAG ID
Least Significant Half JTAG ID
Power Control Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
47
Table 4-11 SIM Registers Address Map (Continued)
(SIM_BASE = $00 F100)
Register Acronym
Address Offset
Register Description
Reserved
SIM_CLKOUT
SIM_PCR
$A
$B
Clock Out Select Register
Peripheral Clock Rate Register
SIM_PCE0
SIM_PCE1
SIM_SD0
$C
Peripheral Clock Enable Register 0
$D
Peripheral Clock Enable Register 1
$E
Peripheral STOP Disable Register 0
Peripheral STOP Disable Register 1
I/O Short Address Location High Register
I/O Short Address Location Low Register
Protection Register
SIM_SD1
$F
SIM_IOSAHI
SIM_IOSALO
SIM_PROT
SIM_GPSA0
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
SIM_IPS0
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
GPIO Peripheral Select Register 0 for GPIOA
GPIO Peripheral Select Register 1 for GPIOA
GPIO Peripheral Select Register 0 for GPIOB
GPIO Peripheral Select Register 1 for GPIOB
GPIO Peripheral Select Register for GPIOC and GPIOD
Internal Peripheral Source Select Register 0 for PWM
Internal Peripheral Source Select Register 1 for DACs
Internal Peripheral Source Select Register 2 for TMRA
Reserved
SIM_IPS1
SIM_IPS2
Table 4-12 Computer Operating Properly Registers Address Map
(COP_BASE = $00 F120)
Register Acronym
Address Offset
Register Description
COP_CTRL
COP_TOUT
COP_CNTR
$0
$1
$2
Control Register
Time-Out Register
Counter Register
Table 4-13 Clock Generation Module Registers Address Map
(OCCS_BASE = $00 F130)
Register Acronym
Address Offset
Register Description
OCCS_CTRL
OCCS_DIVBY
OCCS_STAT
$0
$1
$2
Control Register
Divide-By Register
Status Register
Reserved
OCCS_OCTRL
OCCS_CLKCHK
OCCS_PROT
$5
$6
$7
Oscillator Control Register
Clock Check Register
Protection Register
56F8036 Data Sheet, Rev. 3
48
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
Table 4-14 Power Supervisor Registers Address Map
(PS_BASE = $00 F140)
Register Acronym
Address Offset
Register Description
PS_CTRL
PS_STAT
$0
$1
Control Register
Status Register
Reserved
Table 4-15 GPIOA Registers Address Map
(GPIOA_BASE = $00 F150)
Address Offset
Register Description
Register Acronym
GPIOA_PUPEN
GPIOA_DATA
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
GPIOA_DDIR
Data Direction Register
GPIOA_PEREN
GPIOA_IASSRT
GPIOA_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOA_IEPOL
GPIOA_IPEND
GPIOA_IEDGE
GPIOA_PPOUTM
GPIOA_RDATA
GPIOA_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-16 GPIOB Registers Address Map
(GPIOB_BASE = $00 F160)
Register Acronym
Address Offset
Register Description
GPIOB_PUPEN
GPIOB_DATA
GPIOB_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOB_PEREN
GPIOB_IASSRT
GPIOB_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOB_IEPOL
GPIOB_IPEND
GPIOB_IEDGE
GPIOB_PPOUTM
GPIOB_RDATA
GPIOB_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
49
Table 4-17 GPIOC Registers Address Map
(GPIOC_BASE = $00 F170)
Register Acronym
Address Offset
Register Description
GPIOC_PUPEN
GPIOC_DATA
GPIOC_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOC_PEREN
GPIOC_IASSRT
GPIOC_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOC_IEPOL
GPIOC_IPEND
GPIOC_IEDGE
GPIOC_PPOUTM
GPIOC_RDATA
GPIOC_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-18 GPIOD Registers Address Map
(GPIOD_BASE = $00 F180)
Register Acronym
Address Offset
Register Description
GPIOD_PUPEN
GPIOD_DATA
GPIOD_DDIR
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
Pull-up Enable Register
Data Register
Data Direction Register
GPIOD_PEREN
GPIOD_IASSRT
GPIOD_IEN
Peripheral Enable Register
Interrupt Assert Register
Interrupt Enable Register
GPIOD_IEPOL
GPIOD_IPEND
GPIOD_IEDGE
GPIOD_PPOUTM
GPIOD_RDATA
GPIOD_DRIVE
Interrupt Edge Polarity Register
Interrupt Pending Register
Interrupt Edge-Sensitive Register
Push-Pull Output Mode Control Register
Raw Data Input Register
Output Drive Strength Control Register
Table 4-19 Programmable Interval Timer 0 Registers Address Map
(PIT0_BASE = $00 F190)
Register Acronym
Address Offset
Register Description
PIT0_CTRL
PIT0_MOD
PIT0_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
56F8036 Data Sheet, Rev. 3
50
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
Table 4-20 Programmable Interval Timer 1 Registers Address Map
(PIT1_BASE = $00 F1A0)
Register Acronym
Address Offset
$0
Register Description
PIT1_CTRL
PIT1_MOD
PIT1_CNTR
Control Register
Modulo Register
Counter Register
$1
$2
Table 4-21 Programmable Interval Timer 2 Registers Address Map
(PIT2_BASE = $00 F1B0)
Register Acronym
Address Offset
Register Description
PIT2_CTRL
PIT2_MOD
PIT2_CNTR
$0
$1
$2
Control Register
Modulo Register
Counter Register
Table 4-22 Digital-to-Analog Converter 0 Registers Address Map
(DAC0_BASE = $00 F1C0)
Register Acronym
Address Offset
Register Description
DAC0_CTRL
DAC0_DATA
DAC0_STEP
DAC0_MINVAL
DAC0_MAXVAL
$0
$1
$2
$3
$4
Control Register
Data Register
Step Register
Minimum Value Register
Maximum Value Register
Table 4-23 Digital-to-Analog Converter 0 Registers Address Map
(DAC1_BASE = $00 F1D0)
Register Acronym
Address Offset
Register Description
DAC1_CTRL
DAC1_DATA
DAC1_STEP
DAC1_MINVAL
DAC1_MAXVAL
$0
$1
$2
$3
$4
Control Register
Data Register
Step Register
Minimum Value Register
Maximum Value Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
51
Table 4-24 Comparator A Registers Address Map
(CMPA_BASE = $00 F1E0)
Register Acronym
Address Offset
Register Description
CMPA_CTRL
CMPA_STAT
CMPA_FILT
$0
$1
$2
Control Register
Status Register
Filter Register
Table 4-25 Comparator B Registers Address Map
(CMPB_BASE = $00 F1F0)
Register Acronym
Address Offset
Register Description
CMPB_CTRL
CMPB_STAT
CMPB_FILT
$0
$1
$2
Control Register
Status Register
Filter Register
Table 4-26 Queued Serial Communication Interface 0 Registers Address Map
(QSCI0_BASE = $00 F200)
Register Acronym
Address Offset
Register Description
Baud Rate Register
QSCI0_RATE
QSCI0_CTRL1
QSCI0_CTRL2
QSCI0_STAT
QSCI0_DATA
$0
$1
$2
$3
$4
Control Register 1
Control Register 2
Status Register
Data Register
Table 4-27 Queued Serial Peripheral Interface 0 Registers Address Map
(QSPI0_BASE = $00 F220)
Register Acronym
Address Offset
Register Description
Status and Control Register
QSPI0_SCTRL
QSPI0_DSCTRL
QSPI0_DRCV
QSPI0_DXMIT
QSPI0_FIFO
$0
$1
$2
$3
$4
$5
Data Size and Control Register
Data Receive Register
Data Transmit Register
FIFO Control Register
Delay Register
QSPI0_DELAY
56F8036 Data Sheet, Rev. 3
52
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
2
Table 4-28 I C Registers Address Map
(I2C_BASE = $00 F280)
Register Acronym
Address Offset
Register Description
I2C_CTRL
I2C_TAR
I2C_SAR
I2C_DATA
$0
$2
Control Register
Target Address Register
Slave Address Register
$4
$8
RX/TX Data Buffer and Command Register
Standard Speed Clock SCL High Count Register
Standard Speed Clock SCL Low Count Register
Fast Speed Clock SCL High Count Register
Fast Speed Clock SCL Low Count Register
Interrupt Status Register
I2C_SSHCNT
I2C_SSLCNT
I2C_FSHCNT
I2C_FSLCNT
I2C_ISTAT
$A
$C
$E
$10
$16
$18
$1A
$1C
$1E
$20
$22
$24
$26
$28
$2A
$2C
$2E
$30
$32
$34
$36
$38
$3A
$3C
$40
I2C_IMASK
Interrupt Mask Register
I2C_RISTAT
Raw Interrupt Status Register
I2C_RXFT
Receive FIFO Threshold Register
Transmit FIFO Threshold Register
Clear Combined and Individual Interrupts Register
Clear RX_UNDER Interrupt Register
Clear RX_OVER Interrupt Register
Clear TX_OVER Interrupt Register
Clear RD_REQ Interrupt Register
Clear TX_ABRT Interrupt Register
Clear RX_DONE Interrupt Register
Clear Activity Interrupt Register
Clear STOP_DET Interrupt Register
Clear START_DET Interrupt Register
Clear GEN_CALL Interrupt Register
Enable Register
I2C_TXFT
I2C_CLRINT
I2C_CLRRXUND
I2C_CLRRXOVR
I2C_CLRTXOVR
I2C_CLRRDREQ
I2C_CLRTXABRT
I2C_CLRRXDONE
I2C_CLRACT
I2C_CLRSTPDET
I2C_CLRSTDET
I2C_CLRGC
I2C_ENBL
I2C_STAT
Status Register
I2C_TXFLR
Transmit FIFO Level Register
I2C_RXFLR
Receive FIFO Level Register
I2C_TXABRTSRC
Transmit Abort Status Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
53
Table 4-29 Flash Module Registers Address Map
(FM_BASE = $00 F400)
Register Acronym
Address Offset
Register Description
Clock Divider Register
FM_CLKDIV
FM_CNFG
$0
$1
Configuration Register
Reserved
$2
FM_SECHI
FM_SECLO
$3
Security High Half Register
Security Low Half Register
Reserved
$4
$5 - $9
$10
FM_PROT
Protection Register
Reserved
$11 - $12
$13
FM_USTAT
FM_CMD
User Status Register
Command Register
Reserved
$14
$15 - $17
$18
FM_DATA
Data Buffer Register
Reserved
$19 - $A
$1B
FM_IFROPT_1
FM_TSTSIG
Information Option Register 1
Reserved
$1C
$1D
Test Array Signature Register
Table 4-30 MSCAN Registers Address Map
(MSCAN_BASE = $00 F800)
Register Acronym
Address Offset
Register Description
MSCAN_CTRL0
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
Control Register 0
MSCAN_CTRL1
MSCAN_BTR0
MSCAN_BTR1
MSCAN_RFLG
MSCAN_RIER
MSCAN_TFLG
MSCAN_TIER
MSCAN_TARQ
MSCAN_TAAK
MSCAN_TBSEL
MSCAN_IDAC
Control Register 1
Bus Timing Register 0
Bus Timing Register 1
Receiver Flag Register
Receiver Interrupt Enable Register
Transmitter Flag Register
Transmitter Interrupt Enable Register
Transmitter Message Abort Request Register
Transmitter Message Abort Acknowledge Register
Transmitter Buffer Selection Register
Identifier Acceptance Control Register
Reserved
MSCAN_MISC
$0D
$0E
Miscellaneous Register
MSCAN_RXERR
Receive Error Register
56F8036 Data Sheet, Rev. 3
54
FreescaleSemiconductor
Preliminary
Peripheral Memory-Mapped Registers
Table 4-30 MSCAN Registers Address Map (Continued)
(MSCAN_BASE = $00 F800)
Register Acronym
MSCAN_TXERR
Address Offset
Register Description
Transmit Error Register
Identifier Acceptance Register 0
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$2B
$2C
$2D
$2E
$2F
$30
$31
$32
MSCAN_IDAR0
MSCAN_IDAR1
MSCAN_IDAR2
MSCAN_IDAR3
MSCAN_IDMR0
MSCAN_IDMR1
MSCAN_IDMR2
MSCAN_IDMR3
MSCAN_IDAR4
MSCAN_IDAR5
MSCAN_IDAR6
MSCAN_IDAR7
MSCAN_IDMR4
MSCAN_IDMR5
MSCAN_IDMR6
MSCAN_IDMR7
MSCAN_RXFG0
MSCAN_RXFG1
MSCAN_RXFG2
MSCAN_RXFG3
MSCAN_RXFG4
MSCAN_RXFG5
MSCAN_RXFG6
MSCAN_RXFG7
MSCAN_RXFG8
MSCAN_RXFG9
MSCAN_RXFG10
MSCAN_RXFG11
MSCAN_RXFG12
MSCAN_RXFG13
MSCAN_RXFG14
MSCAN_RXFG15
MSCAN_TXFG0
MSCAN_TXFG1
MSCAN_TXFG2
Identifier Acceptance Register 1
Identifier Acceptance Register 2
Identifier Acceptance Register 3
Identifier Mask Register 0
Identifier Mask Register 1
Identifier Mask Register 2
Identifier Mask Register 3
Identifier Acceptance Register 4
Identifier Acceptance Register 5
Identifier Acceptance Register 6
Identifier Acceptance Register 7
Identifier Mask Register 4
Identifier Mask Register 5
Identifier Mask Register 6
Identifier Mask Register 7
Foreground Receive Buffer 0
Foreground Receive Buffer 1
Foreground Receive Buffer 2
Foreground Receive Buffer 3
Foreground Receive Buffer 4
Foreground Receive Buffer 5
Foreground Receive Buffer 6
Foreground Receive Buffer 7
Foreground Receive Buffer 8
Foreground Receive Buffer 9
Foreground Receive Buffer 10
Foreground Receive Buffer 11
Foreground Receive Buffer 12
Foreground Receive Buffer 13
Foreground Receive Buffer 14
Foreground Receive Buffer 15
Foreground Transmit Buffer 0
Foreground Transmit Buffer 1
Foreground Transmit Buffer 2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
55
Table 4-30 MSCAN Registers Address Map (Continued)
(MSCAN_BASE = $00 F800)
Register Acronym
MSCAN_TXFG3
Address Offset
Register Description
Foreground Transmit Buffer 3
$33
$34
$35
$36
$37
$38
$39
$3A
$3B
$3C
$3D
$3E
$3F
MSCAN_TXFG4
MSCAN_TXFG5
MSCAN_TXFG6
MSCAN_TXFG7
MSCAN_TXFG8
MSCAN_TXFG9
MSCAN_TXFG10
MSCAN_TXFG11
MSCAN_TXFG12
MSCAN_TXFG13
MSCAN_TXFG14
MSCAN_TXFG15
Foreground Transmit Buffer 4
Foreground Transmit Buffer 5
Foreground Transmit Buffer 6
Foreground Transmit Buffer 7
Foreground Transmit Buffer 8
Foreground Transmit Buffer 9
Foreground Transmit Buffer 10
Foreground Transmit Buffer 11
Foreground Transmit Buffer 12
Foreground Transmit Buffer 13
Foreground Transmit Buffer 14
Foreground Transmit Buffer 15
Reserved
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to
the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to
service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Ability to drive initial address on the address bus after reset
For further information, see Table 4-2, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt
sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value
of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority
and number 63 is the lowest.
56F8036 Data Sheet, Rev. 3
56
FreescaleSemiconductor
Preliminary
Functional Description
5.3.1
Normal Interrupt Handling
Once the INTC has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the Vector Base
Address (VBA) and the vector number to determine the vector address, generating an offset into the vector
table for each interrupt.
5.3.2
Interrupt Nesting
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The 56800E core controls the masking of interrupt priority levels it will accept by setting the I0
and I1 bits in its status register.
Table 5-1 Interrupt Mask Bit Definition
Exceptions Permitted
SR[9] (I1) SR[8] (I0)
Exceptions Masked
0
0
1
1
0
1
0
1
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
None
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E
core.
Table 5-2 Interrupt Priority Encoding
Current Interrupt
Priority Level
Required Nested
Exception Priority
IPIC_VALUE[1:0]
00
01
10
11
No interrupt or SWILP
Priority 0
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 1
Priority 2 or 3
5.3.3
Fast Interrupt Handling
Fast interrupts are described in the DSP56800E Reference Manual. The interrupt controller recognizes
Fast Interrupts before the core does.
A Fast Interrupt is defined (to the ITCN) by:
1. Setting the priority of the interrupt as level 2, with the appropriate field in the IPR registers
2. Setting the FIMn register to the appropriate vector number
3. Setting the FIVALn and FIVAHn registers with the address of the code for the Fast Interrupt
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
57
When an interrupt occurs, its vector number is compared with the FIM0 and FIM1 register values. If a
match occurs, and it is a level 2 interrupt, the ITCN handles it as a Fast Interrupt. The ITCN takes the vector
address from the appropriate FIVALn and FIVAHn registers, instead of generating an address that is an
offset from the VBA.
The core then fetches the instruction from the indicated vector address and if it is not a JSR, the core starts
its Fast Interrupt handling.
5.4 Block Diagram
any0
Priority
Level
Level 0
64 -> 6
Priority
Encoder
6
2 -> 4
Decode
INT1
INT
VAB
IPIC
CONTROL
any3
IACK
SR[9:8]
Level 3
Priority
Level
64 -> 6
Priority
PIC_EN
6
Encoder
2 -> 4
Decode
INT64
Figure 5-1 Interrupt Controller Block Diagram
56F8036 Data Sheet, Rev. 3
58
FreescaleSemiconductor
Preliminary
Operating Modes
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
•
•
Functional Mode
The ITCN is in this mode by default.
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F060)
Register
Acronym
Base Address +
Register Name
Section Location
IPR0
$0
$1
Interrupt Priority Register 0
5.6.1
5.6.2
IPR1
Interrupt Priority Register 1
Interrupt Priority Register 2
Interrupt Priority Register 3
Interrupt Priority Register 4
Interrupt Priority Register 5
Interrupt Priority Register 6
Vector Base Address Register
Fast Interrupt Match 0 Register
Fast Interrupt 0 Vector Address Low Register
Fast Interrupt 0 Vector Address High 0 Register
Fast Interrupt Match 1 Register
Fast Interrupt 1 Vector Address Low Register
Fast Interrupt 1 Vector Address High Register
IRQ Pending Register 0
IPR2
$2
5.6.3
IPR3
$3
5.6.4
IPR4
$4
5.6.5
IPR5
$5
5.6.6
IPR6
$6
5.6.7
VBA
$7
5.6.8
FIM0
$8
5.6.9
FIVAL0
FIVAH0
FIM1
$9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
$A
$B
$C
$D
$E
$F
$10
$11
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
Reserved
ICTRL
$16
Interrupt Control Register
5.6.19
Reserved
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
59
Add.
Offset
Register
Name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
$10
IPR0
IPR1
PLL IPL
LVI IPL
RX_REG IPL TX_REG IPL
MSCAN_RX MSCAN_ERR
TRBUF IPL
FM_CBE IPL
GPIOA IPL
BKPT_U IPL
FM_CC IPL
GPIOB IPL
STPCNT IPL
FM_ERR IPL
GPIOC IPL
MSCAN_WK
UP IPL
MSCAN_TX
IPL
GPIOD IPL
IPL
IPL
W
R
0
0
0
0
QSCI0_XMIT
IPL
QSPI0_XMIT QSPI0_RCV
IPR2
IPL IPL
W
R
0
0
0
0
0
0
0
0
QSCI0_RCV QSCI0_RERR QSCI0_TIDL
IPR3
I2C_ERR IPL
IPL
IPL
IPL
W
R
I2C_STAT
IPL
IPR4
TMRA_3 IPL TMRA_2 IPL TMRA_1 IPL TMRA_0 IPL
I2C_TX IPL
I2C_RX IPL
I2C_GEN IPL
W
R
0
0
0
0
0
0
0
0
IPR5
PIT1 IPL
PIT0 IPL
COMPB IPL
COMPA IPL
W
0
0
0
0
0
0
0
0
0
0
ADCB_CC
IPL
IPR6
PWM_F IPL PWM_RL IPL ADC_ZC IPL
ADCA_CC IPL
PIT2 IPL
R
W
R
VBA
VECTOR_BASE_ADDRESS
0
0
0
0
0
0
FIM0
FAST INTERRUPT 0
W
R
FIVAL0
FIVAH0
FIM1
FAST INTERRUPT 0 VECTOR ADDRESS LOW
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
W
R
FAST INTERRUPT 1
W
R
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
FAST INTERRUPT 1 VECTOR ADDRESS LOW
W
R
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
W
R
PENDING[16:2]
PENDING[32:17]
PENDING[48:33]
1
W
R
W
R
W
R
PENDING[63:49]
$11
$16
IRQP3
W
Reserved
ICTRL
R
INT
IPIC
VAB
1
1
1
0
0
INT_
DIS
W
Reserved
= Reserved
Figure 5-2 ITCN Register Map Summary
56F8036 Data Sheet, Rev. 3
60
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.1
Interrupt Priority Register 0 (IPR0)
Base + $0
Read
15
14
0
13
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
PLL IPL
LVI IPL
RX_REG IPL TX_REG IPL
TRBUF IPL
BKPT_U IPL STPCNT IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-3 Interrupt Priority Register 0 (IPR0)
5.6.1.1
PLL Loss of Reference or Change in Lock Status Interrupt Priority Level
(PLL IPL)—Bits 15–14
This field is used to set the interrupt priority levels for the PLL Loss of Reference or Change in Lock Status
IRQ. This IRQ is limited to priorities 1 through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.2
Low Voltage Detector Interrupt Priority Level (LVI IPL)—Bits 13–12
This field is used to set the interrupt priority levels for the Low Voltage Detector IRQ. This IRQ is limited
to priorities 1 through 3 and is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.3
Reserved—Bits 11–10
This bit field is reserved. Each bit must be set to 0.
5.6.1.4
EOnCE Receive Register Full Interrupt Priority Level
(RX_REG IPL)— Bits 9–8
This field is used to set the interrupt priority level for the EOnCE Receive Register Full IRQ. This IRQ is
limited to priorities 1 through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
61
5.6.1.5
EOnCE Transmit Register Empty Interrupt Priority Level
(TX_REG IPL)— Bits 7–6
This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ
is limited to priorities 1 through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.6
EOnCE Trace Buffer Interrupt Priority Level
(TRBUF IPL)— Bits 5–4
This field is used to set the interrupt priority level for the EOnCE Trace Buffer IRQ. This IRQ is limited
to priorities 1 through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.7
EOnCE Breakpoint Unit Interrupt Priority Level
(BKPT_U IPL)— Bits 3–2
This field is used to set the interrupt priority level for the EOnCE Breakpoint Unit IRQ. This IRQ is limited
to priorities 1 through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
5.6.1.8
EOnCE Step Counter Interrupt Priority Level
(STPCNT IPL)— Bits 1–0
This field is used to set the interrupt priority level for the EOnCE Step Counter IRQ. This IRQ is limited
to priorities 1 through 3. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 1
10 = IRQ is priority level 2
11 = IRQ is priority level 3
56F8036 Data Sheet, Rev. 3
62
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.2
Interrupt Priority Register 1 (IPR1)
Base + $1
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSCAN_WK
UP IPL
MSCAN_TX
IPL
MSCAN_RX
IPL
MSCAN_ERR
IPL
GPIOD IPL
FM_CBE IPL
FM_CC IPL
FM_ERR IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-4 Interrupt Priority Register 1 (IPR1)
GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14
5.6.2.1
This field is used to set the interrupt priority level for the GPIOD IRQ. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.2.2
MSCAN Wake Up Interrupt Priority Level
(MSCAN_WKUP IPL)—Bits 13–12
This field is used to set the interrupt priority level for the MSCAN Wake Up IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.2.3
MSCAN Transmit Interrupt Priority Level (MSCAN_TX IPL)—Bits 11–10
This field is used to set the interrupt priority level for the MSCAN Transmit IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
63
5.6.2.4
MSCAN Receive Interrupt Priority Level (MSCAN_RX IPL)—Bits 9–8
This field is used to set the interrupt priority level for MSCAN Receive IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.2.5
MSCAN Error Interrupt Priority Level (MSCAN_ERR IPL)—Bits 7–6
This field is used to set the interrupt priority level for the MSCAN Error IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.2.6
FM Command, Data, Address Buffers Empty Interrupt Priority Level
(FM_CBE IPL)—Bits 5–4
This field is used to set the interrupt priority level for the FM Command, Data Address Buffers Empty
IRQ. This IRQ is limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.2.7
FM Command Complete Interrupt Priority Level (FM_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for the FM Command Complete IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.2.8
FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 1–0
This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities
0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8036 Data Sheet, Rev. 3
64
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.3
Interrupt Priority Register 2 (IPR2)
Base + $2
Read
15
14
13
0
12
0
11
0
10
0
9
8
7
6
5
4
3
2
1
0
QSCI0_XMIT
IPL
QSPI0_XMIT
IPL
QSPI0_RCV
IPL
GPIOA IPL
GPIOB IPL
GPIOC IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-5 Interrupt Priority Register 2 (IPR2)
5.6.3.1
QSCI 0 Transmitter Empty Interrupt Priority Level (QSCI0_XMIT IPL)—
Bits 15–14
This field is used to set the interrupt priority level for the QSCI0 Transmitter Empty IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.2
Reserved—Bits 13–10
This bit field is reserved. Each bit must be set to 0.
5.6.3.3
QSPI 0 Transmitter Empty Interrupt Priority Level (QSPI0_XMIT IPL)—
Bits 9–8
This field is used to set the interrupt priority level for the QSPI0 Transmitter Empty IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.4
QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6
This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
65
5.6.3.5
GPIOA Interrupt Priority Level (GPIOA IPL)—Bits 5–4
This field is used to set the interrupt priority level for the GPIOA IRQ. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.6
GPIOB Interrupt Priority Level (GPIOB IPL)—Bits 3–2
This field is used to set the interrupt priority level for the GPIOB IRQ. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.3.7
GPIOC Interrupt Priority Level (GPIOC IPL)—Bits 1–0
This field is used to set the interrupt priority level for the GPIOC IRQ. This IRQ is limited to priorities 0
through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4
Interrupt Priority Register 3 (IPR3)
Base + $3
Read
15
14
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
4
3
2
1
0
QSCI0_RCV QSCI0_RERR QSCI0_TIDL
IPL IPL IPL
I2C_ERR IPL
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-6 Interrupt Priority Register 3 (IPR3)
2
5.6.4.1
I C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14
2
This field is used to set the interrupt priority level for the I C Error IRQ. This IRQ is limited to priorities
0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8036 Data Sheet, Rev. 3
66
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.4.2
Reserved—Bits 13–6
This bit field is reserved. Each bit must be set to 0.
5.6.4.3
QSCI 0 Receiver Full Interrupt Priority Level (QSCI0_RCV IPL)—Bits 5–4
This field is used to set the interrupt priority level for the QSCI0 Receiver Full IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.4
QSCI 0 Receiver Error Interrupt Priority Level (QSCI0_RERR IPL)—
Bits 3–2
This field is used to set the interrupt priority level for the QSCI0 Receiver Error IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.4.5
QSCI 0 Transmitter Idle Interrupt Priority Level (QSCI0_TIDL IPL)—
Bits 1–0
This field is used to set the interrupt priority level for the QSCI0 Transmitter Idle IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5
Interrupt Priority Register 4 (IPR4)
Base + $4
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMRA_3 IPL
TMRA_2 IPL
TMRA_1 IPL
TMRA_0 IPL I2C_STAT IPL I2C_TX IPL
I2C_RX IPL I2C_GEN IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-7 Interrupt Priority Register 4 (IPR4)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
67
5.6.5.1
Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for the Timer A, Channel 3 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.2
Timer A, Channel 2 Interrupt Priority Level (TMRA_2 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for the Timer A, Channel 2 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.3
Timer A, Channel 1 Interrupt Priority Level (TMRA_1 IPL)—
Bits 11–10
This field is used to set the interrupt priority level for the Timer A, Channel 1 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.5.4
Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)—
Bits 9–8
This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8036 Data Sheet, Rev. 3
68
FreescaleSemiconductor
Preliminary
Register Descriptions
2
5.6.5.5
I C Status Interrupt Priority Level (I2C_STAT IPL)—Bits 7–6
2
This field is used to set the interrupt priority level for the I C Status IRQ. This IRQ is limited to priorities
0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
2
5.6.5.6
I C Transmit Interrupt Priority Level (I2C_TX IPL)—Bits 5–4
2
This field is used to set the interrupt priority level for the I C Transmit IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
2
5.6.5.7
I C Receive Interrupt Priority Level (I2C_RX IPL)— Bits 3–2
2
This field is used to set the interrupt priority level for the I C Receiver IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
2
5.6.5.8
I C General Call Interrupt Priority Level (I2C_GEN IPL)—Bits 1–0
2
This field is used to set the interrupt priority level for the I C General Call IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6
Interrupt Priority Register 5 (IPR5)
Base + $5
Read
15
14
13
12
11
10
9
8
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PIT1 IPL
PIT0 IPL
COMPB IPL
COMPA IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-8 Interrupt Priority Register 5 (IPR6)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
69
5.6.6.1
Programmable Interval Timer 1 Interrupt Priority Level (PIT1 IPL)—
Bits 15–14
This field is used to set the interrupt priority level for the Programmable Interval Timer 1 IRQ. This IRQ
is limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.2
Programmable Interval Timer 0 Interrupt Priority Level (PIT0 IPL)—
Bits 13–12
This field is used to set the interrupt priority level for the Programmable Interval Timer 0 IRQ. This IRQ
is limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.3
Comparator B Interrupt Priority Level (COMPB IPL)—
Bits 11–10
This field is used to set the interrupt priority level for the Comparator B IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.4
Comparator A Interrupt Priority Level (COMPA IPL)—
Bits 9–8
This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities
0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.6.5
Reserved—Bits 7–0
This bit field is reserved. Each bit must be set to 0.
56F8036 Data Sheet, Rev. 3
70
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.7
Interrupt Priority Register 6 (IPR6)
Base + $6
Read
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
ADCB_CC
IPL
ADCA_CC
IPL
PWM_F IPL
PWM_RL IPL
ADC_ZC IPL
PIT2 IPL
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-9 Interrupt Priority Register 6 (IPR6)
5.6.7.1
Reserved—Bits 15–12
This bit field is reserved. Each bit must be set to 0.
5.6.7.2
PWM Fault Interrupt Priority Level (PWM_F IPL)—Bits 11–10
This field is used to set the interrupt priority level for the PWM Fault Interrupt IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.3
Reload PWM Interrupt Priority Level (PWM_RL IPL)—Bits 9–8
This field is used to set the interrupt priority level for the Reload PWM Interrupt IRQ. This IRQ is limited
to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.4
ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)—Bits 7–6
This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to
priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
71
5.6.7.5
ADC B Conversion Complete Interrupt Priority Level
(ADCB_CC IPL)—Bits 5–4
This field is used to set the interrupt priority level for the ADC B Conversion Complete IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.6
ADC A Conversion Complete Interrupt Priority Level
(ADCA_CC IPL)—Bits 3–2
This field is used to set the interrupt priority level for the ADC A Conversion Complete IRQ. This IRQ is
limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.7
Programmable Interval Timer 2 Interrupt Priority Level
(PIT2 IPL)—Bits 1–0
This field is used to set the interrupt priority level for the Programmable Interval Timer 2 IRQ. This IRQ
is limited to priorities 0 through 2. It is disabled by default.
•
•
•
•
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8
Vector Base Address Register (VBA)
Base + $7
Read
15
0
14
0
13
12
11
10
9
8
7
6
5
4
3
0
2
0
1
0
0
0
VECTOR_BASE_ADDRESS
Write
1
0
0
0
0
0
0
0
0
0
0
0
0
RESET
1. The 56F8036 resets to a value of 0 x 0000. This corresponds to reset addresses of 0 x 000000.
Figure 5-10 Vector Base Address Register (VBA)
5.6.8.1
Reserved—Bits 15–14
This bit field is reserved. Each bit must be set to 0.
56F8036 Data Sheet, Rev. 3
72
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.8.2
Vector Address Bus (VAB) Bits 13–0
The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits
are determined based on the highest priority interrupt and are then appended onto VBA before presenting
the full VAB to the Core.
5.6.9
Fast Interrupt Match 0 Register (FIM0)
Base + $8
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
0
0
FAST INTERRUPT 0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-11 Fast Interrupt Match 0 Register (FIM0)
5.6.9.1
Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
5.6.9.2
Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)—Bits 5–0
These values determine which IRQ will be Fast Interrupt 0. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest-priority
level 2 interrupt regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.
5.6.10 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
Base + $9
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FAST INTERRUPT 0 VECTOR ADDRESS LOW
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0)
5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAH0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
73
5.6.11 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Base + $A
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
0
FAST INTERRUPT 0 VECTOR
ADDRESS HIGH
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-13 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.11.1 Reserved—Bits 15–5
This bit field is reserved. Each bit must be set to 0.
5.6.11.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.12 Fast Interrupt 1 Match Register (FIM1)
Base + $B
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
0
0
FAST INTERRUPT 1
Write
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-14 Fast Interrupt 1 Match Register (FIM1)
5.6.12.1 Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
5.6.12.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 5–0
These values determine which IRQ will be Fast Interrupt 1. Fast Interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first. IRQs used as Fast Interrupts must be set to priority level 2. Unexpected results will occur if a Fast
Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority
level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt.
Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to
the vector table.
5.6.13 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
Base + $C
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
1
0
0
0
FAST INTERRUPT 1 VECTOR ADDRESS LOW
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-15 Fast Interrupt 1 Vector Address Low Register (FIVAL1)
56F8036 Data Sheet, Rev. 3
74
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.13.1 Fast Interrupt 1 Vector Address Low (FIVAL1)—Bits 15–0
The lower 16 bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAH1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.14 Fast Interrupt 1 Vector Address High (FIVAH1)
Base + $D
Read
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
2
1
0
0
FAST INTERRUPT 1 VECTOR
ADDRESS HIGH
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 5-16 Fast Interrupt 1 Vector Address High Register (FIVAH1)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved. Each bit must be set to 0.
5.6.14.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 1. This register is combined with FIVAL1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.15 IRQ Pending Register 0 (IRQP0)
Base + $E
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING[16:2]
Write
1
1
1
1
1
1
1
1
1
1
RESET
Figure 5-17 IRQ Pending Register 0 (IRQP0)
5.6.15.1 IRQ Pending (PENDING)—Bits 16–2
These register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending
IRQ numbers correspond to ascending bit locations.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.15.2 Reserved—Bit 0
This bit field is reserved. It must be set to 0.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
75
5.6.16 IRQ Pending Register 1 (IRQP1)
Base + $F
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING[32:17]
Write
RESET
1
1
1
1
1
1
1
1
1
Figure 5-18 IRQ Pending Register 1 (IRQP1)
5.6.16.1 IRQ Pending (PENDING)—Bits 32–17
These register bit values represent the pending IRQs for interrupt vector numbers 17 through 32.
Ascending IRQ numbers correspond to ascending bit locations.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.17 IRQ Pending Register 2 (IRQP2)
Base + $10
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING[48:33]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-19 IRQ Pending Register 2 (IRQP2)
5.6.17.1 IRQ Pending (PENDING)—Bits 48–33
These register bit values represent the pending IRQs for interrupt vector numbers 33 through 48.
Ascending IRQ numbers correspond to ascending bit locations.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.18 IRQ Pending Register 3 (IRQP3)
Base + $11
Read
15
14
13
12
11
10
9
8
7
6
1
5
1
4
1
3
1
2
1
1
1
0
1
PENDING[63:49]
Write
1
1
1
1
1
1
1
1
1
RESET
Figure 5-20 IRQ Pending Register 3 (IRQP3)
5.6.18.1 IRQ Pending (PENDING)—Bits 63–49
These register bit values represent the pending IRQs for interrupt vector numbers 49 through 63.
Ascending IRQ numbers correspond to ascending bit locations.
•
•
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
56F8036 Data Sheet, Rev. 3
76
FreescaleSemiconductor
Preliminary
Register Descriptions
5.6.19 Interrupt Control Register (ICTRL)
$Base + $16
Read
15
14
13
12
11
10
9
8
7
0
6
0
5
4
1
3
1
2
1
1
0
0
0
INT
IPIC
VAB
INT_
DIS
Write
RESET
0
0
0
0
0
0
0
0
0
1
1
1
0
0
Figure 5-21 Interrupt Control Register (ICTRL)
5.6.19.1 Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
•
•
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.6.19.2 Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
•
•
•
•
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
Table 5-4 Interrupt Priority Encoding
Current Interrupt
Priority Level
Required Nested
Exception Priority
IPIC_VALUE[1:0]
00
01
10
11
No interrupt or SWILP
Priority 0
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Priority 1
Priority 2 or 3
5.6.19.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken.
In the case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated
when the 56800E core jumps to a new interrupt service routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
77
5.6.19.4 Interrupt Disable (INT_DIS)—Bit 5
This bit allows all interrupts to be disabled.
•
•
0 = Normal operation (default)
1 = All interrupts disabled
5.6.19.5 Reserved—Bits 4-2
This bit field is reserved. Each bit must be set to 1.
5.6.19.6 Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
5.7 Resets
5.7.1
General
Table 5-5 Reset Summary
Source
Characteristics
Reset
Priority
Core Reset
RST
Core reset from the SIM
5.7.2
Description of Reset Operation
Reset Handshake Timing
5.7.2.1
The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is
asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET
is released. The general timing is shown in Figure 5-22.
RES
CLK
RESET_VECTOR_ADR
VAB
PAB
READ_ADR
Figure 5-22 Reset Interface
56F8036 Data Sheet, Rev. 3
78
FreescaleSemiconductor
Preliminary
Introduction
5.7.3
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
•
•
•
•
•
•
•
•
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.
Part 6 System Integration Module (SIM)
6.1 Introduction
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The System Integration
Module’s functions are discussed in more detail in the following sections.
6.2 Features
The SIM has the following features:
•
•
•
•
•
•
•
•
•
Chip reset sequencing
Core and peripheral clock control and distribution
Stop/Wait mode control
System status control
Registers containing the JTAG ID of the chip
Controls for programmable peripheral and GPIO connections
Peripheral clocks for TMR and PWM with a high-speed (3X) option
Power-saving clock gating for peripherals
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down the 56800E core, system clock, and peripheral clock
— Wait mode shuts down the 56800E core and unnecessary system clock operation
— Run mode supports full device operation
•
•
Controls the enable/disable functions of the 56800E core WAIT and STOP instructions with write protection
capability
Controls the enable/disable functions of Large Regulator Standby mode with write protection capability
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
79
•
•
•
•
•
•
•
•
Permits selected peripherals to run in Stop mode to generate Stop recovery interrupts
Controls for programmable peripheral and GPIO connections
Software chip reset
I/O short address base location control
Peripheral protection control to provide runaway code protection for safety-critical applications
Controls output of internal clock sources to I/O pins
Four general-purpose software control registers are reset only at power-on
Peripherals Stop mode clocking control
56F8036 Data Sheet, Rev. 3
80
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3 Register Descriptions
A write to an address without an associated register is an NOP. A read from an address without an
associated register returns unknown data.
Table 6-1 SIM Registers (SIM_BASE = $00 F100)
Register
Acronym
Section
Location
Base Address +
Register Name
CTRL
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
6.3.1
6.3.2
6.3.3
6.3.3
6.3.3
6.3.3
6.3.4
6.3.5
6.3.6
RSTAT
SWC0
SWC1
SWC2
SWC3
MSHID
LSHID
PWR
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half of JTAG ID
Least Significant Half of JTAG ID
Power Control Register
Reserved
CLKOUT
PCR
$A
$B
CLKO Select Register
6.3.7
6.3.8
Peripheral Clock Rate Register
PCE0
$C
Peripheral Clock Enable Register 0
Peripheral Clock Enable Register 0
Stop Disable Register 0
6.3.9
PCE1
$D
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
SD0
$E
SD1
$F
Stop Disable Register 1
IOSAHI
IOSALO
PROT
GPSA0
GPSA1
GPSB0
GPSB1
GPSCD
IPS0
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
I/O Short Address Location High Register
I/O Short Address Location Low Register
Protection Register
GPIO Peripheral Select Register 0 for GPIOA
GPIO Peripheral Select Register 1 for GPIOA
GPIO Peripheral Select Register 0 for GPIOB
GPIO Peripheral Select Register 1 for GPIOB
GPIO Peripheral Select Register for GPIOC and GPIOD
Internal Peripheral Source Select Register 0 for PWM
Internal Peripheral Source Select Register 1 for DACs
Internal Peripheral Source Select Register 2 for Quad Timer A
Reserved
IPSS1
IPSS2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
81
Add.
Address
Offset Acronym
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
SIM_
CTRL
ONCE SW
EBL0 RST
STOP_
DISABLE
WAIT_
DISABLE
$0
W
COP_ COP_
R
0
0
0
0
0
0
0
0
0
SWR
EXTR POR
0
0
SIM_
$1
TOR
LOR
RSTAT
W
R
$2
$3
$4
$5
$6
$7
$8
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
Software Control Data 0
Software Control Data 1
Software Control Data 2
Software Control Data 3
W
R
W
R
W
R
W
R
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
W
R
W
R
SIM_PWR
Reserved
LRSTDBY
W
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIM_
CLKOUT
$A
$B
$C
$D
$E
$F
PWM3 PWM2 PWM1 PWM0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TMRA_ PWM_C I2C_
CR CR
SIM_PCR
SIM_PCE0
SIM_PCE1
SIM_SD0
SIM_SD1
R
W
R
CMPB CMPA DAC1 DAC0
0
ADC
0
I2C
0
QSCI0
0
QSPI0
TA2
PWM
TA0
W
R
PIT2
PIT1
PIT0
TA3
0
TA1
0
W
R
CMPB_ CMPA_ DAC1_ DAC0_
SD
ADC_
SD
I2C_
SD
QSCI0
_SD
QSPI0
_SD
PWM_
SD
SD
SD
SD
W
R
0
0
0
0
PIT2_ PIT1_S PIT0_
TA3_ TA2_ TA1_ TA0_
SD
SD
0
D
0
SD
0
SD
SD
SD
W
R
0
0
0
0
0
0
$10 SIM_IOSAHI
$11 SIM_IOSALO
ISAL[23:22]
W
R
ISAL[21:6]
0
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
$12
SIM_PROT
PCEP
GIPSP
W
R
0
0
0
0
GPS_
A6
$13 SIM_GPSA0
$14 SIM_GPSA1
$15 SIM_GPSB0
$16 SIM_GPSB1
$17 SIM_GPSCD
GPS_A5
GPS_A4
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_A9
GPS_A8
W
R
0
0
0
0
0
0
GPS_
B1
GPS_
B0
GPS_B6
GPS_B5
GPS_B3
GPS_B2
W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_
B9
GPS_
B8
GPS_
B7
W
R
0
0
0
GPS_
D5
W
R
0
IPS0_
FAULT2
IPS0_
FAULT1
$18
$19
$1A
SIM_IPS0
SIM_IPS1
IPS0_PSRC2
0
IPS0_PSRC1
IPS0_PSRC0
W
R
0
0
0
0
0
0
0
0
IPS1_DSYNC1
IPS1_DSYNC0
0 0
W
R
0
0
0
0
IPS2_
TA3
IPS2_
TA2
IPS2_
TA1
SIM_IPS2
Reserved
W
0
= Read as 0
1
= Read as 1
= Reserved
Figure 6-1 SIM Register Map Summary
56F8036 Data Sheet, Rev. 3
82
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.1
SIM Control Register (SIM_CTRL)
Base + $0
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
ONCE SW
EBL
STOP_
DISABLE
WAIT_
DISABLE
RST
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-2 SIM Control Register (SIM_CTRL)
6.3.1.1
Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
6.3.1.2
OnCE Enable (ONCEEBL)—Bit 5
•
•
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Note:
Using default state “0” is recommended.
6.3.1.3
Software Reset (SWRST)—Bit 4
•
•
Writing 1 to this field will cause the device to reset
Read is 0
6.3.1.4
Stop Disable (STOP_DISABLE)—Bits 3–2
•
•
•
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
•
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
6.3.1.5
Wait Disable (WAIT_DISABLE)—Bits 1–0
•
•
•
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
•
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
6.3.2
SIM Reset Status Register (SIM_RSTAT)
This read-only register is updated upon any system reset and indicates the cause of the most recent reset.
It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External
Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On
Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
83
most recent reset source will be indicated if multiple resets occur. If multiple reset sources assert
simultaneously, the highest-precedence source will be indicated. The precedence from highest to lowest is
Power-On Reset, External Reset, COP Loss of Reference Reset, COP Time-Out Reset, and Software
Reset. Power-On Reset is always set during a Power-On Reset; however, Power-On Reset will be cleared
and External Reset will be set if the external reset pin is asserted or remains asserted after the Power-On
Reset has deasserted.
Base + $1
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COP_ COP_
TOR
0
0
0
0
0
0
0
0
0
SWR
EXTR POR
0
0
LOR
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
RESET
Figure 6-3 SIM Reset Status Register (SIM_RSTAT)
6.3.2.1
Reserved—Bits 15–7
This bit field is reserved. Each bit must be set to 0.
6.3.2.2
Software Reset (SWR)—Bit 6
When set, this bit indicates that the previous system reset occurred as a result of a software reset (written
1 to SWRST bit in the SIM_CTRL register).
6.3.2.3
COP Time-Out Reset (COP_TOR)—Bit 5
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
(COP) module signaling a COP time-out reset. If COP_TOR is set as code starts executing, the COP reset
vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.4
COP Loss of Reference Reset (COP_LOR)—Bit 4
When set, this bit indicates that the previous system reset was caused by the Computer Operating Properly
(COP) module signaling a loss of COP reference clock reset. If COP_LOR is set as code starts executing,
the COP reset vector in the vector table will be used. Otherwise, the normal reset vector is used.
6.3.2.5
External Reset (EXTR)—Bit 3
When set, this bit indicates that the previous system reset was caused by an external reset.
6.3.2.6
Power-On Reset (POR)—Bit 2
This bit is set during a Power-On Reset.
6.3.2.7
Reserved—Bits 1–0
This bit field is reserved. Each bit must be set to 0.
56F8036 Data Sheet, Rev. 3
84
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.3
SIM Software Control Registers (SIM_SWC0, SIM_SWC1,
SIM_SWC2, and SIM_SWC3)
These registers are general-purpose registers. They are reset only at power-on, so they can monitor
software execution flow.
Base + $2
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Software Control Data 0 - 3
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-4 SIM Software Control Register 0 (SIM_SWC0 - 3)
Software Control Register 0 - 3 (FIELD)—Bits 15–0
6.3.3.1
This register is reset only by the Power-On Reset (POR). It is intended for use by a software developer to
contain data that will be unaffected by the other reset sources (external reset, software reset, and COP
reset).
6.3.4
Most Significant Half of JTAG ID (SIM_MSHID)
This read-only register displays the most significant half of the JTAG ID for the chip. This register reads
$01F2.
Base + $6
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
Write
RESET
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)
6.3.5
Least Significant Half of JTAG ID (SIM_LSHID)
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$801D.
Base + $7
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Write
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
RESET
Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
85
6.3.6
SIM Power Control Register (SIM_PWR)
This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives
the core digital logic power supply from the IO power supply. At a system bus frequency of 200kHz, the
large regulator may be put in a reduced-power standby mode without interfering with device operation to
reduce device power consumption. Refer to the overview of power-down modes and the overview of clock
generation for more information on the use of large regulator standby.
Base + $8
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LRSTDBY
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-7 SIM Power Control Register (SIM_PWR)
6.3.6.1
Reserved—Bits 15–2
This bit field is reserved. Each bit must be set to 0.
6.3.6.2
Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0
•
•
•
•
00 = Large regulator is in Normal mode
01 = Large regulator is in Standby (reduced-power) mode
10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset
11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset
6.3.7
Clock Output Select Register (SIM_CLKOUT)
The Clock Output Select register can be used to multiplex out selected clock sources generated inside the
clock generation and SIM modules onto the muxed clock output pins. All functionality is for test purposes
only. Glitches may be produced when the clock is enabled or switched. The delay from the clock source
to the output is unspecified. The observability of the clock output signals at output pads is subject to the
frequency limitations of the associated IO cell.
GPIOA[3:0] can function as GPIO, PWM, or as clock output pins. If GPIOA[3:0] are programmed to
operate as peripheral outputs, then the choice is between PWM and clock outputs. The default state is for
the peripheral function of GPIOA[3:0] to be programmed as PWM (selected by bits [9:6] of the Clock
Output Select register).
See Figure 6-8 for details.
Base + $A
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
0
0
0
PWM3 PWM2 PWM1 PWM0
Write
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
RESET
Figure 6-8 CLKO Select Register (SIM_CLKOUT)
56F8036 Data Sheet, Rev. 3
86
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.7.1
Reserved—Bits 15–10
This bit field is reserved. Each bit must be set to 0.
6.3.7.2
PWM3—Bit 9
•
•
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
PWM2—Bit 8
•
•
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
PWM1—Bit 7
•
•
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock
6.3.7.5
PWM0—Bit 6
•
•
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock
6.3.7.6
Reserved—Bit 5
This bit field is reserved for factory test. It must be set to 1.
6.3.7.7
Reserved—Bits 4–0
This bit field is reserved for factory test. Each bit must be set to 0.
6.3.8
Peripheral Clock Rate Register (SIM_PCR)
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected
peripherals clocks have the option to be clocked at 3X system clock rate, which has a maximum of 96MHz,
if the PLL output clock is selected as the system clock. If PLL is disabled, the 3X system clock will not be
available. This register is used to enable high-speed clocking for those peripherals that support it.
Note:
Operation is unpredictable if peripheral clocks are reconfigured at runtime, so peripherals should be
disabled before a peripheral clock is reconfigured.
Base + $B
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
TMRA_ PWM_ I2C_
CR
CR
CR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-9 Peripheral Clock Rate Register (SIM_PCR)
6.3.8.1
Reserved—Bit 15
This bit field is reserved. It must be set to 0.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
87
6.3.8.2
Quad Timer A Clock Rate (TMRA_CR)—Bit 14
This bit selects the clock speed for the Quad Timer A module.
•
•
0 = Quad Timer A clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = Quad Timer A clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.3
Pulse Width Modulator Clock Rate (PWM_CR)—Bit 13
This bit selects the clock speed for the PWM module.
•
•
0 = PWM module clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = PWM module clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.4
Inter-Integrated Circuit Run Clock Rate (I2C_CR)—Bit 12
2
This bit selects the clock speed for the I C run clock.
•
•
0 = I2C module run clock rate equals the system clock rate, to a maximum 32MHz (default)
1 = I2C module run clock rate equals 3X system clock rate, to a maximum 96MHz
6.3.8.5
Reserved—Bits 11–0
This bit field is reserved. Each bit must be set to 0.
6.3.9
Peripheral Clock Enable Register 0 (SIM_PCE0)
The Peripheral Clock Enable register enables or disables clocks to the peripherals as a power savings
feature. Significant power savings are achieved by enabling only the peripheral clocks that are in use.
When a peripheral’s clock is disabled, that peripheral is in Stop mode. Accesses made to a module that has
its clock disabled will have no effect. The corresponding peripheral should itself be disabled while its clock
is shut off. IPBus writes are not possible.
Setting the PCE bit does not guarantee that the peripheral’s clock is running. Enabled peripheral clocks
will still become disabled in Stop mode, unless the peripheral’s Stop Disable control in the SDn register
is set to 1.
Note:
The MSCAN module supports extended power management capabilities, including Sleep,
Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. Refer to
the 56F802X and 56F803XPeripheral Reference Manual for details.
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Read
Write
CMPB CMPA DAC1 DAC0
ADC
I2C
QSCI0
QSPI0
PWM
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-10 Peripheral Clock Enable Register 0 (SIM_PCE0)
Comparator B Clock Enable (CMPB)—Bit 15
6.3.9.1
•
•
0 = The clock is not provided to the Comparator B module (the Comparator B module is disabled)
1 = The clock is enabled to the Comparator B module
56F8036 Data Sheet, Rev. 3
88
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.9.2
Comparator A Clock Enable (CMPA)—Bit 14
•
•
0 = The clock is not provided to the Comparator A module (the Comparator A module is disabled)
1 = The clock is enabled to the Comparator A module
6.3.9.3
Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13
•
•
0 = The clock is not provided to the DAC1 module (the DAC1 module is disabled)
1 = The clock is enabled to the DAC1 module
6.3.9.4
Digital-to-Analog Clock Enable 0 (DAC0)—Bit 12
•
•
0 = The clock is not provided to the DAC0 module (the DAC0 module is disabled)
1 = The clock is enabled to the DAC0 module
6.3.9.5
Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.9.6
Analog-to-Digital Converter Clock Enable (ADC)—Bit 10
•
•
0 = The clock is not provided to the ADC module (the ADC module is disabled)
1 = The clock is enabled to the ADC module
6.3.9.7
Reserved—Bits 9–7
This bit field is reserved. It must be set to 0.
6.3.9.8
Inter-Integrated Circuit IPBus Clock Enable (I2C)—Bit 6
•
•
0 = The clock is not provided to the I2C module (the I2C module is disabled)
1 = The clock is enabled to the I2C module
6.3.9.9
Reserved—Bit 5
This bit field is reserved. It must be set to 0.
6.3.9.10 QSCI 0 Clock Enable (QSCI0)—Bit 4
•
•
0 = The clock is not provided to the QSCI0 module (the QSCI0 module is disabled)
1 = The clock is enabled to the QSCI0 module
6.3.9.11 Reserved—Bit 3
This bit field is reserved. It must be set to 0.
6.3.9.12 QSPI 0 Clock Enable (QSPI0)—Bit 2
•
•
0 = The clock is not provided to the QSPI0 module (the QSPI0 module is disabled)
1 = The clock is enabled to the QSPI0 module
6.3.9.13 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
89
6.3.9.14 PWM Clock Enable (PWM)—Bit 0
•
•
0 = The clock is not provided to the PWM module (the PWM module is disabled)
1 = The clock is enabled to the PWM module
6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1)
See Section 6.3.9 for general information about Peripheral Clock Enable registers.
Base + $D
Read
15
14
PIT2
0
13
PIT1
0
12
PIT0
0
11
10
9
8
7
6
5
4
3
TA3
0
2
TA2
0
1
TA1
0
0
TA0
0
0
0
0
0
0
0
0
0
0
Write
0
0
0
0
0
0
0
0
0
RESET
Figure 6-11 Peripheral Clock Enable Register 1 (SIM_PCE1)
6.3.10.1 Reserved—Bit 15
This bit field is reserved. It must be set to 0.
6.3.10.2 Programmable Interval Timer 2 Clock Enable (PIT2)—Bit 14
•
•
0 = The clock is not provided to the PIT2 module (the PIT2 module is disabled)
1 = The clock is enabled to the PIT2 module
6.3.10.3 Programmable Interval Timer 1 Clock Enable (PIT1)—Bit 13
•
•
0 = The clock is not provided to the PIT1 module (the PIT1 module is disabled)
1 = The clock is enabled to the PIT1 module
6.3.10.4 Programmable Interval Timer 0 Clock Enable (PIT0)—Bit 12
•
•
0 = The clock is not provided to the PIT0 module (the PIT0 module is disabled)
1 = The clock is enabled to the PIT0 module
6.3.10.5 Reserved—Bits 11–4
This bit field is reserved. Each bit must be set to 0.
6.3.10.6 Quad Timer A, Channel 3 Clock Enable (TA3)—Bit 3
•
•
0 = The clock is not provided to the Timer A3 module (the Timer A3 module is disabled)
1 = The clock is enabled to the Timer A3 module
6.3.10.7 Quad Timer A, Channel 2 Clock Enable (TA2)—Bit 2
•
•
0 = The clock is not provided to the Timer A2 module (the Timer A2 module is disabled)
1 = The clock is enabled to the Timer A2 module
6.3.10.8 Quad Timer A, Channel 1 Clock Enable (TA1)—Bit 1
•
•
0 = The clock is not provided to the Timer A1 module (the Timer A1 module is disabled)
1 = The clock is enabled to the Timer A1 module
56F8036 Data Sheet, Rev. 3
90
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.10.9 Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0
•
•
0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)
1 = The clock is enabled to the Timer A0 module
6.3.11 Stop Disable Register 0 (SD0)
By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This
register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the
system to return to Run mode, this feature is provided so that selected peripherals can be left operating in
Stop mode for the purpose of generating a wake-up interrupt.
For power-conscious applications, it is recommended that only a minimum set of peripherals be
configured to remain operational during Stop mode.
Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless
their corresponding Stop Disable control is set to 1. Refer to the 56F802X and 56F803XPeripheral
Reference Manual for further details. Reads and writes cannot be made to a module that has its clock
disabled.
Note:
The MSCAN module supports extended power management capabilities including Sleep,
Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. For
details, refer to the 56F802X and 56F803XPeripheral Reference Manual.
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Read
Write
CMPB_ CMPA_ DAC1_ DAC0_
ADC_
SD
I2C_
SD
QSCI0_
SD
QSPI0_
SD
PWM_
SD
SD
SD
SD
SD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-12 Stop Disable Register 0 (SD0)
6.3.11.1 Comparator B Clock Stop Disable (CMPB_SD)—Bit 15
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.2 Comparator A Clock Stop Disable (CMPA_SD)—Bit 14
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.3 Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
91
6.3.11.4 Digital-to-Analog Converter 0 Clock Stop Disable (DAC0_SD)—Bit 12
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.5 Reserved—Bit 11
This bit field is reserved. It must be set to 0.
6.3.11.6 Analog-to-Digital Converter Clock Stop Disable (ADC_SD)—Bit 10
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.7 Reserved—Bits 9–7
This bit field is reserved. It must be set to 0.
6.3.11.8 Inter-Integrated Circuit Clock Stop Disable (I2C_SD)—Bit 6
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.9 Reserved—Bit 5
This bit field is reserved. It must be set to 0.
6.3.11.10 QSCI0 Clock Stop Disable (QSCI0_SD)—Bit 4
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.11 Reserved—Bit 3
This bit field is reserved. It must be set to 0.
6.3.11.12 QSPI0 Clock Stop Disable (QSPI0_SD)—Bit 2
Each bit controls clocks to the indicated peripheral.
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.13 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
56F8036 Data Sheet, Rev. 3
92
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.11.14 PWM Clock Stop Disable (PWM_SD)—Bit 0
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.12 Stop Disable Register 1 (SD1)
See Section 6.3.11 for general information about Stop Disable Registers.
Base + $F
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PIT2_ PIT1_
SD
PIT0_
SD
TA3_
SD
TA2_ TA1_ TA0_
SD
SD
SD
SD
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-13 Stop Disable Register 1 (SD1)
6.3.12.1 Reserved—Bit 15
This bit field is reserved. It must be set to 0.
6.3.12.2 Programmable Interval Timer 2 Clock Stop Disable (PIT2_SD)—Bit 14
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.3 Programmable Interval Timer 1 Clock Stop Disable (PIT1_SD)—Bit 13
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.4 Programmable Interval Timer 0 Clock Stop Disable (PIT0_SD)—Bit 12
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.5 Reserved—Bits 11–4
This bit field is reserved. Each bit must be set to 0.
6.3.12.6 Quad Timer A, Channel 3 Clock Stop Disable (TA3_SD)—Bit 3
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
93
6.3.12.7 Quad Timer A, Channel 2 Clock Stop Disable (TA2_SD)—Bit 2
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.8 Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.12.9 Quad Timer A, Channel 0 Clock Stop Disable (TA0_SD)—Bit 0
•
•
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE1
register
6.3.13 I/O Short Address Location Register High (SIM_IOSAHI)
In I/O short address mode, the instruction specifies only 6 LSBs of the effective address; the upper 18 bits
are “hard coded” to a specific area of memory. This scheme allows efficient access to a 64-location area
in peripheral space with single word instruction. Short address location registers specify the upper 18 bits
of I/O address, which are “hard coded”. These registers allow access to peripherals using I/O short address
mode, regardless of the physical location of the peripheral, as shown in Figure 6-14.
Instruction Portion
“Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_IOSALO Register
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
Figure 6-14 I/O Short Address Determination
With this register set, software can set the SIM_IOSAHI and SIM_IOSALO registers to point to its
peripheral registers and then use the I/O short addressing mode to access them.
Note:
Note:
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
56F8036 Data Sheet, Rev. 3
94
FreescaleSemiconductor
Preliminary
Register Descriptions
Base + $10
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ISAL[23:22]
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
RESET
Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI)
6.3.13.1 Reserved—Bits 15—2
This bit field is reserved. Each bit must be set to 0.
6.3.13.2 Input/Output Short Address Location (ISAL[23:22])—Bits 1–0
This field represents the upper two address bits of the “hard coded” I/O short address.
6.3.14 I/O Short Address Location Register Low (SIM_IOSALO)
See Section 6.3.13 for general information about I/O short address location registers.
Base + $11
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ISAL[21:6]
Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RESET
Figure 6-16 I/O Short Address Location Low Register (SIM_IOSALO)
6.3.14.1 Input/Output Short Address Location (ISAL[21:6])—Bits 15–0
This field represents the lower 16 address bits of the “hard coded” I/O short address.
6.3.15 Protection Register (SIM_PROT)
This register provides write protection of selected control fields for safety-critical applications. The
primary purpose is to prevent unsafe conditions due to the unintentional modification of these fields
between the onset of a code runaway and a reset by the COP watchdog. The GPIO and Internal Peripheral
Select Protection (GIPSP) field protects the contents of registers in the SIM and GPIO modules that control
inter-peripheral signal muxing and GPIO configuration. The Peripheral Clock Enable Protection (PCEP)
field protects the SIM registers’ contents, which contain peripheral clock controls. Some peripherals
provide additional safety features. Refer to the 56F802X and 56F803XPeripheral Reference Manual for
details.
Flexibility is provided so that write protection control values may themselves be optionally locked
(write-protected). Protection controls in this register have two bit values which determine the setting of the
control and whether the value is locked. While a protection control remains unlocked, protection can be
disabled and re-enabled by software. Once a protection control is locked, its value can only be altered by
a chip reset, which restores its default non-locked value.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
95
Base + $12
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
PCEP
GIPSP
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-17 Protection Register (SIM_PROT)
6.3.15.1 Reserved—Bits 15–4
This bit field is reserved. Each bit must be set to 0.
6.3.15.2 Peripheral Clock Enable Protection (PCEP)—Bits 3–2
These bits enable write protection of all fields in the PCEn, SDn, and PCR registers in the SIM module.
•
•
•
•
00 = Write protection off (default)
01 = Write protection on
10 = Write protection off and locked until chip reset
11 = Write protection on and locked until chip reset
6.3.15.3 GPIO and Internal Peripheral Select Protection (GIPSP)—Bits 1–0
These bits enable write protection of GPSn and IPSn registers in the SIM module and write protect all
GPIOx_PEREN, GPIOx_PPOUTM and GPIOx_DRIVE registers in GPIO modules.
•
•
•
•
00 = Write protection off (default)
01 = Write protection on
10 = Write protection off and locked until chip reset
11 = Write protection on and locked until chip reset
Note:
The PWM fields in the CLKOUT register are also write protected by GIPSP. They are reserved for
in-house test only.
6.3.16 SIM GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
Most I/O pins have an associated GPIO function. In addition to the GPIO function, I/O can be configured
to be one of several peripheral functions. The GPIOx_PEREN register within the GPIO module controls
the selection between peripheral or GPIO control of the I/O pins. The GPIO function is selected when the
GPIOx_PEREN bit for the I/O is 0. When the GPIOx_PEREN bit of the GPIO is 1, the fields in the GPSn
registers select which peripheral function has control of the I/O. Figure 6-18 illustrates the output path to
an I/O pin when an I/O has two peripheral functions. Similar muxing is required on peripheral function
inputs to receive input from the properly selected I/O pin.
56F8036 Data Sheet, Rev. 3
96
FreescaleSemiconductor
Preliminary
Register Descriptions
GPIOA6_PEREN
Register
SIM_GPSA0
Register
GPIOA6
0
GPIOA6 pin
PWM
FAULT0
0
1
1
Timer A0
Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control
In some cases, the user can choose peripheral function between several I/O, each of which have the option
to be programmed to control a specific peripheral function. If the user wishes to use that function, only one
of these I/O must be configured to control that peripheral function. If more than one I/O is configured to
control the peripheral function, the peripheral output signal will fan out to each I/O, but the peripheral input
signal will be the logical OR and AND of all the I/O signals.
Complete lists of I/O muxings are provided in Table 2-3.
The GPSn setting can be altered during normal operation, but a delay must be inserted between the time
when one function is disabled and another function is enabled.
Note:
After reset, all I/O pins are GPIO, except the JTAG pins and the RESET pin.
Base + $13
15
14
13
12
GPS_A6
0
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Read
Write
GPS_A5
GPS_A4
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-19 GPIO Peripheral Select Register 0 for GPIOA (SIM_GPSA0)
6.3.16.1 Reserved—Bits 15–13
This bit field is reserved. Each bit must be set to 0.
6.3.16.2 Configure GPIOA6 (GPS_A6)—Bit 12
This field selects the alternate function for GPIOA6.
•
•
0 = FAULT0 - PWM FAULT0 Input (default)
1 = TA0 - Timer A0
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
97
6.3.16.3 Configure GPIOA5 (GPS_A5)—Bits 11–10
This field selects the alternate function for GPIOA5.
•
•
•
•
00 = PWM5 - PWM5 (default)
01 = FAULT2 - PWM FAULT2 Input
10 = TA3 - Timer A3
11 = Reserved
6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8
This field selects the alternate function for GPIOA4.
•
•
•
•
00 = PWM4 - PWM4 (default)
01 = FAULT1 - PWM FAULT1 Input
10 = TA2 - Timer A2
11 = Reserved
6.3.16.5 Reserved—Bits 7–0
This bit field is reserved. Each bit must be set to 0.
6.3.17 SIM GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $14
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_A9
GPS_A8
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-20 GPIO Peripheral Select Register 1 for GPIOA (SIM_GPSA1)
6.3.17.1 Reserved—Bits 15–4
This bit field is reserved. Each bit must be set to 0.
6.3.17.2 Configure GPIOA9 (GPS_A9)—Bits 3–2
This field selects the alternate function for GPIOA9.
•
•
•
•
00 = FAULT2 - PWM FAULT2 Input (default)
01 = TA3 - Timer A3
10 = CMPBI1 - Comparator B Input 1
11 = Reserved
56F8036 Data Sheet, Rev. 3
98
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.17.3 Configure GPIOA8 (GPS_A8)—Bits 1–0
This field selects the alternate function for GPIOA8.
•
•
•
•
00 = FAULT1 - PWM FAULT1 Input (default)
01 = TA2 - Timer A2
10 = CMPAI1 - Comparator A Input 1
11 = Reserved
6.3.18 SIM GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $15
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
GPS_
B1
GPS_
B0
GPS_B6
GPS_B5
GPS_B3
GPS_B2
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-21 GPIO Peripheral Select Register 0 for GPIOB (SIM_GPSB0)
6.3.18.1 Reserved—Bit 15
This bit field is reserved. It must be set to 0.
6.3.18.2 Configure GPIOB6 (GPS_B6)—Bits 14–13
This field selects the alternate function for GPIOB6.
•
•
•
•
00 = RXD0 - QSCI0 Receive Data (default)
01 = SDA - I2C Serial
10 = CLKIN - External Clock Input
11 = Reserved
6.3.18.3 Configure GPIOB5 (GPS_B5)—Bits 12–11
This field selects the alternate function for GPIOB5.
•
•
•
•
00 = TA1 - Timer A1 (default)
01 = FAULT3 - PWM FAULT3 Input
10 = CLKIN - External Clock Input
11 = Reserved
6.3.18.4 Reserved—Bits 10–8
This bit field is reserved. Each bit must be set to 0.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
99
6.3.18.5 Configure GPIOB3 (GPS_B3)—Bits 7–6
This field selects the alternate function for GPIOB3.
•
•
•
•
00 = MOSI0 - QSPI0 Master Out/Slave In (default)
01 = TA3 - Timer A3
10 = PSRC1 - PWM2 / PWM3 Pair External Source
11 = Reserved
6.3.18.6 Configure GPIOB2 (GPS_B2)—Bits 5–4
This field selects the alternate function for GPIOB2.
•
•
•
•
00 = MISO0 QSPI0 Master In/Slave Out (default)
01 = TA2 - Timer A2
10 = PSRC0 - PWM0 / PWM1 Pair External Source
11 = Reserved
6.3.18.7 Reserved—Bit 3
This bit field is reserved. It must be set to 0.
6.3.18.8 Configure GPIOB1 (GPS_B1)—Bit 2
This field selects the alternate function for GPIOB1.
•
•
0 = SS0 - QSPI0 Slave Select (default)
1 = SDA - I2C Serial Data
6.3.18.9 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
6.3.18.10 Configure GPIOB0 (GPS_B0)—Bits 0
This field selects the alternate function for GPIOB0.
•
•
0 = SCLK0 - QSPI0 Serial Clock (default)
1 = SCL - I2C Serial Clock
6.3.19 SIM GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $16
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_
B9
GPS_
B8
GPS_
B7
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-22 GPIO Peripheral Select Register 1 for GPIOB (SIM_GPSB1)
56F8036 Data Sheet, Rev. 3
100
FreescaleSemiconductor
Preliminary
Register Descriptions
6.3.19.1 Reserved—Bits 15–5
This bit field is reserved. Each bit must be set to 0.
6.3.19.2 Configure GPIOB9 (GPS_B9)—Bit 4
This field selects the alternate function for GPIOB9.
•
•
0 = SDA - I2C Serial Data (default)
1 = CANRX - MSCAN Receive Data
6.3.19.3 Reserved—Bit 3
This bit field is reserved. It must be set to 0.
6.3.19.4 Configure GPIOB8 (GPS_B8)—Bit 2
This field selects the alternate function for GPIOB8.
•
•
0 = SCL - I2C Serial Clock (default)
1 = CANTX - MSCAN Transmit Data
6.3.19.5 Reserved—Bit 1
This bit field is reserved. It must be set to 0.
6.3.19.6 Configure GPIOB7 (GPS_B7)—Bit 0
This field selects the alternate function for GPIOB7.
•
•
0 = TXD0 - QSCI0 Transmit Data (default)
1 = SCL - I2C Serial Clock
6.3.20 SIM GPIO Peripheral Select Register for GPIOC and GPIOD
(SIM_GPSCD)
See Section 6.3.16 for general information about GPIO Peripheral Select Registers.
Base + $17
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPS_
D5
Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
Figure 6-23 GPIO Peripheral Select Register for GPIOC and GPIOD (SIM_GPSCD)
6.3.20.1 Reserved—Bits 15–13
This bit field is reserved. Each bit must be set to 0.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
101
6.3.20.2 Configure GPIOD5 (GPS_D5)—Bit 12
This field selects the alternate function for GPIOD5.
•
•
0 = XTAL - External Crystal Oscillator Output (default)
1 = CLKIN - External Clock Input
6.3.20.3 Reserved—Bits 11–0
This bit field is reserved. Each bit must be set to 0.
6.3.21 Internal Peripheral Source Select Register 0 for Pulse Width
Modulator (SIM_IPS0)
The internal integration of peripherals provides input signal source selection for peripherals where an input
signal to a peripheral can be fed from one of several sources. These registers are organized by peripheral
type and provide a selection list for every peripheral input signal that has more than one alternative source
to indicate which source is selected.
If one of the alternative sources is GPIO, the setting in these registers must be made consistently with the
settings in the GPSn and GPIOx_PEREN registers. Specifically, when an IPSn field is configured to select
an I/O pin as the source, then GPSn register settings must configure only one I/O pin to feed this peripheral
input function. Also, the GPIOx_PEREN bit for that I/O pin must be set to 1 to enable peripheral control
of the I/O.
GPIOA5_PEREN
Register
SIM_GPSA0
Register
GPIOA5
SIM_IPS0
Register
0
PWM5
GPIOA5 pin
00
01
10
1
0
PWM
FAULT2
Timer A3
1
Comparator A
Output (Internal)
Figure 6-24 Overall Control of Signal Source using SIM_IPSn Control
IPSn settings should not be altered while an affected peripheral is in an enabled (operational)
configuration. See the 56F802X and 56F803XPeripheral Reference Manual for details.
56F8036 Data Sheet, Rev. 3
102
FreescaleSemiconductor
Preliminary
Register Descriptions
Base + $18
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
IPS0_
FAULT2
IPS0_
FAULT1
IPS0_PSRC2
0
IPS0_PSRC1
0
IPS0_PSRC0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0)
6.3.21.1 Reserved—Bits 15–14
This bit field is reserved. Each bit must be set to 0.
6.3.21.2 Select Input Peripheral Source for FAULT2 (IPS0_FAULT2)—Bit 13
This field selects the alternate input peripheral source signal to feed PWM input FAULT2.
•
•
0 = I/O Pin (External) - Use PWM FAULT2 Input Pin (default)
1 = CMPBO (Internal) - Use Comparator B Output
6.3.21.3 Reserved—Bit 12
This bit field is reserved. It must be set to 0.
6.3.21.4 Select Input Peripheral Source for FAULT1 (IPS0_FAULT1)—Bit 11
This field selects the alternate input peripheral source signal to feed PWM input FAULT1.
•
•
0 = I/O pin (External) - Use PWM FAULT2 Input Pin (default)
1 = CMPAO (Internal) - Use Comparator A Output
6.3.21.5 Reserved—Bits 10–9
This bit field is reserved. Each bit must be set to 0.
6.3.21.6 Select Input Peripheral Source for PWM4/PWM5 Pair Source
(IPS0_PSRC2)—Bits 8–6
This field selects the alternate input peripheral source signal to feed PWM input PSRC2 as the
PWM4/PWM5 pair source.
•
•
•
000 = Reserved (default)
001 = TA3 (Internal) - Use Timer A3 output as PWM source
010 = ADC SAMPLE2 (Internal) - Use ADC SAMPLE2 result as PWM source
— If the ADC conversion result in SAMPLE2 is greater than the value programmed into the High Limit
register HLMT2, then PWM4 is set to 0 and PWM5 is set to 1
— If the ADC conversion result in SAMPLE2 is less than the value programmed into the Low Limit
register LLMT2, then PWM4 is set to 1 and PWM5 is set to 0
•
•
•
•
011 = CMPAO (Internal) - Use Comparator A output as PWM source
100 = CMPBO (Internal) - Use Comparator B output as PWM source
11x = Reserved
1x1 = Reserved
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
103
6.3.21.7 Select Input Peripheral Source for PWM2/PWM3 Pair Source
(IPS0_PSRC1)—Bits 5–3
This field selects the alternate input peripheral source signal to feed PWM input PSRC1 as the
PWM2/PWM3 pair source.
•
•
•
000 = I/O pin (External) - Use a PSRC1 input pin as PWM source (default)
001 = TA2 (Internal) - Use Timer A2 output as PWM source
010 = ADC SAMPLE1 (Internal) - Use ADC SAMPLE1 result as PWM source
— If the ADC conversion result in SAMPLE1 is greater than the value programmed into the High Limit
register HLMT1, then PWM2 is set to 0 and PWM3 is set to 1
— If the ADC conversion result in SAMPLE1 is less than the value programmed into the Low Limit
register LLMT2, then PWM2 is set to 1 and PWM3 is set to 0
•
•
•
•
011 = CMPAO (Internal) - Use Comparator A output as PWM source
100 = CMPBO (Internal) - Use Comparator B output as PWM source
11x = Reserved
1x1 = Reserved
6.3.21.8 Select Input Peripheral Source for PWM0/PWM1 Pair Source
(IPS0_PSRC0)—Bits 2–0
This field selects the alternate input peripheral source signal to feed PWM input PSRC0 as the
PWM0/PWM1 pair source.
•
•
•
000 = I/O pin (External) - Use a PSRC0 input pin as PWM source (default)
001 = TA0 (Internal) - Use Timer A0 output as PWM source
010 = ADC SAMPLE0 (Internal) - Use ADC SAMPLE0 result as PWM source
— If the ADC conversion result in SAMPLE0 is greater than the value programmed into the High Limit
register HLMT1, then PWM0 is set to 0 and PWM1 is set to 1
— If the ADC conversion result in SAMPLE0 is less than the value programmed into the Low Limit
register LLMT2, then PWM0 is set to 1 and PWM1 is set to 0
•
•
•
•
011 = CMPAO (Internal) - Use Comparator A output as PWM source
100 = CMPBO (Internal) - Use Comparator B output as PWM source
11x = Reserved
1x1 = Reserved
6.3.22 Internal Peripheral Source Select Register 1 for Digital-to-Analog
Converters (SIM_IPS1)
See Section 6.3.21 for general information about Internal Peripheral Source Select registers.
56F8036 Data Sheet, Rev. 3
104
FreescaleSemiconductor
Preliminary
Register Descriptions
Base + $19
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
IPS1_DSYNC1
0
IPS1_DSYNC0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1)
6.3.22.1 Reserved—Bits 15–7
This bit field is reserved. Each bit must be set to 0.
6.3.22.2 Select Input Peripheral Source for SYNC Input to DAC 1
(IPS1_DSYNC1)—Bits 6–4
This field selects the alternate input source signal to feed DAC1 SYNC input.
•
•
•
•
•
•
•
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
6.3.22.3 Reserved—Bit 3
This bit field is reserved. Each bit must be set to 0.
6.3.22.4 Select Input Peripheral Source for SYNC Input to DAC 0
(IPS1_DSYNC0)—Bits 2–0
This field selects the alternate input source signal to feed DAC0 SYNC input.
•
•
•
•
•
•
•
000 = PIT0 (Internal) - Use Programmable Interval Timer 0 Output as DAC SYNC input (default)
001 = PIT1 (Internal) - Use Programmable Interval Timer 1 Output as DAC SYNC input
010 = PIT2 (Internal) - Use Programmable Interval Timer 2 Output as DAC SYNC input
011 = PWM SYNC (Internal) - Use PWM reload synchronization signal as DAC SYNC input
100 = TA0 (Internal) - Use Timer A0 output as DAC SYNC input
101 = TA1 (Internal) - Use Timer A1 output as DAC SYNC input
11x = Reserved
6.3.23 Internal Peripheral Source Select Register 2 for Quad Timer A
(SIM_IPS2)
See Section 6.3.21 for general information about Internal Peripheral Source Select registers.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
105
Base + $1A
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IPS2_
TA3
IPS2_
TA2
IPS2_
TA1
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)
6.3.23.1 Reserved—Bits 15–13
This bit field is reserved. Each bit must be set to 0.
6.3.23.2 Select Input Peripheral Source for TA3 (IPS2_TA3)—Bit 12
This field selects the alternate input peripheral source signal to feed Quad Timer A, input 3.
•
•
0 = I/O pin (External) - Use Timer A3 input/output pin
1 = PWM SYNC (Internal) - Use PWM reload synchronization signal
6.3.23.3 Reserved—Bits 11–9
This bit field is reserved. Each bit must be set to 0.
6.3.23.4 Select Input Peripheral Source for TA2 (IPS2_TA2)—Bit 8
This field selects the alternate input source signal to feed Quad Timer A, input 2.
•
•
0 = I/O pin (External) - Use Timer A2 input/output pin
1 = CMPBO (Internal) - Use Comparator B output
6.3.23.5 Reserved—Bits 7–5
This bit field is reserved. Each bit must be set to 0.
6.3.23.6 Select Input Peripheral Source for TA1 (IPS2_TA1)—Bit 4
This field selects the alternate input peripheral source signal to feed Quad Timer A, input 1.
•
•
0 = I/O pin (External) - Use Timer A1 input/output pin
1 = CMPAO (Internal) - Use Comparator A output
6.3.23.7 Reserved—Bits 3–0
This bit field is reserved. Each bit must be set to 0.
For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A
module must be identical, at either the system clock rate or 3X system clock rate.
56F8036 Data Sheet, Rev. 3
106
FreescaleSemiconductor
Preliminary
Clock Generation Overview
6.4 Clock Generation Overview
The SIM uses the master clock (2X system clock) at a maximum of 64MHz from the OCCS module to
produce a system clock at a maximum of 32MHz for the peripheral, core, and memory. It divides the
master clock by two and gates it with appropriate power mode and clock gating controls. A 3X system
high-speed peripheral clock input from OCCS operates at three times the system clock at a maximum of
2
96MHz and can be an optional clock for PWM, Timer A, and I C modules. These clocks are generated by
gating the 3X system high-speed peripheral clock with appropriate power mode and clock gating controls.
The OCCS configuration controls the operating frequency of the SIM’s master clocks. In the OCCS, either
an external clock (CLKIN), a crystal oscillator, or the relaxation oscillator can be selected as the master
clock source (MSTR_OSC). An external clock can be operated at any frequency up to 64MHz. The crystal
oscillator can be operated only at a maximum of 8MHz. The relaxation oscillator can be operated at full
speed (8MHz), standby speed (400kHz using ROSB), or powered down (using ROPD). An 8MHz
MSTR_OSC can be multiplied to 196MHz using the PLL and postscaled to provide a variety of high-speed
clock rates. Either the postscaled PLL output or MSTR_OSC signal can be selected to produce the master
clocks to the SIM. When the PLL is selected, both the 3X system clock and the 2X system clock are
enabled. If the PLL is not selected, the 3X system clock is disabled and the master clock is MSTR_OSC.
In combination with the OCCS module, the SIM provides power modes (see Section 6.5), clock enables,
and clock rate controls to provide flexible control of clocking and power utilization. The clock rate
controls enable the high-speed clocking option for the two quad timers (TMRA and TMRB) and PWM,
but requires the PLL to be on and selected. Refer to the 56F802X and 56F803XPeripheral Reference
Manual for further details. The peripheral clock enable controls can be used to disable an individual
peripheral clock when it is not used.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
107
6.5 Power-Saving Modes
The 56F8036 operates in one of five Power-Saving modes, as shown in Table 6-2.
Table 6-2 Clock Operation in Power-Saving Modes
Mode
Core Clocks
Peripheral Clocks
Description
Device is fully functional
Run
Wait
Core and memory
clocks enabled
Peripheral clocks
enabled
Core and memory
clocks disabled
Peripheral clocks
enabled
Core executes WAIT instruction to enter this
mode.
Typically used for power-conscious applications.
Possible recoveries from Wait mode to Run
mode are:
1. Any interrupt
2. Executing a Debug mode entry command
during the 56800E core JTAG interface
3. Any reset (POR, external, software, COP)
Stop
Master clock generation in the OCCS
remains operational, but the SIM disables
the generation of system and peripheral
clocks.
Core executes STOP instruction to enter this
mode.
Possible recoveries from Stop mode to Run
mode are:
1. Interrupt from any peripheral configured in the
CTRL register to operate in Stop mode (TA0-3,
QSCI0, PIT0-1, CAN, CMPA-B)
2. Low-voltage interrupt
3. Executing a Debug mode entry command
using the 56800E core JTAG interface
4. Any reset (POR, external, software, COP)
Standby
The OCCS generates the master clock at a The user configures the OCCS and SIM to select
reduced frequency (400kHz). The PLL is
disabled and the high-speed peripheral
option is not available. System and
peripheral clocks operate at 200kHz.
the relaxation oscillator clock source (PRECS),
shut down the PLL (PLLPD), put the relaxation
oscillator in Standby mode (ROSB), and put the
large regulator in Standby (LRSTDBY). The
device is fully operational, but operating at a
minimum frequency and power configuration.
Recovery requires reversing the sequence used
to enter this mode (allowing for PLL lock time).
Power-Down
Master clock generation in the OCCS is
completely shut down. All system and
peripheral clocks are disabled.
The user configures the OCCS and SIM to enter
Standby mode as shown in the previous
description, followed by powering down the
oscillator (ROPD). The only possible recoveries
from this mode are:
1. External Reset
2. Power-On Reset
The power-saving modes provide additional power management options by disabling the clock,
reconfiguring the voltage regulator clock generation to manage power utilization, as shown in Table 6-2.
Run, Wait, and Stop modes provide methods of enabling/disabling the peripheral and/or core clocking as
a group. Stop disable controls for an individual peripheral are provided in the SDn registers to override the
56F8036 Data Sheet, Rev. 3
108
FreescaleSemiconductor
Preliminary
Resets
default behavior of Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues
to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode
to Run mode. Standby mode provides normal operation but at very low speed and power utilization. It is
possible to invoke Stop or Wait mode while in Standby mode for even greater levels of power reduction.
A 400kHz external clock can optionally be used in Standby mode to produce the required Standby 200kHz
system clock rate. Power-down mode, which selects the ROSC clock source but shuts it off, fully disables
the device and minimizes its power utilization but is only recoverable via reset.
When the PLL is not selected and the system bus is operating at 200kHz or less, the large regulator can be
put into its Standby mode (LRSTDBY) to reduce the power utilization of that regulator.
All peripherals, except the COP/watchdog timer, run at the system clock frequency or optional 3X system
2
clock for PWM, Timers, and I C. The COP timer runs at OSC_CLK / 1024. The maximum frequency of
operation is 32MHz.
6.6 Resets
The SIM supports five sources of reset, as shown in Figure 6-28. The two asynchronous sources are the
external reset pin and the Power-On Reset (POR). The three synchronous sources are the software reset
(SW reset), which is generated within the SIM itself by writing the SIM_CTRL register in Section 6.3.1,
the COP time-out reset (COP_TOR), and the COP loss-of-reference reset (COP_LOR). The reset
generation module has three reset detectors, which resolve into four primary resets. These are outlined in
Table 6-3. The JTAG circuitry is reset by the Power-On Reset.
Table 6-3 Primary System Resets
Reset Sources
Reset Signal
POR
External
Software
COP
Comments
EXTENDED_POR
X
Stretched version of POR released 64
OSC_CLK cycles after POR deasserts
CLKGEN_RST
X
X
X
X
Released 32 OSC_CLK cycles after all reset
sources, including EXTENDED_POR, have
released
PERIP_RST
CORE_RST
X
X
X
X
X
X
X
X
Releases 32 SYS_CLK cycles after the
CLKGEN_RST is released
Releases 32 SYS_CLK cycles after
PERIP_RST is released
Figure 6-28 provides a graphic illustration of the details in Table 6-3. Note that the POR_Delay blocks
use the OSC_CLK as their time base, since other system clocks are inactive during this phase of reset.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
109
EXTENDED_POR
JTAG
POR
pulse shaper
Power-On
Reset
(active low)
Memory
Subsystem
Delay 64
OSC_CLK
Clock
CLKGEN_RST
OCCS
COMBINED_RST
External
RESET IN
(active low)
PERIP_RST
Delay 32
OSC_CLK
Clock
RESET
Peripherals
pulse shaper
Delay 32
COP_TOR
(active low)
sys clocks
SW Reset
56800E
pulse shaper
Delay 32
sys clocks
COP_LOR
(active low)
pulse shaper
Delay blocks assert immediately and
deassert only after the programmed
number of clock cycles.
CORE_RST
Figure 6-28 Sources of RESET Functional Diagram (Test modes not included)
POR resets are extended 64 OSC_CLK clocks to stabilize the power supply and clock source. All resets
are subsequently extended for an additional 32 OSC_CLK clocks and 64 system clocks as the various
internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a
POR reset from when power comes on to when code is running is 28µS. An external reset generation
circuit may also be used. A description of how these resets are used to initialize the clocking system and
system modules is included in Section 6.7.
6.7 Clocks
The memory, peripheral and core clocks all operate at the same frequency (32MHz maximum) with the
exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option
to operate at 3X system clock. The SIM is responsible for clock distributions.
While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,
the ADC standby and conversion clocks are generated by a direct interface between the ADC and the
OCCS module.
56F8036 Data Sheet, Rev. 3
110
FreescaleSemiconductor
Preliminary
Clocks
The deassertion sequence of internal resets coordinates the device start up, including the clocking system
start up. The sequence is described in the following steps:
1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is
reached, the POR reset will release.
2. The release of POR reset permits operation of the POR reset extender. The POR extender generates
an extended POR reset, which is released 64 OSC_CLK cycles after POR reset. This provides an
additional time period for the clock source and power to stabilize.
3. A Combined reset consists of the OR of the extended POR reset, the external reset, the COP reset
and Software reset. The entire device, except for the POR extender, is held reset as long as
Combined reset is asserted. The release of Combined reset permits operation of the CTRL register,
the Synchronous reset generator, and the CLKGEN reset extender.
4. The Synchronous reset generator generates a reset to the Software and COP reset logic. The COP
and Software reset logic is released three OSC_CLK cycles after Combined reset deasserts. This
provides a reasonable minimum duration to the reset for these specialized functions.
5. The CLKGEN reset extender generates the CLKGEN reset used by the clock generation logic. The
CLKGEN reset is released 32 OSC_CLK cycles after Combined reset deasserts. This provides a
window in which the SIM stabilizes the master clock inputs to the clock generator.
6. The release of CLKGEN reset permits operation of the clock generation logic and the Peripheral
reset extender. The Peripheral reset extender generates the Peripheral reset, which is released 32
SYS_CLK cycles after CLKGEN reset. This provides a window in which peripheral and core logic
remain clocked, but in reset, so that synchronous resets can be resolved.
7. The release of Peripheral reset permits operation of the peripheral logic and the Core reset extender.
The Core reset extender generates the Core reset, which is released 32 SYS_CLK cycles after the
Peripheral reset. This provides a window in which critical peripheral start-up functions, such as
Flash Security in the Flash memory, can be implemented.
8. The release of Core reset permits execution of code by the 56800E core and marks the end of the
system start-up sequence.
Figure 6-29 illustrates clock relationships to one another and to the various resets as the device comes out
of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external
reset, COP and Software reset). In the 56F8036, this signal will be stretched by the SIM for a period of
time (up to 96 OSC_CLK clock cycles, depending upon the status of the POR) to create the clock
generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with
the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK
cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK
cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge
of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals
(for example, the Flash interface unit) set-up time prior to the 56800E core becoming active.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
111
Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles
for Combined reset extension
RST
MSTR_OSC
Switch on falling OSC_CLK
96 MSTR_OSC cycles
CKGEN_RST
2X SYS_CLK
SYS_CLK
SYS_CLK_D
SYS_CLK_DIV2
PERIP_RST
32 SYS_CLK cycles delay
Switch on falling SYS_CLK
Switch on falling SYS_CLK
32 SYS_CLK cycles delay
CORE_RST
Figure 6-29 Timing Relationships of Reset Signal to Clocks
6.8 Interrupts
The SIM generates no interrupts.
Part 7 Security Features
The 56F8036 offers security features intended to prevent unauthorized users from reading the contents of
the Flash Memory (FM) array. The 56F8036’s Flash security consists of several hardware interlocks that
prevent unauthorized users from gaining access to the Flash array.
Note, however, that part of the security must lie with the user’s code. An extreme example would be user’s
code that includes a subroutine to read and transfer the contents of the internal program to QSCI, QSPI or
another peripheral, as this code would defeat the purpose of security. At the same time, the user may also
wish to put a “backdoor” in his program. As an example, the user downloads a security key through the
QSCI, allowing access to a programming routine that updates parameters stored in another section of the
Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8036 can be secured by
programming the security bytes located in the FM configuration field, which are located at the last nine
56F8036 Data Sheet, Rev. 3
112
FreescaleSemiconductor
Preliminary
Flash Access Lock and Unlock Mechanisms
words of Program Flash. These non-volatile bytes will keep the device secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security. Refer to
the Flash Memory chapter in the 56F802X and 56F803XPeripheral Reference Manual for the state of
the security bytes and the resulting state of security. When Flash security mode is enabled in accordance
with the method described in the Flash Memory module chapter, the 56F8036 will disable the core EOnCE
debug capabilities. Normal program execution is otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
The 56F8036 has several operating functional and debug modes. Effective Flash security must address
operating mode selection and anticipate modes in which the on-chip Flash can be read without explicit user
permission.
7.2.1
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE
port functionality is mapped. When the 56F8036 boots, the chip-level JTAG TAP (Test Access Port) is
active and provides the chip’s boundary scan capability and access to the ID register, but proper
implementation of Flash security will block any attempt to access the internal Flash memory via the
EOnCE port when security is enabled.
7.2.2
Flash Lockout Recovery Using JTAG
If a user inadvertently enables security on the 56F8036, the only lockout recovery mechanism is the
complete erasure of the internal Flash contents, including the configuration field, and thus disables security
(the protection register is cleared). This does not compromise security, as the entire contents of the user’s
secured code stored in Flash are erased before security is disabled on the 56F8036 on the next reset or
power-up sequence.
To start the lockout recovery sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must
first be shifted into the chip-level TAP controller’s instruction register. Once the
LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value
must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user
must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence.
The controller must remain in this state until the erase sequence has completed. Refer to the 56F802X and
56F803XPeripheral Reference Manual for more details, or contact Freescale.
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
(by advancing the TAP state machine to the reset state) and the 56F8036 (by asserting external chip
reset) to return to normal unsecured operation.
7.2.3
Flash Lockout Recovery using CodeWarrior
CodeWarrior can unlock a device using the command sequence described in Section 7.2.2 by selecting the
Debug menu, then selecting DSP56800E, followed by Unlock Flash.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
113
Another mechanism is also built into CodeWarrior using the device’s memory configuration file. The
command “Unlock_Flash_on_Connect1” in the .cfg file accomplishes the same task as using the Debug
menu.
7.2.4
Product Analysis
The recommended method of unsecuring a programmed 56F8036 for product analysis of field failures is
via the backdoor key access. The customer would need to supply Technical Support with the backdoor key
and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows
backdoor key access must be set.
An alternative method for performing analysis on a secured microcontroller would be to mass-erase and
reprogram the Flash with the original code, but modify the security bytes.
To insure that a customer does not inadvertently lock himself out of the 56F8036 during programming, it
is recommended that the user program the backdoor access key first, the application code second, and the
security bytes within the FM configuration field last.
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F802X and
56F803XPeripheral Reference Manual and contains only chip-specific information. This information
supersedes the generic information in the 56F802X and 56F803XPeripheral Reference Manual.
8.2 Configuration
There are four GPIO ports defined on the 56F8036. The width of each port, the associated peripheral and
reset functions are shown in Table 8-1. The specific mapping of GPIO port pins is shown in Table 8-2.
Additional details are shown in Tables 2-2 and 2-3.
Table 8-1 GPIO Ports Configuration
Available
GPIO Port
Pins in
Peripheral Function
Reset Function
56F8036
PWM, Timer, QSPI, Comparator, Reset
GPIO, RESET
A
B
12
11
QSPI, I2C, PWM, Clock, MSCAN,
Comparator, Timer
GPIO
ADC, Comparator, QSCI
GPIO
C
D
10
6
Clock, Oscillator, DAC, JTAG
GPIO, JTAG
56F8036 Data Sheet, Rev. 3
114
FreescaleSemiconductor
Preliminary
Configuration
Table 8-2 GPIO External Signals Map
LQFP
Peripheral Function
Package Pin
Notes
GPIO Function
GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
PWM0
44
43
35
36
33
Defaults to A0
Defaults to A1
Defaults to A2
Defaults to A3
PWM1
PWM2
PWM3
PWM4 / TA2 / FAULT1
SIM register SIM_GPS is used to
select between PWM4, TA2, and
FAULT1.
Defaults to A4
GPIOA5
GPIOA6
PWM5 / TA3 / FAULT2
FAULT0 / TA0
29
26
SIM register SIM_GPS is used to
select between PWM5, TA3, and
FAULT2.
Defaults to A5
SIM register SIM_GPS is used to
select between FAULT0 and TA0.
Defaults to A6
GPIOA7
GPIOA8
RESET
23
28
Defaults to RESET
FAULT1 / TA2 / CMPAI1
SIM register SIM_GPS is used to
select between FAULT1, TA2, and
CMPAI1.
Defaults to A8
GPIOA9
FAULT2 / TA3 / CMPBI1
5
SIM register SIM_GPS is used to
select between FAULT2, TA3, and
CMPBI1.
Defaults to A9
GPIOA10
GPIOA11
GPIOB0
CMPAI2
27
6
Defaults to A10
Defaults to A11
CMPBI2
SCLK0 / SCL
32
SIM register SIM_GPS is used to
select between SCLK and SCL.
Defaults to B0
GPIOB1
GPIOB2
SS0 / SDA
2
SIM register SIM_GPS is used to
select between SS0 and SDA.
Defaults to B1
MISO0 / TA2 / PSRC0
25
SIM register SIM_GPS is used to
select between MISO0, TA2, and
PSRC0.
Defaults to B2
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
115
Table 8-2 GPIO External Signals Map (Continued)
LQFP
Package Pin
Notes
GPIO Function
Peripheral Function
GPIOB3
MOSI0 / TA3 / PSRC1
24
SIM register SIM_GPS is used to
select between MOSI0, TA3 and
PSRC1.
Defaults to B3
GPIOB5
GPIOB6
TA1 / FAULT3 / CLKIN
4
1
SIM register SIM_GPS is used to
select between TA1, FAULT3, and
CLKIN.
CLKIN functionality is enabled using
the PLL Control Register within the
OCCS block.
Defaults to B5
RXD0 / SDA / CLKIN
SIM register SIM_GPS is used to
select between RXD0, SDA, and
CLKIN.
CLKIN functionality is enabled using
the PLL Control Register within the
OCCS block.
Defaults to B6
GPIOB7
GPIOB8
GPIOB9
TXD0 / SCL
3
SIM register SIM_GPS is used to
select between TXD0 and SCL.
Defaults to B7
SCL / CANTX
SDA / CANRX
42
34
SIM register SIM_GPS is used to
select between SCL and CANTX.
Defaults to B8
SIM register SIM_GPS is used to
select between SDA and CANRX.
Defaults to B9
GPIOB10
GPIOB11
GPIOC0
CMPAO
22
46
17
Defaults to B10
Defaults to B11
CMPBO
ANA0 / CMPAI3
SIM register SIM_GPS is used to
select between ANA0 and CMPAI3.
Defaults to C0
GPIOC1
GPIOC2
ANA1
16
15
Defaults to C1
ANA2 / VREFHA
SIM register SIM_GPS is used to
select between ANA2 and VREFHA
.
Defaults to C2
GPIOC3
GPIOC4
ANA3 / VREFLA
ANB0 / CMPBI3
14
8
SIM register SIM_GPS is used to
select between ANA3 and VREFLA
.
Defaults to C3
SIM register SIM_GPS is used to
select between ANB0 and CMPBI3.
Defaults to C4
56F8036 Data Sheet, Rev. 3
116
FreescaleSemiconductor
Preliminary
Reset Values
Table 8-2 GPIO External Signals Map (Continued)
LQFP
Package Pin
Notes
GPIO Function
Peripheral Function
ANB1
GPIOC5
GPIOC6
9
Defaults to C5
ANB2 / VREFHB
10
SIM register SIM_GPS is used to
select between ANB2 and VREFHB
.
Defaults to C6
GPIOC7
ANB3 / VREFLB
11
SIM register SIM_GPS is used to
select between ANB3 and VREFLB
.
Defaults to C7
GPIOC8
GPIOC12
GPIOD0
GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
ANA4
ANB4
TDI
18
7
Defaults to C8
Defaults to C12
Defaults to TDI
Defaults to TDO
Defaults to TCK
Defaults to TMS
Defaults to D4
45
48
21
47
41
40
TDO
TCK
TMS
EXTAL
XTAL / CLKIN
SIM register SIM_GPSCD is used to
select between XTAL and CLKIN.
Defaults to D5
8.3 Reset Values
Tables 8-1 and 8-2 detail registers for the 56F8036; Figures 8-1 through 8-4 summarize register maps and
reset values.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
117
Add.
Offset
Register Acronym
GPIOA_PUPEN
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
R
W
PU[15:0]
$0
$1
$2
$3
$4
$5
$6
RS
0
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
R
W
.0
.0
.0
.0
D[15:0]
GPIOA_DATA
GPIOA_DDIR
GPIOA_PEREN
GPIOA_IASSRT
GPIOA_IEN
RS
0
0
0
0
0
0
0
0
0
0
0
R
W
.0. .0. .0. .0.
DD[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
PE[15:0]
RS
0
0
0
0
0
0
0
R
W
0
0
0
0
0
0
0
0
0
IA[15:0]
RS
0
0
0
0
R
W
0
0
0
IEN[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
IEPOL[15:0]
GPIOA_IEPOL
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IPR[15:0]
$7
$8
$9
$A
$B
GPIOA_IPEND
GPIOA_IEDGE
GPIOA_PPOUTM
GPIOA_RDATA
GPIOA_DRIVE
RS
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
0
0
0
0
1
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
R
W
IES[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
OEN[15:0]
RS
0
0
1
0
1
0
1
0
1
1
R
W
RAW DATA[15:0]
RS
0
0
X
0
X
0
X
0
X
X
X
X
R
W
DRIVE[15:0]
RS
0
0
0
0
0
0
0
0
0
R
W
Read as 0
Reserved
Reset
RS
Figure 8-1 GPIOA Register Map Summary
56F8036 Data Sheet, Rev. 3
118
FreescaleSemiconductor
Preliminary
Reset Values
Add.
Offset
Register Acronym
GPIOB_PUPEN
15
0
14
0
13
0
12
0
11
10
9
8
7
6
5
4
3
2
1
0
R
W
PU[15:0]
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
RS
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
R
W
D[15:0]
GPIOB_DATA
GPIOB_DDIR
RS
0
0
0
0
0
0
0
0
0
0
R
W
DD[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
PE[15:0]
GPIOB_PEREN
GPIOB_IASSRT
GPIOB_IEN
RS
0
0
0
0
0
0
0
0
0
0
R
W
IA[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
IEN[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
IEPOL[15:0]
GPIOB_IEPOL
GPIOB_IPEND
GPIOB_IEDGE
GPIOB_PPOUTM
GPIOB_RDATA
GPIOB_DRIVE
RS
0
0
0
0
0
0
0
0
0
0
R
W
IPR[15:0]
RS
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
0
0
0
0
1
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
R
W
IES[15:0]
RS
0
0
0
0
0
0
0
0
0
0
R
W
OEN[15:0]
RS
0
0
0
0
1
0
1
0
1
1
R
W
RAW DATA[15:0]
RS
0
0
0
0
X
0
X
0
X
X
X
X
R
W
DRIVE[15:0]
RS
0
0
0
0
0
0
0
0
0
R
W
Read as 0
Reserved
Reset
RS
Figure 8-2 GPIOB Register Map Summary
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
119
Add.
Offset
Register Acronym
GPIOC_PUPEN
15
0
14
0
13
0
12
11
0
10
0
9
0
8
0
7
6
5
4
3
2
1
0
R
W
PU [15:0]
1
PU
D
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
RS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
R
W
D [15:0]
0
GPIOC_DATA
GPIOC_DDIR
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
DD [15:0]
0
DD
PE
IA
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
PE [15:0]
0
GPIOC_PEREN
GPIOC_IASSRT
GPIOC_IEN
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IA [15:0]
0
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IEN [15:0]
0
IEN
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IEPOL [15:0]
0
IEPOL
GPIOC_IEPOL
GPIOC_IPEND
GPIOC_IEDGE
GPIOC_PPOUTM
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
IPR [15:0]
0
IPR
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
R
W
IES [15:0]
0
IES
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
OEN [15:0]
1
OEN
RS
1
0
1
0
1
0
1
0
1
0
1
0
1
0
RAW DATA
[15:0]
R
RAW DATA
$A
$B
GPIOC_RDATA
GPIOC_DRIVE
W
RS
X
0
X
0
X
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
X
X
0
X
0
X
0
R
W
DRIVE [15:0]
0
DRIVE
RS
0
0
0
0
0
0
0
0
0
0
R
W
Read as 0
Reserved
Reset
RS
Figure 8-3 GPIOC Register Map Summary
56F8036 Data Sheet, Rev. 3
120
FreescaleSemiconductor
Preliminary
Reset Values
Add.
Offset
Register Acronym
GPIOD_PUPEN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
PU[15:0]
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
R
W
D[15:0]
GPIOD_DATA
GPIOD_DDIR
RS
0
0
R
W
DD[15:0]
RS
0
0
R
W
PE[15:0]
GPIOD_PEREN
GPIOD_IASSRT
GPIOD_IEN
RS
1
1
R
W
IA[15:0]
RS
0
0
R
W
IEN[15:0]
RS
0
0
R
W
IEPOL[15:0]
GPIOD_IEPOL
GPIOD_IPEND
GPIOD_IEDGE
GPIOD_PPOUTM
GPIOD_RDATA
GPIOD_DRIVE
RS
0
0
R
W
IPR[15:0]
RS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
0
0
0
1
X
0
0
0
1
X
0
0
0
1
0
0
0
0
1
0
0
1
X
0
R
W
IES[15:0]
RS
0
0
R
W
OEN[15:0]
RS
1
1
R
W
RAW DATA[15:0]
RS
X
X
X
X
R
W
DRIVE[15:0]
RS
0
0
0
0
0
0
R
W
Read as 0
Reserved
Reset
RS
Figure 8-4 GPIOD Register Map Summary
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
121
Part 9 Joint Test Action Group (JTAG)
9.1 56F8036 Information
Please contact your Freescale sales representative or authorized distributor for device/package-specific
BSDL information.
The TRST pin is not available in this package. The pin is tied to V in the package.
DD
The JTAG state machine is reset during POR and can also be reset via a soft reset by holding TMS high
for five rising edges of TCK, as described in the 56F802X and 56F803XPeripheral Reference Manual.
Part 10 Specifications
10.1 General Characteristics
The 56F8036 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The
term “5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels, combined with the ability to receive 5V levels without damage.
Absolute maximum ratings in Table 10-1 are stress ratings only, and functional operation at the maximum
is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to
the device.
Unless otherwise stated, all specifications within this chapter apply over the temperature range of -40ºC to
125ºC ambient temperature over the following supply ranges:
V
= V
= 0V, V = V
= 3.0–3.6V, CL < 50pF, f = 32MHz
SS
SSA
DD
DDA
OP
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
56F8036 Data Sheet, Rev. 3
122
FreescaleSemiconductor
Preliminary
General Characteristics
Table 10-1 Absolute Maximum Ratings
(VSS = 0V, VSSA = 0V)
Characteristic
Supply Voltage Range
Symbol
VDD
Notes
Min
-0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.3
- 0.4
- 0.3
—
Max
4.0
Unit
V
Analog Supply Voltage Range
ADC High Voltage Reference
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Digital Input Voltage Range
Oscillator Voltage Range
VDDA
VREFHx
ΔVDD
ΔVSS
VIN
4.0
V
4.0
V
0.3
V
0.3
V
Pin Groups 1, 2
Pin Group 4
6.0
V
VOSC
VINA
4.0
V
Analog Input Voltage Range
Pin Group 3
4.0
V
Input clamp current, per pin (VIN < 0)1
Output clamp current, per pin (VO < 0)1
VIC
-20.0
mA
VOC
—
-20.0
4.0
mA
V
Output Voltage Range
(Normal Push-Pull mode)
Pin Group 1
Pin Group 2
Internal
VOUT
- 0.3
Output Voltage Range
(Open Drain mode)
VOUTOD
- 0.3
- 0.3
6.0
4.0
V
V
Output Voltage Range (DAC)
VDAC
Ambient Temperature
Industrial
TA
- 40
- 55
105
150
°C
°C
Storage Temperature Range
(Extended Industrial)
TSTG
1. Continuous clamp current per pin is -2.0 mA
Default Mode
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET, GPIOA7
Pin Group 3: ADC and Comparator Analog Inputs
Pin Group 4: XTAL, EXTAL
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
123
10.1.1 ElectroStatic Discharge (ESD) Model
Table 10-2 56F8036 ESD Protection
Characteristic
Min
Typ
Max
Unit
ESD for Human Body Model (HBM)
ESD for Machine Model (MM)
2000
200
—
—
—
—
—
—
V
V
V
ESD for Charge Device Model (CDM)
750
6
Table 10-3 LQFP Package Thermal Characteristics
Value
(LQFP)
Characteristic
Symbol
Unit
Notes
Comments
Junction to ambient
Natural convection
Single layer board
(1s)
RθJA
41
34
°C/W
°C/W
2
Junction to ambient
Natural convection
Four layer board
(2s2p)
RθJMA
1, 2
Junction to ambient
(@200 ft/min)
Single layer board
(1s)
RθJMA
34
29
°C/W
°C/W
2
Junction to ambient
(@200 ft/min)
Four layer board
(2s2p)
RθJMA
1, 2
Junction to board
RθJB
RθJC
ΨJT
24
8
°C/W
°C/W
°C/W
4
3
5
Junction to case
Junction to package top
Natural Convection
2
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p
thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (R ), was simulated to be equivalent to the JEDEC specification JESD51-2
θJA
in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes
(2s2p, where “s” is the number of signal layers and “p” is the number of planes) per JESD51-6 and JESD51-7. The correct name
for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (R ), was simulated to be equivalent to the measured values using the cold plate
θJC
technique with the cold plate temperature used as the “case” temperature. The basic cold plate measurement technique is de-
scribed by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the
package is being used with a heat sink.
4. Junction to board thermal resistance, Theta-JB (R ), is a metric of the thermal resistance from the junction to the printed circuit
θJB
board determined per JESD51-8. Board temperature is measured on the top surface of the board near the package.
5. Thermal Characterization Parameter, Psi-JT (Y ), is the “resistance” from junction to reference point thermocouple on top center
JT
of case as defined in JESD51-2. Y is a useful value to use to estimate junction temperature in steady state customer
JT
environments.
6. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
7. See Section 12.1 for more details on thermal design considerations.
56F8036 Data Sheet, Rev. 3
124
FreescaleSemiconductor
Preliminary
General Characteristics
Table 10-4 Recommended Operating Conditions
(V = 0V, V = 0V, V = 0V)
REFL x
SSA
SS
Characteristic
Supply voltage
Symbol
Notes
Min
Typ
Max
Unit
VDD,
3
3.3
3.6
V
VDDA
ADC Reference Voltage High
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
VREFHx
ΔVDD
3.0
-0.1
-0.1
VDDA
0.1
V
V
V
0
0
ΔVSS
0.1
Device Clock Frequency
Using relaxation oscillator
Using external clock source
FSYSCLK
1
0
32
32
MHz
Input Voltage High (digital inputs)
Input Voltage Low (digital inputs)
VIH
VIL
Pin Groups 1, 2
Pin Groups 1, 2
Pin Group 4
2.0
5.5
0.8
V
V
-0.3
Oscillator Input Voltage High
VIHOSC
XTAL not driven by an external clock
XTAL driven by an external clock source
VDDA - 0.8
2.0
VDDA + 0.3
VDDA + 0.3
V
Oscillator Input Voltage Low
VILOSC
IOH
Pin Group 4
-0.3
0.8
V
Output Source Current High at VOH min.)1
Pin Group 1
Pin Group 1
—
—
-4
-8
mA
When programmed for low drive strength
When programmed for high drive strength
Output Source Current Low (at VOL max.)1
IOL
Pin Groups 1, 2
Pin Groups 1, 2
—
—
4
8
mA
When programmed for low drive strength
When programmed for high drive strength
Ambient Operating Temperature
(Extended Industrial)
TA
NF
-40
105
—
°C
Flash Endurance
(Program Erase Cycles)
TA = -40°C to
125°C
10,000
cycles
Flash Data Retention
TR
TJ <= 85°C avg
TJ <= 85°C avg
15
20
—
—
years
years
Flash Data Retention with <100
Program/Erase Cycles
tFLRET
—
1. Total chip source or sink current cannot exceed 75mA
Default Mode
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET, GPIOA7
Pin Group 3: ADC and Comparator Analog Inputs
Pin Group 4: XTAL, EXTAL
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
125
10.2 DC Electrical Characteristics
Table 10-5 DC Electrical Characteristics
At Recommended Operating Conditions
Test
Conditions
Characteristic
Symbol
Notes
Min
Typ
Max
Unit
Output Voltage High
Output Voltage Low
VOH
VOL
IIH
Pin Group 1
Pin Groups 1, 2
Pin Groups 1, 2
2.4
—
—
—
0
—
0.4
V
V
IOH = IOHmax
IOL = IOLmax
Digital Input Current High (a)
pull-up enabled or disabled
—
+/- 2.5
μA
VIN = 2.4V
to 5.5V
Comparator Input Current High
Oscillator Input Current High
IIHC
IIHOSC
IIL
Pin Group 3
Pin Group 3
—
—
0
0
+/- 2
+/- 2
μA
μA
μA
VIN = VDDA
VIN = VDDA
VIN = 0V
Digital Input Current Low1
pull-up enabled
pull-up disabled
Pin Groups 1, 2
-15
—
-30
0
-60
+/- 2.5
Comparator Input Current Low
Oscillator Input Current Low
DAC Output Voltage Range
IILC
Pin Group 3
Pin Group 3
Internal
—
—
0
0
+/- 2
+/- 2
μA
μA
V
VIN = 0V
VIN = 0V
—
IILOSC
VDAC
Typically
—
Typically
VSSA
+
VDDA -
40mV
40mV
Output Current 1
High Impedance State
IOZ
Pin Groups 1, 2
Pin Groups 1, 2
—
0
+/- 2.5
μA
—
Schmitt Trigger Input Hysteresis
Input Capacitance
VHYS
CIN
—
—
—
0.35
10
—
—
—
V
—
—
—
pF
pF
Output Capacitance
COUT
10
1. See Figure 10-1
Default Mode
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2: RESET, GPIOA7
Pin Group 3: ADC and Comparator Analog Inputs
Pin Group 4: XTAL, EXTAL
56F8036 Data Sheet, Rev. 3
126
FreescaleSemiconductor
Preliminary
DC Electrical Characteristics
2.0
0.0
- 2.0
- 4.0
- 6.0
- 8.0
- 10.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Volt
Figure 10-1 I /I vs. V (Typical; Pull-Up Disabled)
IN OZ
IN
Table 10-6 Current Consumption per Power Supply Pin
Typical @ 3.3V, 25°C
Maximum@ 3.6V, 25°C
Mode
Conditions
1
1
IDDA
IDDA
IDD
IDD
RUN
32MHz Device Clock
48mA
18.8mA
—
—
Relaxation Oscillator on
PLL powered on
Continuous MAC instructions with fetches from
Program Flash
All peripheral modules enabled. TMR and PWM
using 1X Clock
ADC/DAC powered on and clocked
Comparator powered on
WAIT
STOP
32MHz Device Clock
Relaxation Oscillator on
PLL powered on
Processor Core in WAIT state
All Peripheral modules enabled. TMR and PWM
using 1X Clock
29mA
0μA
0μA
—
—
—
—
ADC/DAC/Comparator powered off
4MHz Device Clock
5.4mA
Relaxation Oscillator on
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
127
Table 10-6 Current Consumption per Power Supply Pin (Continued)
Typical @ 3.3V, 25°C
Maximum@ 3.6V, 25°C
Mode
Conditions
1
1
IDDA
IDDA
IDD
IDD
STANDBY > STOP 100kHz Device Clock
Relaxation Oscillator in Standby mode
290μA
0μA
390μA
1μA
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC/DAC/Comparator powered off
Voltage regulator in Standby mode
POWERDOWN
Device Clock is off
190μA
0μA
250μA
1μA
Relaxation Oscillator powered off
PLL powered off
Processor Core in STOP state
All peripheral module and core clocks are off
ADC /DAC/Comparator powered off
Voltage Regulator in Standby mode
1. No Output Switching
All ports configured as inputs
All inputs Low
No DC Loads
Table 10-7 Power-On Reset Low-Voltage Parameters
Typ
2.7
Max
—
Unit
Min
2.58
—
Characteristic
Symbol
VEI3.3
VE12.5
VEIH
Low-Voltage Interrupt for 3.3V supply1
V
V
Low-Voltage Interrupt for 2.5V supply2
2.15
50
—
Low-Voltage Interrupt Recovery Hysteresis
—
—
mV
V
Power-On Reset3
POR
—
1.8
1.9
1. When V drops below V
, an interrupt is generated.
DD
EI3.3
2. When V drops below V
, an interrupt is generated.
DD
EI32.5
3. Power-On Reset occurs whenever the internally regulated 2.5V digital supply drops below 1.8V. While
power is ramping up, this signal remains active for as long as the internal 2.5V is below 2.15V or the 3.3V
1/O voltage is below 2.7V, no matter how long the ramp-up rate is. The internally regulated voltage is
typically 100mV less than V during ramp-up until 2.5V is reached, at which time it self-regulates.
DD
10.2.1 Voltage Regulator Specifications
The 56F8036 has two on-chip regulators. One supplies the PLL and relaxation oscillator. It has no external
pins and therefore has no external characteristics which must be guaranteed (other than proper operation
of the device). The second regulator supplies approximately 2.5V to the 56F8036’s core logic. This
regulator requires an external 4.4µF, or greater, capacitor for proper operation. Ceramic and tantalum
56F8036 Data Sheet, Rev. 3
128
FreescaleSemiconductor
Preliminary
AC Electrical Characteristics
capacitors tend to provide better performance tolerances. The output voltage can be measured directly on
the V
pin. The specifications for this regulator are shown in Table 10-8.
CAP
Table 10-8. Regulator Parameters
Characteristic
Symbol
ISS
Min
—
Typical
450
Max
650
30
Unit
mA
Short Circuit Current
Short Circuit Tolerance
(VCAP shorted to ground)
TRSC
—
—
minutes
10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in Table 10-5. Unless otherwise specified,
propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
between the 10% and 90% points, as shown in Figure 10-2.
Low
VIL
High
VIH
90%
50%
10%
Input Signal
Midpoint1
Fall Time
Note: The midpoint is VIL + (VIH – VIL)/2.
Rise Time
Figure 10-2 Input Signal Measurement References
Figure 10-3 shows the definitions of the following signal states:
•
•
•
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached VOL or VOH
•
Data Invalid state, when a signal level is in transition between VOL and VOH
Data2 Valid
Data2
Data1 Valid
Data1
Data3 Valid
Data3
Data
Tri-stated
Data Invalid State
Data Active
Data Active
Figure 10-3 Signal States
10.4 Flash Memory Characteristics
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
129
Table 10-9 Flash Timing Parameters
Characteristic
Symbol
Tprog
Terase
Tme
Min
20
Typ
—
Max
40
Unit
μs
Program time1
Erase time 2
20
—
—
ms
ms
Mass erase time
100
—
—
1. There is additional overhead which is part of the programming sequence. See the 56F802X and 56F803XPeripheral
Reference Manual for details.
2. Specifies page erase time. There are 512 bytes per page in the Program Flash memory.
10.5 External Clock Operation Timing
1
Table 10-10 External Clock Operation Timing Requirements
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
8
Unit
MHz
ns
Frequency of operation (external clock driver)2
Clock Pulse Width3
tPW
6.25
—
—
—
—
—
3
External Clock Input Rise Time4
trise
ns
External Clock Input Fall Time5
tfall
—
3
ns
1. Parameters listed are guaranteed by design.
2. See Figure 10-4 for details on using the recommended connection of an external clock driver.
3. The chip may not function if the high or low pulse width is smaller than 6.25ns.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
VIH
External
Clock
90%
50%
10%
90%
50%
10%
VIL
tfall
trise
tPW
tPW
Note: The midpoint is VIL + (VIH – VIL)/2.
Figure 10-4 External Clock Timing
56F8036 Data Sheet, Rev. 3
130
FreescaleSemiconductor
Preliminary
Phase Locked Loop Timing
10.6 Phase Locked Loop Timing
Table 10-11 PLL Timing
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
—
Unit
MHz
MHz
MHz
µs
External reference crystal frequency for the PLL1
Internal reference relaxation oscillator frequency for the PLL
frosc
fop
—
96
—
—
—
8
—
PLL output frequency2 (24 x reference frequency)
PLL lock time3
192
40
—
—
tplls
100
0.37
—
Accumulated jitter using an 8MHz external crystal as the PLL source4
Cycle-to-cycle jitter
JA
%
tjitterpll
350
ps
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
is optimized for 8MHz input.
2. The core system clock will operate at 1/6 of the PLL output frequency.
3. This is the time required after the PLL is enabled to ensure reliable operation.
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
and using an 8MHz oscillator frequency.
10.7 Relaxation Oscillator Timing
Table 10-12 Relaxation Oscillator Timing
Characteristic
Symbol
Minimum
Typical
Maximum
Unit
Relaxation Oscillator output frequency1
Normal Mode
Standby Mode
fop
—
—
8.05
200
MHz
kHz
Relaxation Oscillator stabilization time2
troscs
—
—
1
3
ms
ps
Cycle-to-cycle jitter. This is measured on the CLKO
signal (programmed prescaler_clock) over 264 clocks3
tjitterrosc
400
—
Minimum tuning step size
Maximum tuning step size
—
—
—
.08
40
—
—
%
%
%
Variation over temperature -40°C to 150ºC4
Variation over temperature 0°C to 105ºC4
+1.0 to -1.5 +3.0 to -3.0
0 to +1 +2.0 to -2.0
—
%
1. Output frequency after application of 8MHz trim value, at 125°C.
2. This is the time required from Standby to Normal mode transition.
3. J is required to meet QSCI requirements.
A
4. See Figure 10-5
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
131
8.16
8.08
8
7.92
7.84
-50
-25
0
25
50
75
100
125
150
175
Degrees C (Junction)
Figure 10-5 Relaxation Oscillator Temperature Variation (Typical) After Trim at 125°C
56F8036 Data Sheet, Rev. 3
132
FreescaleSemiconductor
Preliminary
Reset, Stop, Wait, Mode Select, and Interrupt Timing
10.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Note:
All address and data buses described here are internal.
1,2
Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Characteristic
Symbol
tRA
Typical Min
Typical Max
Unit
ns
See Figure
Minimum RESET Assertion Duration
4T
—
—
10-6
—
Minimum GPIO pin Assertion for Interrupt
tIW
2T
96TOSC + 64T
—
—
97TOSC + 65T
6T
ns
RESET deassertion to First Address Fetch3
tRDA
tIF
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
ns
—
1. In the formulas, T = system clock cycle and T = oscillator clock cycle. For an operating frequency of 32MHz, T = 31.25ns. At
osc
8MHz (used during Reset and Stop modes), T = 125ns.
2. Parameters listed are guaranteed by design.
3. During Power-On Reset, it is possible to use the 56F8036 internal reset stretching circuitry to extend this period to 2^21T.
GPIO pin
(Input)
TIW
Figure 10-6 GPIO Interrupt Timing (Negative Edge-Sensitive)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
133
10.9 Serial Peripheral Interface (SPI) Timing
1
Table 10-14 SPI Timing
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
tC
10-7, 10-8,
10-9, 10-10
125
62.5
—
—
ns
ns
Enable lead time
Master
Slave
tELD
tELG
tCH
tCL
10-10
10-10
—
31
—
—
ns
ns
Enable lag time
Master
Slave
—
125
—
—
ns
ns
Clock (SCK) high time
Master
Slave
10-7, 10-8,
10-9, 10-10
50
31
—
—
ns
ns
Clock (SCK) low time
Master
Slave
10-10
50
31
—
—
ns
ns
Data set-up time required for inputs
Master
Slave
tDS
tDH
tA
10-7, 10-8,
10-9, 10-10
20
0
—
—
ns
ns
Data hold time required for inputs
Master
Slave
10-7, 10-8,
10-9, 10-10
0
2
—
—
ns
ns
Access time (time to data active from
high-impedance state)
Slave
10-10
10-10
4.8
3.7
15
ns
ns
Disable time (hold time to high-impedance state)
Slave
tD
15.2
Data Valid for outputs
Master
Slave (after enable edge)
tDV
10-7, 10-8,
10-9, 10-10
—
—
4.5
20.4
ns
ns
Data invalid
Master
Slave
tDI
tR
tF
10-7, 10-8,
10-9, 10-10
0
0
—
—
ns
ns
Rise time
Master
Slave
10-7, 10-8,
10-9, 10-10
—
—
11.5
10.0
ns
ns
Fall time
Master
Slave
10-7, 10-8,
10-9, 10-10
—
—
9.7
9.0
ns
ns
1. Parameters listed are guaranteed by design.
56F8036 Data Sheet, Rev. 3
134
FreescaleSemiconductor
Preliminary
Serial Peripheral Interface (SPI) Timing
SS
(Input)
SS is held High on master
tC
tR
tF
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV
Bits 14–1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-7 SPI Master Timing (CPHA = 0)
SS
(Input)
SS is held High on master
tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output)
tCH
tF
tCL
tCH
tR
SCLK (CPOL = 1)
(Output)
tDS
tDH
MISO
MSB in
tDI
Bits 14–1
LSB in
tDI(ref)
(Input)
tDV(ref)
tDV
Bits 14– 1
MOSI
(Output)
Master MSB out
tF
Master LSB out
tR
Figure 10-8 SPI Master Timing (CPHA = 1)
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
135
SS
(Input)
tC
tF
tELG
tCL
tR
SCLK (CPOL = 0)
(Input)
tCH
tELD
tCL
SCLK (CPOL = 1)
(Input)
tCH
tF
tA
tR
tD
MISO
(Output)
Slave MSB out
Bits 14–1
tDV
Slave LSB out
tDI
tDS
tDI
tDH
MOSI
(Input)
MSB in
Bits 14–1
LSB in
Figure 10-9 SPI Slave Timing (CPHA = 0)
SS
(Input)
tF
tC
tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELG
tELD
tCL
SCLK (CPOL = 1)
(Input)
tDV
tCH
tR
tD
Slave LSB out
tDI
LSB in
tA
tF
MISO
Slave MSB out
Bits 14–1
tDV
(Output)
tDS
tDH
MOSI
(Input)
MSB in
Bits 14–1
Figure 10-10 SPI Slave Timing (CPHA = 1)
56F8036 Data Sheet, Rev. 3
136
FreescaleSemiconductor
Preliminary
Quad Timer Timing
10.10 Quad Timer Timing
1, 2
Table 10-15 Timer Timing
Characteristic
Timer input period
Symbol
PIN
Min
2T + 6
1T + 3
125
Max
—
Unit
ns
See Figure
10-11
Timer input high / low period
Timer output period
PINHL
POUT
—
ns
10-11
—
ns
10-11
Timer output high / low period
POUTHL
50
—
ns
10-11
1. In the formulas listed, T = the clock cycle. For 32MHz operation, T = 31.25ns.
2. Parameters listed are guaranteed by design.
Timer Inputs
PINHL
PINHL
PIN
Timer Outputs
POUTHL
POUTHL
POUT
Figure 10-11 Timer Timing
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
137
10.11 Serial Communication Interface (SCI) Timing
1
Table 10-16 SCI Timing
Characteristic
Symbol
Min
—
Max
Unit
See Figure
—
Baud Rate2
BR
(fMAX/16)
Mbps
RXD3 Pulse Width
TXD4 Pulse Width
RXDPW
TXDPW
0.965/BR
1.04/BR
1.04/BR
ns
ns
10-12
0.965/BR
10-13
LIN Slave Mode
Deviation of slave node clock from
nominal clock rate before
synchronization
FTOL_UNSYNCH
FTOL_SYNCH
TBREAK
-14
-2
14
2
%
%
—
Deviation of slave node clock relative
to the master node clock after
synchronization
—
Minimum break character length
13
11
—
—
Master
node bit
periods
—
Slavenode
bit periods
—
1. Parameters listed are guaranteed by design.
2. f is the frequency of operation of the system clock in MHz, which is 32MHz for the 56F8036 device.
MAX
3. The RXD pin in QSCI0 is named RXD0.
4. The TXD pin in QSCI0 is named TXD0.
RXD
QSCI Receive
data pin
RXDPW
(Input)
Figure 10-12 RXD Pulse Width
TXD
QSCI Receive
data pin
TXDPW
(Input)
Figure 10-13 TXD Pulse Width
56F8036 Data Sheet, Rev. 3
138
FreescaleSemiconductor
Preliminary
Freescale’s Scalable Controller Area Network (MSCAN) Timing
10.12 Freescale’s Scalable Controller Area Network (MSCAN)
Timing
1
Table 10-17 MSCAN Timing
Characteristic
Baud rate
Bus wake-up detection
Symbol
BRCAN
Min
—
Max
1
Unit
Mbps
µs
TWAKEUP
TIPBUS
—
1. Parameters listed are guaranteed by design
MSCAN_RX
CAN receive
data pin
TWAKEUP
(Input)
Figure 10-14 Bus Wake-up Detection
2
10.13 Inter-Integrated Circuit Interface (I C) Timing
2
Table 10-18 I C Timing
Standard Mode
Minimum Maximum
Fast Mode
Minimum Maximum
Characteristic
Symbol
Unit
SCL Clock Frequency
fSCL
0
100
—
0
400
—
kHz
Hold time (repeated)
START condition. After
this period, the first clock
pulse is generated.
tHD; STA
4.0
0.6
μs
LOW period of the SCL
clock
tLOW
4.7
4.0
4.7
—
—
—
1.3
0.6
0.6
—
—
—
μs
μs
μs
μs
HIGH period of the SCL
clock
tHIGH
Set-up time for a repeated
START condition
tSU; STA
Data hold time for I2C bus
devices
01
3.452
—
01
0.92
—
tHD; DAT
2503
1003, 4
Data set-up time
tSU; DAT
ns
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
139
2
Table 10-18 I C Timing (Continued)
Standard Mode
Minimum Maximum
Fast Mode
Characteristic
Symbol
Unit
ns
Minimum
Maximum
5
Rise time of both SDA and
SCL signals
tr
tf
—
—
1000
300
—
300
20 +0.1Cb
5
Fall time of both SDA and
SCL signals
300
—
ns
20 +0.1Cb
Set-up time for STOP
condition
tSU; STO
4.0
4.7
0.6
μs
Bus free time between
STOP and START
condition
tBUF
—
1.3
0
—
μs
Pulse width of spikes that
must be suppressed by
the input filter
tSP
N/A
N/A
50
ns
2
1. The master mode I C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
2. The maximum t
must be met only if the device does not stretch the LOW period (t
) of the SCL signal.
HD; DAT
LOW
3. Set-up time in slave-transmitter mode is 1 iPBus clock period, if the TX FIFO is empty.
2
2
4. A Fast mode I C bus device can be used in a Standard mode I C bus system, but the requirement t
> = 250ns
SU; DAT
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
t
+ t
= 1000 + 250 = 1250ns (according to the Standard mode I C bus specification) before the SCL line is
rmax
SU; DAT
released.
5. C = total capacitance of the one bus line in pF
b
SDA
t
f
t
SU; DAT
t
t
t
t
t
t
SP
t
r
BUF
f
r
HD; STA
LOW
SCL
t
t
t
SU; STA
HD; STA
SU; STO
S
SR
P
S
t
t
HIGH
HD; DAT
2
Figure 10-15 Timing Definition for Fast and Standard Mode Devices on the I C Bus
56F8036 Data Sheet, Rev. 3
140
FreescaleSemiconductor
Preliminary
JTAG Timing
10.14 JTAG Timing
Table 10-19 JTAG Timing
Characteristic
Symbol
Min
DC
50
5
Max
Unit
MHz
ns
See Figure
TCK frequency of operation1
TCK clock pulse width
fOP
SYS_CLK/8
10-16
10-16
10-17
10-17
10-17
10-17
tPW
tDS
tDH
tDV
tTS
—
—
—
30
30
TMS, TDI data set-up time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
ns
5
ns
—
—
ns
ns
1. TCK frequency of operation must be less than 1/8 the processor rate.
1/fOP
tPW
tPW
VIH
VM
VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2
Figure 10-16 Test Clock Input Timing Diagram
TCK
(Input)
tDS
tDH
TDI
TMS
Input Data Valid
(Input)
tDV
TDO
(Output)
Output Data Valid
tTS
TDO
(Output)
Figure 10-17 Test Access Port Timing Diagram
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
141
10.15 Analog-to-Digital Converter (ADC) Parameters
1
Table 10-20 ADC Parameters
Parameter
DC Specifications
Symbol
Min
Typ
Max
Unit
Resolution
RES
fADIC
RAD
12
0.1
—
—
—
6
12
5.33
VREFH
13
Bits
MHz
V
ADC internal clock
Conversion range
VREFL
—
ADC power-up time2
tAIC cycles3
tAIC cycles3
tAIC cycles3
tAIC cycles3
tADPU
Recovery from auto standby
tREC
tADC
tADS
—
—
—
0
6
1
1
Conversion time
Sample time
Accuracy
—
—
Integral non-linearity4
(Full input signal range)
LSB5
LSB5
INL
—
—
+/- 3
+/- 5
+/- 1
Differential non-linearity
DNL
+/- .6
Monotonicity
GUARANTEED
+/- 4
Offset Voltage Internal Ref
VOFFSET
VOFFSET
EGAIN
—
—
—
+/- 9
+/- 12
mV
mV
—
Offset Voltage External Ref
Gain Error (transfer gain)
+/- 6
.998 to 1.002
1.01 to .99
ADC Inputs6 (Pin Group 3)
Input voltage (external reference)
VADIN
VADIN
IIA
VREFL
VSSA
—
—
VREFH
VDDA
+/- 2
—
V
V
Input voltage (internal reference)
Input leakage
—
0
μA
VREFH current
IVREFH
IADI
—
0
μA
Input injection current7, per pin
Input capacitance
—
—
3
mA
pF
CADI
XIN
—
See Figure 10-18
See Figure 10-18
—
Input impedance
—
—
Ohms
AC Specifications
Signal-to-noise ratio
SNR
THD
60
60
61
58
—
65
64
66
62
dB
dB
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal-to-noise plus distortion
Effective Number Of Bits
SFDR
SINAD
ENOB
dB
dB
10.0
Bits
1. All measurements were made at V = 3.3V, V
= 3.3V, and V = ground
REFL
DD
REFH
2. Includes power-up of ADC and V
3. ADC clock cycles
REF
4. INL measured from V = V
to V = V
IN REFH
IN
REFL
5. LSB = Least Significant Bit = 0.806mV
6. Pin groups are detailed following Table 10-1.
7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the
ADC.
56F8036 Data Sheet, Rev. 3
142
FreescaleSemiconductor
Preliminary
Equivalent Circuit for ADC Inputs
10.16 Equivalent Circuit for ADC Inputs
Figure 10-18 illustrates the ADC input circuit during sample and hold. S1 and S2 are always open/closed
at the same time that S3 is closed/open. When S1/S2 are closed and S3 is open, one input of the sample
and hold circuit moves to (V
- V
) / 2, while the other charges to the analog input voltage. When
REFHx
REFLx
the switches are flipped, the charge on C1 and C2 are averaged via S3, with the result that a single-ended
analog input is switched to a differential voltage centered about (V - V ) / 2. The switches
REFHx
REFLx
switch on every cycle of the ADC clock (open one-half ADC clock, closed one-half ADC clock). Note that
there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter
into the S/H output voltage, as S1 provides isolation during the charge-sharing phase.
One aspect of this circuit is that there is an on-going input current, which is a function of the analog input
voltage, V , and the ADC clock frequency.
REF
125Ω ESD Resistor
8pF noise damping capacitor
4
3
Analog Input
S1
C1
S/H
S3
C2
S2
(VREFHx - VREFLx ) / 2
2
1
C1 = C2 = 1pF
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
3. Equivalent resistance for the channel select mux; 100 ohms
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pF
Figure 10-18 Equivalent Circuit for A/D Loading
10.17 Comparator (CMP) Parameters
Table 10-21 CMP Parameters
Characteristic
Conditions/Comments
Symbol
Min
Typ
Max
Unit
Input Offset Voltage1
Within range of VDDA - .1V to
VSSA + .1V
VOFFSET
—
+/- 10
+/- 20
mV
Input Propagation Delay
Power-up time
tPD
—
—
35
45
ns
tCPU
TBD
TBD
1. No guaranteed specification within 0.1V of V
or V
SSA
DDA
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
143
10.18 Digital-to-Analog Converter (DAC) Parameters
Table 10-22 DAC Parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
DC Specifications
Resolution
12
TBD
TBD
—
12
2
bits
µS
Conversion time
Conversion rate
Power-up time
—
—
—
500.000
11
conv/sec
µS
Time from release of PWRDWN
signal until DACOUT signal is
valid
tDAPU
Accuracy
Integral non-linearity1
LSB2
LSB2
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
INL
—
—
+/- 3
+/- 8.0
< - 1
Differential non-linearity1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
DNL
+/- .8
Monotonicity
Offset error1
> 6 sigma monotonicity,
< 3.4 ppm non-monotonicity
guaranteed
+/- 25
—
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
VOFFSET
—
—
+/- 40
mV
Gain error1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
EGAIN
+/- .5
—
+/- 1.5
%
V
DAC Output
Output voltage range
Within 40mV of either VREFLX or
VREFHX
VOUT
VREFLX
+.04V
VREFHX
- .04V
AC Specifications
Signal-to-noise ratio
SNR
—
—
TBD
TBD
—
—
dB
dB
Spurious free dynamic
range
SFDR
Effective number of bits
ENOB
9
—
—
bits
1. No guaranteed specification within 5% of V
2. LSB = 0.806mV
or V
SSA
DDA
56F8036 Data Sheet, Rev. 3
144
FreescaleSemiconductor
Preliminary
Power Consumption
10.19 Power Consumption
See Section 10.1 for a list of IDD requirements for the 56F8036. This section provides additional detail
which can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
Total power = A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static component]
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
2
C, the internal [dynamic component], is classic C*V *F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
2
on the external pins of the chip. This is also commonly described as C*V *F, although simulations on two
of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Table 10-23 I/O Loading Coefficients at 10MHz
Intercept
Slope
8mA drive
4mA drive
1.3
0.11mW / pF
0.11mW / pF
1.15mW
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-23 provides coefficients for calculating power dissipated
in the I/O cells as a function of capacitive load. In these cases:
TotalPower = Σ((Intercept + Slope*Cload)*frequency/10MHz)
where:
•
•
•
Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
Cload is expressed in pF
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
145
Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found
to be fairly low when averaged over a period of time.
E, the external [static component], reflects the effects of placing resistive loads on the outputs of the
2
device. Sum the total of all V /R or IV to arrive at the resistive load contribution to power. Assume V = 0.5
for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving
10mA into LEDs, then P = 8*.5*.01 = 40mW.
In previous discussions, power consumption due to parasitics associated with pure input pins is ignored,
as it is assumed to be negligible.
56F8036 Data Sheet, Rev. 3
146
FreescaleSemiconductor
Preliminary
56F8036 Package and Pin-Out Information
Part 11 Packaging
11.1 56F8036 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8036. This device comes in a 48-pin
Low-profile Quad Flat Pack (LQFP). Figure 11-1 shows the package outline, Figure 11-2 shows the
mechanical parameters and Table 11-1 lists the pin-out.
ORIENTATION
GPIOB6 / RXD0 / SDA / CLKIN
GPIOB1 / SS0 / SDA
MARK
GPIOA3 / PWM3
GPIOA2 / PWM2
PIN 37
GPIOB7 / TXD0 / SCL
GPIOB9 / SDA / CANRX
PIN 1
GPIOA4 / PWM4 / TA2 / FAULT1
GPIOB5 / TA1 / FAULT3 / CLKIN
GPIOB0 / SCLK0 / SCL
GPIOA9 / FAULT2 / TA3 / CMPBI1
GPIOA11 / CMPBI2
V
DD
V
SS
GPIOC12 / ANB4
GPIOC4 / ANB0 & CMPBI3
GPIOC5 / ANB1
GPIOA5 / PWM5 / TA3 / FAULTA2
GPIOA8 / FAULTA1 / TA2 / CMPAI1
GPIOA10 / CMPAI2
GPIOC6 / ANB2 / V
PIN 25
REFHB
PIN 13
GPIOA6 / FAULT0 / TA0
GPIOC7 / ANB3 / V
REFLB
GPIOB2 / MISO0 / TA2 / PSRC0
V
DDA
Figure 11-1 Top View, 56F8036 48-Pin LQFP Package
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
147
1
Table 11-1 56F8036 48-Pin LQFP Package Identification by Pin Number
Pin
#
Pin
#
Pin
#
Pin
#
Signal Name
Signal Name
VSSA
Signal Name
Signal Name
VCAP
1
2
GPIOB6
RXD0 / SDA / CLKIN
13
14
25
26
GPIOB2
MISO0 / TA2 / PSRC0
37
38
GPIOB1
GPIOC3
GPIOA6
VDD
SS0 / SDA
ANA3 / VREFLA
FAULT0 / TA0
3
4
GPIOB7
TXD0 / SCL
15
16
GPIOC2
ANA2 / VREFHA
27
28
GPIOA10
CMPAI2
39
40
VSS
GPIOB5
TA1 / FAULT3 / CLKIN
GPIOC1
ANA1
GPIOA8
FAULT1 / TA2 /
CMPAI1
GPIOD5
XTAL / CLKIN
5
GPIOA9
FAULT2 / TA3 /
CMPBI1
17
GPIOC0
ANA0 & CMPAI3
29
GPIOA5
PWM5 / TA3 / FAULT2
41
GPIOD4
EXTAL
6
7
GPIOA11
CMPBI2
18
19
20
21
22
GPIOC8
ANA4
30
31
32
33
34
VSS
42
43
44
45
46
GPIOB8
SCL / CANTX
GPIOC12
ANB4
VSS
VDD
GPIOA1
PWM1
8
GPIOC4
ANB0 & CMPBI3
VCAP
GPIOB0
SCLK0 / SCL
GPIOA0
PWM0
9
GPIOC5
ANB1
TCI
GPIOD2
GPIOA4
PWM4 / TA2 / FAULT1
TDI
GPIOD0
10
GPIOC6
GPIOB10
GPIOB9
GPIOB11
ANB2 / VREFHB
CMPAO
SDA / CANRX
CMPBO
11
12
GPIOC7
ANB3 / VREFLB
23
24
RESET
GPIOA7
35
36
GPIOA2
PWM2
47
48
TMS
GPIOD3
VDDA
GPIOB3
MOSI0 / TA3 /
PSRC1
GPIOA3
PWM3
TDO
GPIOD1
1. Alternate signals are in italic
56F8036 Data Sheet, Rev. 3
148
FreescaleSemiconductor
Preliminary
56F8036 Package and Pin-Out Information
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
4X
0.200 AB T-U Z
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE AB IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
DETAIL Y
9
A
P
A1
48
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
37
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE AC.
1
36
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 PER SIDE. DIMENSIONS
AANDBDOINCLUDEMOLDMISMATCHAND
ARE DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION
SHALL NOT CAUSE THE D DIMENSION TO
EXCEED 0.350.
T
U
B
V
AE
AE
B1
V1
12
25
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076.
9. EXACT SHAPE OF EACH CORNER IS
OPTIONAL.
13
24
Z
MILLIMETERS
DIM MIN MAX
S1
A
A1
B
7.000 BSC
3.500 BSC
7.000 BSC
T, U, Z
S
B1
C
D
E
F
G
H
J
K
L
M
N
P
3.500 BSC
DETAIL Y
4X
1.400 1.600
0.170 0.270
1.350 1.450
0.170 0.230
0.500 BSC
0.050 0.150
0.090 0.200
0.500 0.700
0.200 AC T-U Z
0.080 AC
G
AB
AC
0
7
°
°
12 REF
°
0.090 0.160
0.250 BSC
0.150 0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
R
S
S1
V
V1
W
AA
AD
°
M
BASE METAL
TOP & BOTTOM
R
N
J
E
C
H
F
D
M
0.080
AC T-U Z
SECTION AE-AE
W
°
L
K
DETAIL AD
CASE 932-03
ISSUE F
AA
Figure 11-2 56F8036 48-Pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
149
Part 12 Design Considerations
12.1 Thermal Design Considerations
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
T = T + (R
x P )
D
J
A
θJΑ
where:
o
T
R
= Ambient temperature for the package ( C)
A
o
= Junction-to-ambient thermal resistance ( C/W)
θJΑ
P
= Power dissipation in the package (W)
D
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Unfortunately, there are two values in common usage: the value
determined on a single-layer board and the value obtained on a board with two planes. For packages such
as the PBGA, these values can be different by a factor of two. Which value is closer to the application
depends on the power dissipated by other components on the board. The value obtained on a single layer
board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the
internal planes is usually appropriate if the board has low-power dissipation and the components are well
separated.
When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
R
= R
+ R
θJA
θJC θCA
where:
R
R
R
= Package junction-to-ambient thermal resistance (°C/W)
= Package junction-to-case thermal resistance (°C/W)
= Package case-to-ambient thermal resistance (°C/W)
θJA
θJC
θCA
R
is device related and cannot be influenced by the user. The user controls the thermal environment to
θJC
change the case to ambient thermal resistance, R
. For instance, the user can change the size of the heat
θCA
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are not used, the
Thermal Characterization Parameter (Ψ ) can be used to determine the junction temperature with a
JT
measurement of the temperature at the top center of the package case using the following equation:
T = T + (Ψ x P )
J
T
JT
D
where:
o
T
Ψ
= Thermocouple temperature on top of package ( C)
= Thermal characterization parameter ( C/W)
T
o
JT
P
= Power dissipation in package (W)
D
56F8036 Data Sheet, Rev. 3
150
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
12.2 Electrical Design Considerations
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit.
Reliability of operation is enhanced if unused inputs are
tied to an appropriate voltage level.
Use the following list of considerations to assure correct operation of the 56F8036:
•
Provide a low-impedance path from the board power supply to each VDD pin on the 56F8036 and from the
board ground to each VSS (GND) pin
•
The minimum bypass requirement is to place 0.01–0.1µF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
tolerances.
•
•
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are as short as possible
Bypass the VDD and VSS with approximately 100µF, plus the number of 0.1µF ceramic capacitors
PCB trace lengths should be minimal for high-frequency signals
•
•
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
151
•
•
Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins
Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA are
recommended. Connect the separate analog and digital power and ground planes as close as possible to
power supply outputs. If both analog circuit and digital circuit are powered by the same power supply, it is
advisable to connect a small inductor or ferrite bead in serial with both VDDA and VSSA traces.
•
It is highly desirable to physically separate analog components from noisy digital components by ground
planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog
ground trace around an analog signal trace to isolate it from digital traces.
•
•
•
•
Because the Flash memory is programmed through the JTAG/EOnCE port, QSPI, QSCI, or I2C, the
designer should provide an interface to this port if in-circuit Flash programming is desired
If desired, connect an external RC circuit to the RESET pin. The Resistor value should be in the range of
4.7k—10k; the Capacitor value should be in the range of 0.22µf - 4.7µf.
Add a 3.3k external pull-up on the TMS pin of the JTAG port to keep EOnce in a restate during normal
operation if JTAG converter is not present
During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pull-up
enable. The typical value of internal pull-up is around 110K. These internal pull-ups can be disabled by
software.
•
•
To eliminate PCB trace impedance effect, each ADC input should have a 33pf-10 ohm RC filter
Device GPIOs have only a down (substrate) diode on the GPIO circuit. Devices do not have a positive clamp
diode because GPIOs use a floating gate structure to tolerate 5V input. The absolute maximum clamp
current is -20mA at Vin less than 0V. The continuous clamp current is -2mA at Vin less than 0V. If positive
voltage spikes are a concern, a positive clamp is recommended.
Part 13 Ordering Information
Table 13-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order devices.
Table 13-1 56F8036 Ordering Information
Ambient
Temperature
Range
Supply
Voltage
Pin
Count
Frequency
(MHz)
Device
Package Type
Order Number
Low-Profile Quad Flat Pack (LQFP)
MC56F8036
3.0–3.6 V
48
32
-40° to + 105° C
MC56F8036VLF*
* This package is RoHS compliant.
56F8036 Data Sheet, Rev. 3
152
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
Part 14 Appendix
Register acronyms are revised from previous device data sheets to provide a cleaner register description.
A cross reference to legacy and revised acronyms are provided in the following table.
Note:
This table comprises all peripherals used in the 56F803x and 56F802x family; some of the peripherals
described here may not be present on this device.
Table 14-1 Legacy and Revised Acronyms
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
Analog-to-Digital Converter (ADC) Module
Control 1 Register
Control 2 Register
CTRL1
CTRL2
ADCR1
ADCR2
ADZCC
ADC_CTRL1
ADC_CTRL2
ADC_ZXCTRL
ADC_ADCR1
ADC_ADCR2
ADC_ADZCC
ADC_ADCR1
ADC_ADCR2
ADC_ADZCC
0xF080
0xF081
0xF082
Zero Crossing Control
Register
ZXCTRL
Channel List 1
Register
CLIST1
CLIST2
CLIST3
CLIST4
SDIS
ADLST1
ADLST2
ADC_CLIST1
ADC_CLIST2
ADC_CLIST3
ADC_CLIST4
ADC_SDIS
ADC_ADLST1
ADC_ADLST2
ADC_ADCLST3
ADC_ADCLST4
ADC_ADSDIS
ADC_ADLST1
ADC_ADLST2
ADC_ADCLST3
ADC_ADCLST4
ADC_ADSDIS
0xF083
0xF084
0xF085
0xF086
0xF087
Channel List 2
Register
Channel List 3
Register
Channel List 4
Register
Sample Disable
Register
ADSDIS
ADSTAT
Status Register
STAT
RDY
ADC_STAT
ADC_ADSTAT
ADC_ADSTAT
0xF088
0xF089
Conversion Ready
Register
ADC_CNRDY
ADC_ADCNRDY
ADC_ADCNRDY
Limit Status Register
LIMSTAT
ZXSTAT
ADLSTAT
ADC_LIMSTAT
ADC_ZXSTAT
ADC_ADLSTAT
ADC_ADLSTAT
0xF08A
0xF08B
Zero Crossing Status
Register
ADZCSTAT
ADC_ADZCSTAT
ADC_ADZCSTAT
Result 0-7 Registers
Result 8-15 Registers
RSLT0-7
RSLT8-15
LOLIM0-7
ADRSLT0-7
ADC_RSLT0-7
ADC_RSLT8-15
ADC_LOLIM0-7
ADC_ADRSLT0-7
ADC_ADRSLT8-15
ADC_ADLLMT0-7
ADC_ADRSLT0-7
ADC_ADRSLT8-15
ADC_ADLLMT0-7
0xF08C 0XF093
0xF094 0XF09B
0XF09C 0XF0A3
Low Limit 0-7
Registers
ADLLMT0-7
ADHLMT0-7
High Limit 0-7
Registers
HILIM0-7
ADC_HILIM0-7
ADC_ADHLMT0-7
ADC_ADHLMT0-7
0XF0A4 0XF0AB
Offset 0-7 Registers
OFFST0-7
PWR
ADOFS0-7
ADPOWER
ADC_OFFST0-7
ADC_PWR
ADC_ADOFS0-7
ADC_ADPOWER
ADC_ADOFS0-7
ADC_ADPOWER
0XF0AC 0XF0B3
0XF0B4
Power Control
Register
Calibration Register
CAL
ADC_CAL
ADC_ADCAL
ADC_ADCAL
0XF0B5
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
153
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Data Sheet
Memory
Address
Manual
Processor Expert
Register Name
Acronym
New
Legacy
New
Legacy
Start
End
Acronym
Acronym
Acronym
Acronym
Computer Operating Properly (COP) Module
Control Register
Timeout Register
Counter Register
CTRL
TOUT
CNTR
COPCTL
COPTO
COP_CTRL
COP_TOUT
COP_CNTR
COPCTL
COPTO
COPCTL
COPTO
0XF120
0XF121
0XF122
COPCTR
COPCTR
COPCTR
56F8036 Data Sheet, Rev. 3
154
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
Inter-Integrated Circuit Interface (I2C) Module
Control Register
CTRL
TAR
IBCR
I2C_CTRL
I2C_TAR
I2C_IBCR
I2CTAR
I2C_IBCR
I2C_TAR
0xF280
0xF282
Target Address
Register
Slave Address
Register
SAR
DATA
I2C_SAR
I2C_DATA
I2CSAR
I2C_SAR
0xF242
0xF288
0xF28A
Data Buffer &
Command Register
I2C_DATACMD
I2C_SS_SCLHCNT
I2C_DATACMD
I2C_SS_SCLHCNT
Standard Speed
Clock SCL High
Count Register
SSHCNT
I2C_SS_SCL_HCNT
Standard Speed
Clock SCL Low Count
Register
SSLCNT
FSHCNT
FSLCNT
I2C_SS_SCL_LCNT
I2C_FS_SCL_HCNT
I2C_FS_SCL_LCNT
I2C_SS_SCLLCNT
I2C_FS_SCLHCNT
I2C_FS_SCLLCNT
I2C_SS_SCLLCNT
I2C_FS_SCLHCNT
I2C_FS_SCLLCNT
0xF28C
0xF28E
0xF290
Fast Speed Clock
SCL High Count
Register
Fast Speed Clock
SCL Low Count
Register
Interrupt Status
Register
ISTAT
IENBL
RISTAT
RXFT
I2C_INTR_STAT
I2C_INTR_MASK
I2C_INTRSTAT
I2C_INTRMASK
I2C_INTRSTAT
I2C_INTRMASK
I2C_RAW_INTRSTAT
I2C_RXTL
0xF296
0xF298
0xF29A
0xF29C
Interrupt Mask
Register
Raw Interrupt Status
Register
I2C_RAW_INTR_ STAT I2C_RAW_INTRSTAT
I2C_RXTL
Receive FIFO
Threshold Level
Register
Transmit FIFO
Threshold Level
Register
TXFT
I2C_TXTL
I2C_TXTL
0xF29E
0xF2A0
Clear Combined &
Individual Interrupts
Register
CLRINT
I2C_CLRINTR
I2C_CLRINTR
Clear Receive Under
Interrupt Register
CLRRXUND
CLRRXOVR
CLRTXOVR
CLRRDREQ
CLRTXABRT
CLRRXDONE
I2C_CLR_RXUNDER
I2C_CLROVER
I2C_CLR_RXUNDER
I2C_CLROVER
0xF2A2
0xF2A4
0xF2A6
0xF2A8
0xF2AA
0xF2AC
Clear Receive Over
Interrupt Register
Clear Transmit Over
Register
I2C_CLR_TXOVER
I2C_CLR_RDREQ
I2C_CLR_TXABRT
I2C_CLR_RXDONE
I2C_CLR_TXOVER
I2C_CLR_RDREQ
I2C_CLR_TXABRT
I2C_CLR_RXDONE
Clear Read Required
Interrupt Register
Clear Transmit Abort
Interrupt Register
Clear Receive Done
Interrupt Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
155
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Data Sheet
Memory
Address
Manual
Processor Expert
Register Name
Acronym
New
Legacy
New
Legacy
Start
End
Acronym
Acronym
Acronym
Acronym
Clear Activity Interrupt
Register
CLRACT
CLRSTPDET
CLRSTDET
CLRGC
I2C_CLRACTIVITY
I2C_CLR_STOPDET
I2C_CLR_STAR_DET
I2C_CLR_GENCALL
I2C_CLRACTIVITY
I2C_CLR_STOPDET
I2C_CLR_STAR_DET
I2C_CLR_GENCALL
0xF2AE
0xF2B0
0xF2B2
0xF2B4
Clear Stop Detect
Interrupt Register
Clear Start Detect
Interrupt Register
Clear General Call
Interrupt Register
Enable Register
Status Register
ENBL
STAT
I2C_ENABLE
I2C_STAT
I2C_ENABLE
I2C_STAT
0xF2B6
0xF2B8
0xF2BA
Transmit FIFO Level
Register
TXFLR
I2C_TXFLR
I2C_TXFLR
Receive FIFO Level
Register
RXFLR
I2C_RXFLR
I2C_TX_ABRTSRC
I2C_COMPARM1
I2C_COMPARM2
I2C_COMVER1
I2C_COMVER2
I2C_COMTYP1
I2C_COMTYP2
I2C_RXFLR
I2C_TX_ABRTSRC
I2C_COMPARM1
I2C_COMPARM2
I2C_COMVER1
I2C_COMVER2
I2C_COMTYP1
I2C_COMTYP2
0xF2BC
0xF2C0
0xF2FA
0xF2FB
0xF2FC
0xF2FD
0xF2FE
0xF2FF
Transmit Abort
Source Register
TXABRTSRC
COMPARM1
COMPARM2
COMVER1
COMVER2
COMTYP1
COMTYP2
Component
Parameter 1 Register
Component
Parameter 2 Register
Component Version 1
Register
Component Version 2
Register
Component Type 1
Register
Component Type 2
Register
On-Clock Chip Synthesis (OCCS) Module
Control Register
Divide-By Register
Status Register
CTRL
DIVBY
STAT
PLLCR
PLLDB
PLLSR
OSCTL
OCCS_CTRL
OCCS_DIVBY
OCCS_STAT
OCCS_OCTRL
PLLCR
PLLDB
PLLSR
OSCTL
PLLCR
PLLDB
PLLSR
OSCTL
0xF130
0xF131
0xF132
0xF135
Oscillator Control
Register
OCTRL
Clock Check Register
Protection Register
Clock Divider Register
CLKCHK
PROT
OCCS_CLCHK
OCCS_PROT
FM_CLKDIV
FM_CNFG
PLLCLCHK
PLLPROT
FMCLKD
FMCR
OCCS_CLCHK
OCCS_PROT
FMCLKD
0xF136
0xF137
0xF400
0xF401
CLKDIV
CNFG
FMCLKD
FMCR
Configuration
Register
FMCR
Security High Half
Register
SECHI
SECLO
PROT
FMSECH
FMSECL
FMPROT
FM_SECHI
FM_SECLO
FM_PROT
FMSECH
FMSECL
FMPROT
FMSECH
FMSECL
FMPROT
0xF403
0xF404
0xF410
Security Low Half
Register
Protection Register
56F8036 Data Sheet, Rev. 3
156
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
User Status Register
Command Register
Data Buffer Register
USTAT
CMD
FMUSTAT
FMCMD
FMDATA
FMOPT1
FM_USTAT
FM_CMD
FM_DATA
FM_OPT1
FMUSTAT
FMCMD
FMUSTAT
FMCMD
FMDATA
FMOPT1
0xF413
0xF414
0xF418
0xF41B
DATA
OPT1
FMDATA
FMOPT1
Info Optional Data 1
Register
Test Array Signature
Register
TSTSIG
FMTST_SIG
FM_TSTSIG
FMTST_SIG
FMTST_SIG
0xF41D
General Purpose Input/Output (GPIO) Module
x= A (n=0) B (n=1) C (n=2) D (n=3)
Pull-Up Enable
Register
PUPEN
PUR
GPIOx_PUPEN
GPIOx_PUR
GPIO_x_PUR
0xF1n0
Data Register
DATA
DDIR
DR
GPIOx_DATA
GPIOx_DDIR
GPIOx_DR
GPIO_x_DR
0xF1n1
0xF1n2
Data Direction
Register
DDR
GPIOx_DDR
GPIO_x_DDR
Peripheral Enable
Register
PEREN
IASSRT
IEN
PER
IAR
GPIOx_PEREN
GPIOx_IASSRT
GPIOx_IEN
GPIOx_PER
GPIOx_IAR
GPIO_x_PER
GPIO_x_IAR
0xF1n3
0xF1n4
0xF1n5
0xF1n6
0xF1n7
0xF1n8
Interrupt Assert
Register
Interrupt Enable
Register
IENR
IPOLR
IPR
GPIOx_IENR
GPIOx_IPOLR
GPIOx_IPR
GPIO_x_IENR
GPIO_x_IPOLR
GPIO_x_IPR
Interrupt Polarity
Register
IPOL
GPIOx_IPOL
Interrupt Pending
Register
IPEND
IEDGE
GPIOx_IPEND
GPIOx_IEDGE
Interrupt
IESR
GPIOx_IESR
GPIO_x_IESR
Edge-Sensitive
Register
Push-Pull Mode
Registers
PPOUTM
RDATA
DRIVE
PPMODE
RAWDATA
DRIVE
GPIOx_PPOUTM
GPIOx_RDATA
GPIOx_DRIVE
GPIOx_PPMODE
GPIOx_RAWDATA
GPIOx_DRIVE
GPIO_x_PPMODE
GPIO_x_RAWDATA
GPIO_x_DRIVE
0xF1n9
0xF1nA
0xF1nB
Raw Data Input
Register
Output Drive Strength
Register
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
157
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Data Sheet
Memory
Address
Manual
Processor Expert
Register Name
Acronym
New
Legacy
New
Legacy
Start
End
Acronym
Acronym
Acronym
Acronym
Pulse Width Modulator (PWM) Module
Control Register
CTRL
FCTRL
FLTACK
PMCTL
PMFCTL
PMFSA
PWM_CTRL
PWM_FCTRL
PWM_FLTACK
PWM_PMCTL
PWM_PMCTL
PWM_PMFCTL
PWM_PMFSA
0xF0C0
0xF0C1
0xF0C2
Fault Control Register
PWM_PMFCTL
PWM_PMFSA
Fault
Status/Acknowledge
Regis.
Output Control
Register
OUT
PMOUT
PWM_OUT
PWM_PMOUT
PWM_PMOUT
0xF0C3
Counter Register
CNTR
PMCNT
MCM
PWM_CNTR
PWM_CMOD
PWM_PMCNT
PWM_MCM
PWM_PMCNT
PWM_MCM
0xF0C4
0xF0C5
Counter Modulo
Register
CMOD
Value 0-5 Registers
VAL0-5
PMVAL0-5
PWM_VAL0-5
PWM_DTIM0-1
PWM_PMVAL0-5
PWM_PMVAL0-5
0xF0C6 0xF0CB
Deadtime 0-1
Registers
DTIM0-1
PMDEADTM0-1
PWM_PMDEADTM0-1 PWM_PMDEADTM0-1 0xF0CC 0xF0CD
Disable Mapping 1-2
Registers
DMAP1-2
PMDISMAP1-2
PWM_DMAP1-2
PWM_PMDISMAP1-2
PWM_PMDISMAP1-2 0xF0CE 0xF0CF
Configure Register
CNFG
PMCFG
PMCCR
PWM_CNFG
PWM_CCTRL
PWM_PMCFG
PWM_PMCCR
PWM_PMCFG
PWM_PMCCR
0xF0D0
0xF0D1
Channel Control
Register
CCTRL
Port Register
PORT
PMPORT
PMICCR
PWM_PORT
PWM_PMPORT
PWM_PMICCR
PWM_PMPORT
PWM_PMICCR
0xF0D2
0xF0D3
Internal Correction
Control Register
ICCTRL
PWM_ICCTRL
Source Control
Register
SCTRL
SYNC
PMSRC
PWM_SCTRL
PWM_SYNC
PWM_PMSRC
PWM_SYNC
PWM_PMSRC
PWM_SYNC
0xF0D4
0xF0D5
Synchronization
Window Register
Fault Filter 0-3
Register
FFILT0-3
PWM_FFILT0-3
PWM_FFILT0-3
PWM_FFILT0-3
0xF0D6 0xF0D9
Multi-Scalable Controller Area Network (MSCAN) Module
Control 0 Register
CTRL0
CTRL1
BTR0
BTR1
RFLG
RIER
CAN_CTRL0
CAN_CTRL1
CAN_BTR0
CAN_BTR1
CAN_RFLG
CAN_RIER
CANCTRL0
CANCTRL1
CANBTR0
CANBTR1
CANRFLG
CANRIER
0XF800
0XF801
0XF802
0XF803
0XF804
0XF805
Control 1 Register
Bus Timing 0 Register
Bus Timing 1 Register
Receive Flag Register
Receiver Interrupt
Enable Register
Transmitter Flag
Register
TFLG
TIER
CAN_TFLG
CAN_TIER
CAN_TARQ
CANTFLG
CANTIER
CANTARQ
0XF806
0XF807
0XF808
Transmitter Interrupt
Enable Register.
Transmitter Msg Abort
Request Register
TARQ
56F8036 Data Sheet, Rev. 3
158
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
Transmitter Message
Abort Acknowledge
Register
TAAK
CAN_TAAK
CANTAAK
0XF809
Transmitter FIFO
Selection Register
TBSEL
IDAC
CAN_TBSEL
CAN_IDAC
CANTBSEL
CANIDAC
0XF80A
0XF80B
Identifier Acceptance
Control Register
Miscellaneous
Register
MISC
CAN_MISC
CANMISC
0XF80D
Receive Error
Register
RXERR
TXERR
IDAR0-3
IDMR0-3
IDAR4-7
IDMR4-7
RXFG
CAN_RXERR
CAN_TXERR
CAN_IDAR0-3
CANRXERR
CANTXERR
CANIDAR0-3
CANIDMR0-3
CANIDAR4-7
CANIDMR4-7
CANRXFG
CANTXFG
0XF80E
Transmit Error
Register
0XF80F
Identifier Acceptance
0-3 Registers
0xF810 0xF813
0xF814 0xF817
0xF818 0xF81B
0xF81C 0xF81F
0xF82F 0xF820
0xF830 0xF83F
Identifier Mask 0-3
Registers
CAN_IDMR0-3
CAN_IDAR4-7
CAN_IDMR4-7
CAN_RXFG
Identifier Acceptance
4-7 Register
Identifier Mask 4-7
Registers
Foreground Receive
FIFO Register
Foreground Transmit
FIFO Register
TXFG
CAN_TXFG
Power Supervisor (PS) Module
Control Register
Status Register
CTRL
STAT
LVICONTROL
LVISTATUS
PS_CTRL
PS_STAT
LVICONTROL
LVISTATUS
LVICTRL
LVISR
0xF140
0xF141
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
159
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Data Sheet
Memory
Address
Manual
Processor Expert
Acronym
Register Name
New
Legacy
New
Legacy
Acronym
Start
End
Acronym
Acronym
Acronym
Queued Serial Communications Interface (QSCI) Module
n= 0, 1
Baud Rate Register
Control 1 Register
Control 2 Register
Status Register
RATE
CTRL1
CTRL2
STAT
QSCI_RATE
QSCI_CTRL1
QSCI_CTRL2
QSCI_STAT
QSCI_DATA
QSCI_SCIBR
QSCI_SCICR
QSCI_SCICR2
QSCI_SCISR
QSCI_SCIDR
0xF2n0
0xF2n1
0xF2n2
0xF2n3
0xF2n4
Data Register
DATA
Queued Serial Peripheral Interface (QSPI) Module
Status and Control
Register
SCTRL
DSCTRL
DRCV
QSPI_SCTRL
QSPI_SPSCR
QSPI_SPDSR
QSPI_SPDRR
QSPI_SPDTR
0xF2n0
0xF2n1
0xF2n2
0xF2n3
Data Size and Control
Register
QSPI_DSCTRL
QSPI_DRCV
QSPI_DXMIT
Data Receive
Register
Data Transmit
Register
DXMIT
FIFO Control Register
Wait Register
FIFO
QSPI_FIFO
QSPI_WAIT
QSPI_SPFIFO
QSPI_SPWAIT
0xF2n4
0xF2n5
WAIT
Quad-Timer (TMR) Module
n= 0, 1, 2, 3
Compare 1 Register
Compare 2 Register
Capture Register
Load Register
COMP1
COMP2
CAPT
TMRCMP1
TMRCMP2
TMRCAP
TMRn_COMP1
TMRn_COMP2
TMRn_CAPT
TMRn_LOAD
TMRn_HOLD
TMRn_CNTR
TMRn_CTRL
TMRn_SCTRL
TMRn_CMP1
TMRn_CMP2
TMRn_CAP
TMRn_LOAD
TMRn_HOLD
TMRn_CNTR
TMRn_CTRL
TMRn_SCR
TMRn_CMP1
TMRn_CMP2
TMRn_CAP
TMRn_LOAD
TMRn_HOLD
TMRn_CNTR
TMRn_CTRL
TMRn_SCR
0xF0n0
0xF0n1
0xF0n2
0xF0n3
0xF0n4
0xF0n5
0xF0n6
0xF0n7
LOAD
HOLD
CNTR
CTRL
TMRLOAD
TMRHOLD
TMRCNTR
TMRCTRL
TMRSCR
Hold Register
Counter Register
Control Register
Status and Control
Register
SCTRL
Comparator Load 1
Register
CMPLD1
CMPLD2
CSCTRL
TMRCMPLD1
TMRCMPLD2
TMRCOMSCR
TMRn_CMPLD1
TMRn_CMPLD2
TMRn_CSCTRL
TMRn_CMPLD1
TMRn_CMPLD2
TMRn_COMSCR
TMRn_CMPLD1
TMRn_CMPLD2
TMRn_COMSCR
0xF0n8
0xF0n9
0xF0nA
Comparator Load 2
Register
Comparator
Status/Control
Register
Input Filter Register
Enable Register
FILT
TMRn_FILT
TMRn_FILT
TMRn_FILT
0xF0nB
0xF0nF
ENBL
TMRn_ENBL
TMRn_ENBL
TMRn_ENBL
Voltage Regulator (VREG) Module
See SIM section
56F8036 Data Sheet, Rev. 3
160
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
Programmable Interval Timer (PIT) Module
n= 0, 1, 2
Control Register
Modulo Register
Counter Register
CTRL
MOD
CNTR
PITn_CTRL
PITn_MOD
PITn_CNTR
PITCTRL0-2
PITMOD0-2
PITCNTR0-2
PITn_CTRL
PITn_MOD
PITn_CNTR
0xF1n0
0xF1n1
0xF1n2
n= 0, 1
Control Register
Data Register
Step Register
CTRL
DATA
DACn_CTRL
DACn_DATA
DACn_STEP
DACn_MINVAL
DACCTRL0-2
DACDATA0-2
DACSTEP0-2
DACMINVAL0-2
DACn_CTRL
DACn_DATA
DACn_STEP
DACn_MINVAL
0xF1n0
0xF1n1
0xF1n2
0xF1n3
STEP
Minimum Value
Register
MINVAL
Maximum Value
Register
MAXVAL
DACn_MAXVAL
DACMAXVAL0-2
DACn_MAXVAL
0xF1n4
Comparator (CMP) Module
A x = E B x = F
CMPx_CTRL
CMPx_STAT
CMPx_FILT
Control Register
Status Register
Filter Register
CTRL
STAT
FILT
CMP_CTRL
CMP_STAT
CMP_FILT
CMPx_CTRL
0xF1x0
0xF1x1
0xF1x2
CMPx_STAT
CMPx_FILT
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
161
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Data Sheet
Memory
Address
Manual
Processor Expert
Register Name
Acronym
New
Legacy
New
Legacy
Start
End
Acronym
Acronym
Acronym
Acronym
Interrupt Controller (ITCN) Module
Interrupt Priority 0-4
Registers
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ITCN_IPR0-4
ITCN_IPR0-4
INTC_IPR0-4
INTC_VBA
0XF060 0XF064
0XF065
Vector Base Address
Register
ITCN_VBA
ITCN_VBA
ITCN_FIM0
Fast Interrupt Match 0
Register
ITCN_FIM0
INTC_FIM0
0XF066
Fast Interrupt Vector
Address Low 0
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
ITCN_FIVAL0
ITCN_FIVAH0
ITCN_FIM1
INTC_FIVAL0
INTC_FIVAH0
INTC_FIM1
0XF067
Fast Interrupt Vector
Address High 0
0XF068
Fast Interrupt Match 1
Register
0xF069
Fast Interrupt Vector
Address Low 1
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
ITCN_FIVAL1
ITCN_FIVAH1
ITCN_IRQP0
ITCN_IRQP1
ITCN_IRQP2
INTC_FIVAL1
INTC_FIVAH1
INTC_IRQP0
INTC_IRQP1
INTC_IRQP2
0xF06A
Fast Interrupt Vector
Address High 1
0xF06B
Interrupt Pending 0
Register
0xF06C
Interrupt Pending 1
Register
0xF06D
Interrupt Pending 2
Register
0xF06E
System Integration Module (SIM)
Control Register
N/A
N/A
N/A
N/A
N/A
N/A
SIM_CTRL
SIM_RSTAT
SIM_SWC0-3
SIM_CONTROL
SIM_CONTROL
SIM_RSTSTS
SIM_SCR0-3
0xF100
0xF101
Reset Status Register
SIM_RSTSTS
SIM_SCR0-3
Software Control 0-3
Registers
0xF102 0xF105
Most Significant Half
JTAG ID
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SIM_MSHID
SIM_LSHID
SIM_PWR
SIM_MSH_ID
SIM_LSH_ID
SIM_POWER
SIM_CLKOSR
SIM_PCR
SIM_MSH_ID
SIM_LSH_ID
0xF106
0xF107
Least Significant Half
JTAG ID
Power Control
Register
0xF108
Clock Out Select
Register
SIM_CLKOUT
SIM_PCR
SIM_CLKOSR
SIM_PCR
0xF10A
Peripheral Clock Rate
Register
0xF10B
Peripheral Clock
Enable 0-1 Register
SIM_PCE0-1
SIM_SD0-1
SIM_PCE0-1
SIM_SD0-1
SIM_PCE0-1
SIM_SD0-1
0xF10C 0xF10D
0xF10E 0xF10F
Peripheral Stop
Disable 0-1 Register
56F8036 Data Sheet, Rev. 3
162
FreescaleSemiconductor
Preliminary
Electrical Design Considerations
Table 14-1 Legacy and Revised Acronyms (Continued)
Peripheral Reference
Manual
Memory
Address
Data Sheet
Processor Expert
Acronym
Register Name
New
Legacy
New
Acronym
Legacy
Acronym
Start
End
Acronym
Acronym
I/O Short Address
Location High
Register
N/A
N/A
SIM_ISALH
SIM_ISALH
SIM_ISALH
SIM_ISALL
0xF110
I/O Short Address
N/A
N/A
SIM_ISALL
SIM_ISALL
0xF111
Location Low Register
Protection Register
N/A
N/A
N/A
N/A
SIM_PROT
SIM_PROT
SIM_PROT
0xF112
0xF113
GPIOA Peripheral
Select 0 Register
SIM_GPISA0
SIM_GPISA0
SIM_GPISA0
GPIOA Peripheral
Select 0 Register
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
SIM_GPSA1
SIM_GPSB0
SIM_GPSB1
SIM_GPSCD
0xF114
0xF115
0xF116
0xF117
GPIOB Peripheral
Select 0 Register
GPIOB Peripheral
Select 1 Register
GPIO Perip. Select
Register for GPIO C &
D
Internal Peripheral.
Select Register for
PWM
N/A
N/A
N/A
N/A
N/A
N/A
SIM_ISPWM
SIM_IPSDAC
SIM_ISPWM
SIM_IPSDAC
SIM_IPSTMRA
SIM_ISPWM
SIM_IPSDAC
SIM_IPSTMRA
0xF118
0xF119
0xF11A
Internal Peripheral
Select Register for
DAC
Internal Peripheral
Select Register for
TMRA
SIM_IPSTMRA
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
163
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© Freescale Semiconductor, Inc. 2006. All rights reserved.
MC56F8036
Rev. 3
01/2007
相关型号:
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