MC68C812A4 [FREESCALE]
Technical Supplement MC68C812A4 3.3V Electrical Characteristics; 技术补充MC68C812A4 3.3V电气特性
| 型号： | MC68C812A4 |
| 厂家： | 
Freescale |
| 描述： | Technical Supplement MC68C812A4 3.3V Electrical Characteristics |
| 文件： | 总18页 (文件大小：766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
7/28/98
Technical Supplement
MC68C812A4 3.3V Electrical Characteristics
The MC68C812A4 is the low-voltage version of the standard MC68HC812A4 microcontroller unit
(MCU), a 16-bit device composed of standard on-chip peripheral modules connected by an intermodule
bus. Modules include a 16-bit central processing unit (CPU12), a Lite integration module (LIM), two
asynchronous serial communications interfaces (SCI0 and SCI1), a serial peripheral interface (SPI), a
timer and pulse accumulation module, an 8-bit analog-to-digital converter (ATD), 1-Kbyte RAM, 4-Kbyte
EEPROM, and memory expansion logic with chip selects, key wakeup ports, and a phase-locked loop
(PLL).
This supplement contains the most accurate electrical information for the MC68C812A4 microcontroller
available at the time of publication. The information should be considered preliminary and is subject to
change. The following characteristics are contained in this document:
Table 1 Maximum Ratings
Table 2 Thermal Characteristics
Table 3 DC Electrical Characteristics
Table 4 Supply Current
Table 5 ATD Maximum Ratings
Table 6 ATD DC Electrical Characteristics
Table 7 Analog Converter Characteristics (Operating)
Table 8 ATD AC Characteristics (Operating)
Table 9 EEPROM Characteristics
Table 10 Control Timing
Table 11 Peripheral Port Timing
Table 12 Non-Multiplexed Expansion Bus Timing
Table 13 SPI Timing
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1
Table 1 Maximum Ratings
Rating
Symbol
, V
Value
Unit
V
V
,
DD DDA
Supply voltage
Input voltage
−0.3 to +6.5
−0.3 to +6.5
V
DDX
V
V
IN
2
Operating temperature range
MC68C812A4PV5
T to T
L H
0 to +70
T
°C
°C
mA
V
A
stg
IN
Storage temperature range
T
−55 to +150
3
Current drain per pin
I
±25
Excluding V and V
DD
SS
V
differential voltage
V
−V
DDX
6.5
DD
DD
NOTES:
1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or cur-
rents in excess of recommended values affects device reliability. Device modules may not operate
normally while being exposed to electrical extremes.
2. Refer to MC68HC812A4TS/D Technical Summary for complete part numbers.
3. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the in-
puts against damage caused by high static voltages or electric fields; however, normal precautions
are necessary to avoid application of any voltage higher than maximum-rated voltages to this high-
impedance circuit. Extended operation at the maximum ratings can adversely affect device reli-
ability. Tying unused inputs to an appropriate logic voltage level (either GND or V ) enhances
DD
reliability of operation.
Table 2 Thermal Characteristics
Characteristic
Average junction temperature
Symbol
Value
+ (P × Θ )
JA
Unit
°C
T
T
J
A
D
Ambient temperature
T
User-determined
39
°C
A
Package thermal resistance (junction-to-ambient)
112-pin thin quad flat pack (TQFP)
Θ
°C/W
JA
P
+ P
I/O
INT
or
1
Total power dissipation
P
W
D
K
-------------------------
TJ
+
273°C
Device internal power dissipation
P
I
× V
DD
W
W
INT
DD
2
I/O pin power dissipation
P
User-determined
I/O
P
× (T + 273°C) +
3
D
A
A constant
K
W · °C
2
Θ
× P
JA
D
NOTES:
1. This is an approximate value, neglecting P
.
I/O
2. For most applications P « P
and can be neglected.
I/O
INT
3. K is a constant pertaining to the device. Solve for K with a known T and a measured P (at equilibrium). Use
A
D
this value of K to solve for P and T iteratively for any value of T .
D
J
A
2
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Table 3 DC Electrical Characteristics
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , unless otherwise noted
SS A L H
DD
Characteristic
Symbol
Min
Max
V + 0.3
DD
Unit
V
Input high voltage, all inputs
Input low voltage, all inputs
V
0.7 × V
IH
DD
V
V
−0.3
0.2 × V
DD
V
IL
SS
Output high voltage All I/O and output pins
Normal drive strength
I
I
= −10.0 µA
= −0.8 mA
V
V
− 0.2
− 0.8
—
—
V
V
OH
OH
DD
DD
V
OH
Reduced drive strength
I
I
= −4.0 µA
= −0.3 mA
V
V
− 0.2
− 0.8
—
—
V
V
OH
OH
DD
DD
Output low voltage, All I/O and output pins, normal drive strength
I
I
= 10.0 µA
= 1.6 mA
—
—
V
V
+0.2
+0.4
V
V
OL
OL
SS
SS
V
I
OL
EXTAL, PAD[7:0], V , V , V , XIRQ, reduced drive strength
RH
RL
FP
I
I
= 3.6 µA
= 0.6 mA
—
—
V
V
+0.2
+0.4
V
V
OL
OL
SS
SS
1
Input leakage current all inputs except IRQ, PAD7, and XFC
= V or V IRQ, PAD7, XFC
—
—
±1
±10
µA
µA
in
V
in
DD
SS
Three-state leakage, I/O ports, BKGD, and RESET
I
—
±2.5
µA
OZ
Input capacitance
All input pins and ATD pins (non-sampling)
ATD pins (sampling)
All I/O pins
—
—
—
10
15
20
pF
pF
pF
C
in
Output load capacitance
All outputs except PS[7:4]
PS[7:4]
C
—
—
90
130
pF
pF
L
Active pull-up, pull-down current
IRQ, XIRQ, ECLK, LSTRB, R/W , BKGD, MODA, MODB, ARST
Ports A, B, C, D, F, G, H, J, S, T
I
50
500
µA
APU
RAM standby voltage, power down
RAM standby current
NOTES:
V
2.0
—
—
1
V
SB
I
mA
SB
1. Specification is for parts in the 0 to +70°C range. Higher temperature ranges will result in increased current
leakage.
3
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Table 4 Supply Current
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
Characteristic
Symbol
4 MHz
5 MHz Unit
Maximum total supply current
RUN:
Single-chip mode
Expanded mode
I
15
21
17
25
mA
mA
DD
WAIT: (All peripheral functions shut down)
Single-chip mode
W
3
3
3.5
3.5
mA
mA
IDD
Expanded mode
STOP:
Single-chip mode, no clocks
S
250
250
µA
IDD
1
Maximum power dissipation
Single-chip mode
Expanded mode
P
54
76
62
90
mW
mW
D
NOTES:
1. Includes I and I
.
DD
DDA
Note: I is tested with a rail-to-rail square wave on EXTAL
DD
Table 5 ATD Maximum Ratings
Characteristic
ATD reference voltage
Symbol
Value
Units
V
V
≤ V
≥ V
V
RH
−0.3 to +6.5
−0.3 to +6.5
V
V
RH
RL
DDA
SSA
V
RL
V
V
V
differential voltage
differential voltage
|V −V |
SSA
0.1
V
SS
SS
|V −V
|
6.5
6.5
V
V
DD
DDA
DDX
DD
V
−V
DD
differential voltage
|V −V |
RL
6.5
V
REF
RH
|V −V
|
|
6.5
6.5
V
V
RH
DDA
Reference to supply differential voltage
|V −V
RL
SSA
4
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Table 6 ATD DC Electrical Characteristics
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , ATD Clock = 2 MHz, unless
SS A L H
DD
otherwise noted
Characteristic
Symbol
Min
Max
3.6
Unit
V
Analog supply voltage
Analog supply current
Reference voltage, low
Reference voltage, high
V
3.0
DDA
DDA
Normal operation
I
1.0
mA
V
V
V
V
/2
DDA
RL
SSA
V
V
/2
V
V
RH
DDA
DDA
1
V
differential reference voltage
V
−V
RL
3.0
3.6
V
REF
RH
2
Input voltage
Input current, off channel
V
I
V
V
V
INDC
OFF
REF
SSA
DDA
3
100
nA
µA
Reference supply current
Input capacitance
I
250
Not Sampling
Sampling
C
C
10
15
pF
pF
INN
INS
NOTES:
1. Accuracy is guaranteed at V − V = 3.3 Vdc ± 0.3V.
RH
RL
2. To obtain full-scale, full-range results, V
≤ V ≤ V
≤ V ≤ V
.
SSA
RL
INDC
RH
DDA
3. Maximum leakage occurs at maximum operating temperature. Current decreases by ap-
proximately one-half for each 10°C decrease from maximum temperature.
5
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Table 7 Analog Converter Characteristics (Operating)
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , ATD Clock = 2 MHz, unless otherwise noted
SS A L H
DD
Characteristic
Symbol
2 counts
DNL
Min
Typical
Max
Unit
mV
1
8-bit resolution
24
2
Differential non-linearity
−0.5
−1
+0.5
+1
count
count
count
KΩ
2
Integral non-linearity
INL
2,3
Absolute error
2, 4, 8, and 16 ATD sample clocks
AE
−2
+2
4
Maximum source impedance
NOTES:
R
20
See note
S
1. V − V ≥ 3.072V
RH
RL
2. At V
= 3.072V, one 8-bit count = 12 mV.
REF
3. Eight-bit absolute error of 2 counts (24 mV) includes 1/2 count (6 mV) inherent quantization error and 1 1/2
counts (18 mV) circuit (differential, integral, and offset) error.
4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction
leakage into the pin and on leakage due to charge-sharing with internal capacitance.
Error from junction leakage is a function of external source impedance and input leakage current. Expected error
in result value due to junction leakage is expressed in voltage (V
):
ERRJ
V
= R × I
S OFF
ERRJ
where I
is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of
OFF
ATD clock speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge
pump leakage is computed as follows:
V
= .25pF × V
× R × ATDCLK/(8 × number of channels)
ERRJ
DDA S
Table 8 ATD AC Characteristics (Operating)
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , ATD Clock = 2 MHz, unless
SS A L H
DD
otherwise noted
Characteristic
Symbol
Min
Max
Unit
ATD operating clock frequency
Conversion time per channel
f
0.5
2.0
MHz
ATDCLK
0.5 MHz ≤ f
≤ 2 MHz
18 ATD clocks
32 ATD clocks
ATDCLK
t
CONV
9.0
16.0
32.0
60.0
µs
µs
Stop recovery time
V
= 3.3V
t
50
µs
DDA
SR
6
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Table 9 EEPROM Characteristics
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
Characteristic
Symbol
Min
Typical
Max
Unit
MHz
ms
1
Minimum programming clock frequency
Programming time
f
t
3.0
PROG
PROG
20
Clock recovery time following STOP, to continue programming
t
t
+ 1
ms
CRSTOP
PROG
Erase time
t
20
ms
ERASE
Write/erase endurance
Data retention
NOTES:
10,000 30,000
10
cycles
years
1. RC oscillator must be enabled if programming is desired and f
< f
.
SYS
PROG
Table 10 Control Timing
Characteristic
Symbol
5.0 MHz
Unit
Min
Max
5.0
Frequency of operation
E-clock period
f
dc
200
—
MHz
ns
o
t
—
cyc
Crystal frequency
f
10.0
10.0
—
MHz
MHz
ns
XTAL
External oscillator frequency
Processor control setup time
2f
dc
o
t
= t /2+ 30
t
PCSU
130
PCSU
cyc
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be preempted by internal reset)
PW
32
2
—
—
t
t
RSTL
cyc
cyc
Mode programming setup time
t
4
—
—
t
MPS
cyc
Mode programming hold time
t
10
ns
ns
MPH
Interrupt pulse width, IRQ, edge-sensitive mode, KWU
PW
420
—
—
4
IRQ
PW
= 2t + 20
IRQ
cyc
Wait recovery startup time
Timer pulse width, input capture pulse accumulator input
t
t
cyc
WRS
PW
420
—
ns
TIM
PW = 2t + 20
TIM
cyc
7
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1
2
PT[7:0]
PW
TIM
PT[7:0]
1
PT7
PW
PA
2
PT7
NOTES
:
1. Rising edge sensitive input
2. Falling edge sensitive input
TIMER INPUT TIMING
Figure 1 Timer Inputs
8
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1
E
3
P
P
2
P
1
P
F
M HP
t
F
Figure 2 POR and External Reset Timing Diagram
9
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1
E
3
P
2
P
1
1
P
E
O TP
F
STOP RECOVERY TIM
Figure 3 STOP Recovery Timing Diagram
10
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1
E
3
P
2
P
S
P
F
W SR
t
V
A
WAIT RECOVERY TIM
Figure 4 WAIT Recovery Timing Diagram
11
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1
E
P
F
3
P
C
S
B
INTERRUPT TIM
Figure 5 Interrupt Timing Diagram
12
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Table 11 Peripheral Port Timing
Characteristic
Symbol
5.0 MHz
Unit
Min
Max
5.0
—
Frequency of operation (E-clock frequency)
E-clock period
f
dc
MHz
ns
o
t
200
cyc
Peripheral data setup time
MCU read of ports
t
130
0
—
—
40
ns
ns
ns
PDSU
t
= t /2 + 30
PDSU cyc
Peripheral data hold time
MCU read of ports
t
PDH
Delay time, peripheral data write
MCU write to ports
t
—
PWD
MCU READ OF PORT
ECLK
t
t
PDSU
PDH
PORTS
PORT RD TIM
Figure 6 Port Read Timing Diagram
MCU WRITE TO PORT
ECLK
t
PWD
PREVIOUS PORT DATA
NEW DATA VALID
PORT A
PORT WR TIM
Figure 7 Port Write Timing Diagram
13
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Table 12 Non-Multiplexed Expansion Bus Timing
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , unless otherwise noted
DD
SS
A
L
H
1
Num
Characteristic
Delay Symbol
5 MHz
Unit
Min Max
Frequency of operation (E-clock frequency)
f
dc
200
98
98
—
5.0 MHz
o
1
2
3
5
6
7
Cycle time
t
= 1/f
t
cyc
—
—
—
79
—
—
—
—
75
—
—
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
o
Pulse width, E low
Pulse width, E high
Address delay time
Address hold time
PW = t /2 + delay
−2
−2
29
—
—
—
—
25
—
—
20
PW
EL
EL
cyc
2
PW = t /2 + delay
PW
EH
EH
AD
cyc
t
= t /4 + delay
t
t
cyc
AD
AH
20
28
30
0
Address valid time to E rise
t
= PW − t
t
AV
AV
EL
AD
11 Read data setup time
12 Read data hold time
13 Write data delay time
14 Write data hold time
t
DSR
DHR
t
t
= t /4 + delay
t
t
—
DDW
cyc
DDW
DHW
20
23
—
2
15 Write data setup time
16 Read/write delay time
t
= PW − t
t
DSW
EH
DDW
DSW
RWD
t
= t /4 + delay
t
RWD
cyc
Read/write valid time to E rise
17
—
t
28
—
ns
RWV
RWH
t
= PW − t
EL RWD
RWV
18 Read/write hold time
19 Low strobe delay time
—
t
20
—
—
ns
ns
t
= t /4 + delay
20
t
LSD
70
LSD
cyc
Low strobe valid time to E rise
20
—
t
28
—
ns
LSV
LSH
t
= PW − t
EL
LSV
LSD
21 Low strobe hold time
22 Address access time
—
—
—
29
t
20
—
—
—
—
100
68
ns
ns
ns
ns
2
t
= t − t − t
t
t
ACCA
cyc
AD
DSR
ACCA
ACCE
2
23 Access time from E rise
26 Chip select delay time
t
= PW − t
ACCE EH DSR
t
= t /4 + delay
t
CSD
79
CSD
cyc
2
Chip select access time
27
—
t
—
100
ns
ACCS
t
= t − t
− t
ACCS
cyc
CSD DSR
28 Chip select hold time
—
5
t
t
0
10
—
ns
ns
CSH
29 Chip select negated time
NOTES:
t
= t /4 + delay
55
CSN
cyc
CSN
1. All timings are calculated for normal port drives.
2. This characteristic is affected by clock stretch.
Add N × t where N = 0, 1, 2, or 3, depending on the number of clock stretches.
cyc
14
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1
2
3
ECLK
22
7
6
5
ADDR[15:0]
23
11
12
DATA[15:0]
READ
13
15
14
DATA[15:0]
WRITE
16
19
17
20
18
R/W
21
29
LSTRB
(W/O TAG ENABLED)
26
27
28
CS
NOTE: Measurement points shown are 20% and 70% of V
DD
BUS TIM
Figure 8 Non-Multiplexed Expansion Bus Timing Diagram
15
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Table 13 SPI Timing
1
V
= 3.3 Vdc ± 0.3V, V = 0 Vdc, T = T to T , 130 pF load on all SPI pins
SS
A
L
H
DD
Num
Function
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
E-clock
frequency
f
DC
DC
1/2
1/2
op
SCK Period
Master
Slave
1
2
3
4
5
6
7
t
2
2
256
—
t
t
sck
cyc
cyc
Enable Lead Time
Master
Slave
t
1/2
1
—
—
t
t
lead
sck
cyc
Enable Lag Time
Master
Slave
t
1/2
1
—
—
t
t
lag
sck
cyc
Clock (SCK) High or Low Time
Master
Slave
t
t
t
− 60
− 30
128 t
—
ns
ns
wsck
cyc
cyc
cyc
Sequential Transfer Delay
Master
Slave
t
1/2
1
—
—
t
t
td
sck
cyc
Data Setup Time (Inputs)
Master
Slave
t
30
30
—
—
ns
ns
su
Data Hold Time (Inputs)
Master
Slave
t
0
30
—
—
ns
ns
hi
8
9
Slave Access Time
t
—
—
1
1
t
a
cyc
cyc
Slave MISO Disable Time
t
t
dis
Data Valid (after SCK Edge)
10
11
12
13
Master
Slave
t
—
—
50
50
ns
ns
v
Data Hold Time (Outputs)
Master
Slave
t
0
0
—
—
ns
ns
ho
Rise Time
Input
Output
t
—
—
t
t
− 30
ns
ns
ri
cyc
t
30
ro
Fall Time
Input
Output
t
—
—
− 30
30
ns
ns
fi
cyc
t
fo
NOTES:
1. All AC timing is shown with respect to 20% V and 70% V levels unless otherwise noted.
DD
DD
16
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1
SS
(OUTPUT)
5
2
1
12
13
3
SCK
= 0)
4
(CPOL
(OUTPUT)
4
SCK
= 1)
(CPOL
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 .
. . 1
MSB IN
LSB IN
10
10
11
MOSI
(OUTPUT)
2
BIT 6 .
. . 1
LSB OUT
MSB OUT
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SPI MASTER CPHA0
A) SPI Master Timing (CPHA = 0)
1
SS
(OUTPUT)
5
1
13
12
12
13
3
2
SCK
(CPOL
= 0)
(OUTPUT)
4
4
SCK
(CPOL
= 1)
(OUTPUT)
6
7
MISO
(INPUT)
2
MSB IN
BIT 6 .
11
BIT 6 .
.
. 1
LSB IN
10
MOSI
(OUTPUT)
2
PORT DATA
.
. 1
MASTER LSB OUT
PORT DATA
MASTER MSB OUT
1. SS output mode (DDS7 = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
SPI MASTER CPHA1
B) SPI Master Timing (CPHA = 1)
Figure 9 SPI Timing Diagram (1 of 2)
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SS
(INPUT)
5
1
13
12
12
13
3
SCK
= 0)
(CPOL
(INPUT)
4
4
2
SCK
= 1)
(CPOL
(INPUT)
9
8
10
11
11
MISO
(OUTPUT)
SEE
NOTE
BIT 6 .
. . 1
SLAVE LSB OUT
MSB OUT
7
SLAVE
6
MOSI
(INPUT)
BIT 6 .
.
. 1
MSB IN
LSB IN
NOTE: Not defined but normally MSB of character just received.
SPI SLAVE CPHA0
A) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
5
3
1
13
12
13
2
SCK
= 0)
(CPOL
(INPUT)
4
4
12
11
SCK
= 1)
(CPOL
(INPUT)
9
10
MISO
(OUTPUT)
SEE
BIT 6 .
.
. 1
SLAVE LSB OUT
LSB IN
SLAVE
6
MSB OUT
7
NOTE
8
MOSI
(INPUT)
MSB IN
BIT 6 .
. . 1
NOTE: Not defined but normally LSB of character just received.
SPI SLAVE CPHA1
B) SPI Slave Timing (CPHA = 1)
Figure 10 SPI Timing Diagram (2 of 2)
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